xref: /freebsd/sys/powerpc/mpc85xx/mpc85xx.c (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (C) 2008 Semihalf, Rafal Jaworowski
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include "opt_platform.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/reboot.h>
38 #include <sys/rman.h>
39 
40 #include <vm/vm.h>
41 #include <vm/vm_param.h>
42 #include <vm/pmap.h>
43 
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/machdep.h>
47 #include <machine/pio.h>
48 #include <machine/spr.h>
49 
50 #include <dev/fdt/fdt_common.h>
51 
52 #include <dev/fdt/fdt_common.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55 #include <dev/ofw/openfirm.h>
56 
57 #include <powerpc/mpc85xx/mpc85xx.h>
58 
59 /*
60  * MPC85xx system specific routines
61  */
62 
63 uint32_t
64 ccsr_read4(uintptr_t addr)
65 {
66 	volatile uint32_t *ptr = (void *)addr;
67 
68 	return (*ptr);
69 }
70 
71 void
72 ccsr_write4(uintptr_t addr, uint32_t val)
73 {
74 	volatile uint32_t *ptr = (void *)addr;
75 
76 	*ptr = val;
77 	powerpc_iomb();
78 }
79 
80 int
81 law_getmax(void)
82 {
83 	uint32_t ver;
84 	int law_max;
85 
86 	ver = SVR_VER(mfspr(SPR_SVR));
87 	switch (ver) {
88 	case SVR_MPC8555:
89 	case SVR_MPC8555E:
90 		law_max = 8;
91 		break;
92 	case SVR_MPC8533:
93 	case SVR_MPC8533E:
94 	case SVR_MPC8548:
95 	case SVR_MPC8548E:
96 		law_max = 10;
97 		break;
98 	case SVR_P5020:
99 	case SVR_P5020E:
100 	case SVR_P5021:
101 	case SVR_P5021E:
102 	case SVR_P5040:
103 	case SVR_P5040E:
104 		law_max = 32;
105 		break;
106 	default:
107 		law_max = 8;
108 	}
109 
110 	return (law_max);
111 }
112 
113 static inline void
114 law_write(uint32_t n, uint64_t bar, uint32_t sr)
115 {
116 
117 	if (mpc85xx_is_qoriq()) {
118 		ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
119 		ccsr_write4(OCP85XX_LAWBARL(n), bar);
120 		ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
121 		ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
122 	} else {
123 		ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
124 		ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
125 		ccsr_read4(OCP85XX_LAWSR_85XX(n));
126 	}
127 
128 	/*
129 	 * The last write to LAWAR should be followed by a read
130 	 * of LAWAR before any device try to use any of windows.
131 	 * What more the read of LAWAR should be followed by isync
132 	 * instruction.
133 	 */
134 
135 	isync();
136 }
137 
138 static inline void
139 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
140 {
141 
142 	if (mpc85xx_is_qoriq()) {
143 		*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
144 		    ccsr_read4(OCP85XX_LAWBARL(n));
145 		*sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
146 	} else {
147 		*bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
148 		*sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
149 	}
150 }
151 
152 static int
153 law_find_free(void)
154 {
155 	uint32_t i,sr;
156 	uint64_t bar;
157 	int law_max;
158 
159 	law_max = law_getmax();
160 	/* Find free LAW */
161 	for (i = 0; i < law_max; i++) {
162 		law_read(i, &bar, &sr);
163 		if ((sr & 0x80000000) == 0)
164 			break;
165 	}
166 
167 	return (i);
168 }
169 
170 #define	_LAW_SR(trgt,size)	(0x80000000 | (trgt << 20) | \
171 				(flsl(size + (size - 1)) - 2))
172 
173 int
174 law_enable(int trgt, uint64_t bar, uint32_t size)
175 {
176 	uint64_t bar_tmp;
177 	uint32_t sr, sr_tmp;
178 	int i, law_max;
179 
180 	if (size == 0)
181 		return (0);
182 
183 	law_max = law_getmax();
184 	sr = _LAW_SR(trgt, size);
185 
186 	/* Bail if already programmed. */
187 	for (i = 0; i < law_max; i++) {
188 		law_read(i, &bar_tmp, &sr_tmp);
189 		if (sr == sr_tmp && bar == bar_tmp)
190 			return (0);
191 	}
192 
193 	/* Find an unused access window. */
194 	i = law_find_free();
195 
196 	if (i == law_max)
197 		return (ENOSPC);
198 
199 	law_write(i, bar, sr);
200 	return (0);
201 }
202 
203 int
204 law_disable(int trgt, uint64_t bar, uint32_t size)
205 {
206 	uint64_t bar_tmp;
207 	uint32_t sr, sr_tmp;
208 	int i, law_max;
209 
210 	law_max = law_getmax();
211 	sr = _LAW_SR(trgt, size);
212 
213 	/* Find and disable requested LAW. */
214 	for (i = 0; i < law_max; i++) {
215 		law_read(i, &bar_tmp, &sr_tmp);
216 		if (sr == sr_tmp && bar == bar_tmp) {
217 			law_write(i, 0, 0);
218 			return (0);
219 		}
220 	}
221 
222 	return (ENOENT);
223 }
224 
225 int
226 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
227 {
228 	u_long start;
229 	uint32_t ver;
230 	int trgt, rv;
231 
232 	ver = SVR_VER(mfspr(SPR_SVR));
233 
234 	start = rman_get_start(res) & 0xf000;
235 
236 	rv = 0;
237 	trgt = -1;
238 	switch (start) {
239 	case 0x0000:
240 	case 0x8000:
241 		trgt = 0;
242 		break;
243 	case 0x1000:
244 	case 0x9000:
245 		trgt = 1;
246 		break;
247 	case 0x2000:
248 	case 0xa000:
249 		if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
250 			trgt = 3;
251 		else
252 			trgt = 2;
253 		break;
254 	case 0x3000:
255 	case 0xb000:
256 		if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
257 			rv = EINVAL;
258 		else
259 			trgt = 3;
260 		break;
261 	default:
262 		rv = ENXIO;
263 	}
264 	if (rv == 0) {
265 		*trgt_mem = trgt;
266 		*trgt_io = trgt;
267 	}
268 	return (rv);
269 }
270 
271 static void
272 l3cache_inval(void)
273 {
274 
275 	/* Flash invalidate the CPC and clear all the locks */
276 	ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
277 	    OCP85XX_CPC_CSR0_LFC);
278 	while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
279 	    OCP85XX_CPC_CSR0_LFC))
280 		;
281 }
282 
283 static void
284 l3cache_enable(void)
285 {
286 
287 	ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
288 	    OCP85XX_CPC_CSR0_PE);
289 	/* Read back to sync write */
290 	ccsr_read4(OCP85XX_CPC_CSR0);
291 }
292 
293 void
294 mpc85xx_enable_l3_cache(void)
295 {
296 	uint32_t csr, size, ver;
297 
298 	/* Enable L3 CoreNet Platform Cache (CPC) */
299 	ver = SVR_VER(mfspr(SPR_SVR));
300 	if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
301 	    ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
302 		csr = ccsr_read4(OCP85XX_CPC_CSR0);
303 		if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
304 			l3cache_inval();
305 			l3cache_enable();
306 		}
307 
308 		csr = ccsr_read4(OCP85XX_CPC_CSR0);
309 		if ((boothowto & RB_VERBOSE) != 0 ||
310 		    (csr & OCP85XX_CPC_CSR0_CE) == 0) {
311 			size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
312 			printf("L3 Corenet Platform Cache: %d KB %sabled\n",
313 			    size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
314 			    "dis" : "en");
315 		}
316 	}
317 }
318 
319 int
320 mpc85xx_is_qoriq(void)
321 {
322 	uint16_t pvr = mfpvr() >> 16;
323 
324 	/* QorIQ register set is only in e500mc and derivative core based SoCs. */
325 	if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
326 		return (1);
327 
328 	return (0);
329 }
330 
331 uint32_t
332 mpc85xx_get_platform_clock(void)
333 {
334 	phandle_t soc;
335 	static uint32_t freq;
336 
337 	if (freq != 0)
338 		return (freq);
339 
340 	soc = OF_finddevice("/soc");
341 
342 	/* freq isn't modified on error. */
343 	OF_getencprop(soc, "bus-frequency", (void *)&freq, sizeof(freq));
344 
345 	return (freq);
346 }
347 
348 uint32_t
349 mpc85xx_get_system_clock(void)
350 {
351 	uint32_t freq;
352 
353 	freq = mpc85xx_get_platform_clock();
354 
355 	return (freq / 2);
356 }
357