1 /*- 2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_platform.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/reboot.h> 36 #include <sys/rman.h> 37 38 #include <vm/vm.h> 39 #include <vm/vm_param.h> 40 #include <vm/pmap.h> 41 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/machdep.h> 45 #include <machine/pio.h> 46 #include <machine/spr.h> 47 48 #include <dev/fdt/fdt_common.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 #include <dev/ofw/openfirm.h> 54 55 #include <powerpc/mpc85xx/mpc85xx.h> 56 57 58 /* 59 * MPC85xx system specific routines 60 */ 61 62 uint32_t 63 ccsr_read4(uintptr_t addr) 64 { 65 volatile uint32_t *ptr = (void *)addr; 66 67 return (*ptr); 68 } 69 70 void 71 ccsr_write4(uintptr_t addr, uint32_t val) 72 { 73 volatile uint32_t *ptr = (void *)addr; 74 75 *ptr = val; 76 powerpc_iomb(); 77 } 78 79 int 80 law_getmax(void) 81 { 82 uint32_t ver; 83 int law_max; 84 85 ver = SVR_VER(mfspr(SPR_SVR)); 86 switch (ver) { 87 case SVR_MPC8555: 88 case SVR_MPC8555E: 89 law_max = 8; 90 break; 91 case SVR_MPC8533: 92 case SVR_MPC8533E: 93 case SVR_MPC8548: 94 case SVR_MPC8548E: 95 law_max = 10; 96 break; 97 case SVR_P5020: 98 case SVR_P5020E: 99 law_max = 32; 100 break; 101 default: 102 law_max = 8; 103 } 104 105 return (law_max); 106 } 107 108 static inline void 109 law_write(uint32_t n, uint64_t bar, uint32_t sr) 110 { 111 112 if (mpc85xx_is_qoriq()) { 113 ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32); 114 ccsr_write4(OCP85XX_LAWBARL(n), bar); 115 ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr); 116 ccsr_read4(OCP85XX_LAWSR_QORIQ(n)); 117 } else { 118 ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12); 119 ccsr_write4(OCP85XX_LAWSR_85XX(n), sr); 120 ccsr_read4(OCP85XX_LAWSR_85XX(n)); 121 } 122 123 /* 124 * The last write to LAWAR should be followed by a read 125 * of LAWAR before any device try to use any of windows. 126 * What more the read of LAWAR should be followed by isync 127 * instruction. 128 */ 129 130 isync(); 131 } 132 133 static inline void 134 law_read(uint32_t n, uint64_t *bar, uint32_t *sr) 135 { 136 137 if (mpc85xx_is_qoriq()) { 138 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 | 139 ccsr_read4(OCP85XX_LAWBARL(n)); 140 *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n)); 141 } else { 142 *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12; 143 *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n)); 144 } 145 } 146 147 static int 148 law_find_free(void) 149 { 150 uint32_t i,sr; 151 uint64_t bar; 152 int law_max; 153 154 law_max = law_getmax(); 155 /* Find free LAW */ 156 for (i = 0; i < law_max; i++) { 157 law_read(i, &bar, &sr); 158 if ((sr & 0x80000000) == 0) 159 break; 160 } 161 162 return (i); 163 } 164 165 #define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | \ 166 (flsl(size + (size - 1)) - 2)) 167 168 int 169 law_enable(int trgt, uint64_t bar, uint32_t size) 170 { 171 uint64_t bar_tmp; 172 uint32_t sr, sr_tmp; 173 int i, law_max; 174 175 if (size == 0) 176 return (0); 177 178 law_max = law_getmax(); 179 sr = _LAW_SR(trgt, size); 180 181 /* Bail if already programmed. */ 182 for (i = 0; i < law_max; i++) { 183 law_read(i, &bar_tmp, &sr_tmp); 184 if (sr == sr_tmp && bar == bar_tmp) 185 return (0); 186 } 187 188 /* Find an unused access window. */ 189 i = law_find_free(); 190 191 if (i == law_max) 192 return (ENOSPC); 193 194 law_write(i, bar, sr); 195 return (0); 196 } 197 198 int 199 law_disable(int trgt, uint64_t bar, uint32_t size) 200 { 201 uint64_t bar_tmp; 202 uint32_t sr, sr_tmp; 203 int i, law_max; 204 205 law_max = law_getmax(); 206 sr = _LAW_SR(trgt, size); 207 208 /* Find and disable requested LAW. */ 209 for (i = 0; i < law_max; i++) { 210 law_read(i, &bar_tmp, &sr_tmp); 211 if (sr == sr_tmp && bar == bar_tmp) { 212 law_write(i, 0, 0); 213 return (0); 214 } 215 } 216 217 return (ENOENT); 218 } 219 220 int 221 law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io) 222 { 223 u_long start; 224 uint32_t ver; 225 int trgt, rv; 226 227 ver = SVR_VER(mfspr(SPR_SVR)); 228 229 start = rman_get_start(res) & 0xf000; 230 231 rv = 0; 232 trgt = -1; 233 switch (start) { 234 case 0x0000: 235 case 0x8000: 236 trgt = 0; 237 break; 238 case 0x1000: 239 case 0x9000: 240 trgt = 1; 241 break; 242 case 0x2000: 243 case 0xa000: 244 if (ver == SVR_MPC8548E || ver == SVR_MPC8548) 245 trgt = 3; 246 else 247 trgt = 2; 248 break; 249 case 0x3000: 250 case 0xb000: 251 if (ver == SVR_MPC8548E || ver == SVR_MPC8548) 252 rv = EINVAL; 253 else 254 trgt = 3; 255 break; 256 default: 257 rv = ENXIO; 258 } 259 if (rv == 0) { 260 *trgt_mem = trgt; 261 *trgt_io = trgt; 262 } 263 return (rv); 264 } 265 266 static void 267 l3cache_inval(void) 268 { 269 270 /* Flash invalidate the CPC and clear all the locks */ 271 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI | 272 OCP85XX_CPC_CSR0_LFC); 273 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI | 274 OCP85XX_CPC_CSR0_LFC)) 275 ; 276 } 277 278 static void 279 l3cache_enable(void) 280 { 281 282 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE | 283 OCP85XX_CPC_CSR0_PE); 284 /* Read back to sync write */ 285 ccsr_read4(OCP85XX_CPC_CSR0); 286 } 287 288 void 289 mpc85xx_enable_l3_cache(void) 290 { 291 uint32_t csr, size, ver; 292 293 /* Enable L3 CoreNet Platform Cache (CPC) */ 294 ver = SVR_VER(mfspr(SPR_SVR)); 295 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 || 296 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) { 297 csr = ccsr_read4(OCP85XX_CPC_CSR0); 298 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { 299 l3cache_inval(); 300 l3cache_enable(); 301 } 302 303 csr = ccsr_read4(OCP85XX_CPC_CSR0); 304 if ((boothowto & RB_VERBOSE) != 0 || 305 (csr & OCP85XX_CPC_CSR0_CE) == 0) { 306 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0)); 307 printf("L3 Corenet Platform Cache: %d KB %sabled\n", 308 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? 309 "dis" : "en"); 310 } 311 } 312 } 313 314 int 315 mpc85xx_is_qoriq(void) 316 { 317 uint16_t pvr = mfpvr() >> 16; 318 319 /* QorIQ register set is only in e500mc and derivative core based SoCs. */ 320 if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500) 321 return (1); 322 323 return (0); 324 } 325 326 static void 327 mpc85xx_dataloss_erratum_spr976(void) 328 { 329 uint32_t svr = SVR_VER(mfspr(SPR_SVR)); 330 331 /* Ignore whether it's the E variant */ 332 svr &= ~0x8; 333 334 if (svr != SVR_P3041 && svr != SVR_P4040 && 335 svr != SVR_P4080 && svr != SVR_P5020) 336 return; 337 338 mb(); 339 isync(); 340 mtspr(976, (mfspr(976) & ~0x1f8) | 0x48); 341 isync(); 342 } 343 344 static vm_offset_t 345 mpc85xx_map_dcsr(void) 346 { 347 phandle_t node; 348 u_long b, s; 349 int err; 350 351 /* 352 * Try to access the dcsr node directly i.e. through /aliases/. 353 */ 354 if ((node = OF_finddevice("dcsr")) != -1) 355 if (fdt_is_compatible_strict(node, "fsl,dcsr")) 356 goto moveon; 357 /* 358 * Find the node the long way. 359 */ 360 if ((node = OF_finddevice("/")) == -1) 361 return (0); 362 363 if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0) 364 return (0); 365 366 moveon: 367 err = fdt_get_range(node, 0, &b, &s); 368 369 if (err != 0) 370 return (0); 371 372 law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000); 373 return pmap_early_io_map(b, 0x400000); 374 } 375 376 377 378 void 379 mpc85xx_fix_errata(vm_offset_t va_ccsr) 380 { 381 uint32_t svr = SVR_VER(mfspr(SPR_SVR)); 382 vm_offset_t va_dcsr; 383 384 /* Ignore whether it's the E variant */ 385 svr &= ~0x8; 386 387 if (svr != SVR_P3041 && svr != SVR_P4040 && 388 svr != SVR_P4080 && svr != SVR_P5020) 389 return; 390 391 if (mfmsr() & PSL_EE) 392 return; 393 394 /* 395 * dcsr region need to be mapped thus patch can refer to. 396 * Align dcsr right after ccsbar. 397 */ 398 va_dcsr = mpc85xx_map_dcsr(); 399 if (va_dcsr == 0) 400 goto err; 401 402 /* 403 * As A004510 errata specify, special purpose register 976 404 * SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual 405 * does not document SPR976 register. 406 */ 407 mpc85xx_dataloss_erratum_spr976(); 408 409 /* 410 * Specific settings in the CCF and core platform cache (CPC) 411 * are required to reconfigure the CoreNet coherency fabric. 412 * The register settings that should be updated are described 413 * in errata and relay on base address, offset and updated value. 414 * Special conditions must be used to update these registers correctly. 415 */ 416 dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800); 417 dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800); 418 dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000); 419 dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000); 420 dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000); 421 422 switch (svr) { 423 case SVR_P5020: 424 dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000); 425 break; 426 case SVR_P4040: 427 case SVR_P4080: 428 dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000); 429 break; 430 case SVR_P3041: 431 dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000); 432 } 433 dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000); 434 dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000); 435 436 err: 437 return; 438 } 439