1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2008, Juniper Networks, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _MACHINE_LBC_H_ 32 #define _MACHINE_LBC_H_ 33 34 /* Maximum number of devices on Local Bus */ 35 #define LBC_DEV_MAX 8 36 37 /* Local access registers */ 38 #define LBC85XX_BR(n) (0x0 + (8 * n)) /* Base register 0-7 */ 39 #define LBC85XX_OR(n) (0x4 + (8 * n)) /* Options register 0-7 */ 40 #define LBC85XX_MAR 0x068 /* UPM address register */ 41 #define LBC85XX_MAMR 0x070 /* UPMA mode register */ 42 #define LBC85XX_MBMR 0x074 /* UPMB mode register */ 43 #define LBC85XX_MCMR 0x078 /* UPMC mode register */ 44 #define LBC85XX_MRTPR 0x084 /* Memory refresh timer prescaler */ 45 #define LBC85XX_MDR 0x088 /* UPM data register */ 46 #define LBC85XX_LSOR 0x090 /* Special operation initiation */ 47 #define LBC85XX_LURT 0x0a0 /* UPM refresh timer */ 48 #define LBC85XX_LSRT 0x0a4 /* SDRAM refresh timer */ 49 #define LBC85XX_LTESR 0x0b0 /* Transfer error status register */ 50 #define LBC85XX_LTEDR 0x0b4 /* Transfer error disable register */ 51 #define LBC85XX_LTEIR 0x0b8 /* Transfer error interrupt register */ 52 #define LBC85XX_LTEATR 0x0bc /* Transfer error attributes register */ 53 #define LBC85XX_LTEAR 0x0c0 /* Transfer error address register */ 54 #define LBC85XX_LTECCR 0x0c4 /* Transfer error ECC register */ 55 #define LBC85XX_LBCR 0x0d0 /* Configuration register */ 56 #define LBC85XX_LCRR 0x0d4 /* Clock ratio register */ 57 #define LBC85XX_FMR 0x0e0 /* Flash mode register */ 58 #define LBC85XX_FIR 0x0e4 /* Flash instruction register */ 59 #define LBC85XX_FCR 0x0e8 /* Flash command register */ 60 #define LBC85XX_FBAR 0x0ec /* Flash block address register */ 61 #define LBC85XX_FPAR 0x0f0 /* Flash page address register */ 62 #define LBC85XX_FBCR 0x0f4 /* Flash byte count register */ 63 #define LBC85XX_FECC0 0x100 /* Flash ECC block 0 register */ 64 #define LBC85XX_FECC1 0x104 /* Flash ECC block 0 register */ 65 #define LBC85XX_FECC2 0x108 /* Flash ECC block 0 register */ 66 #define LBC85XX_FECC3 0x10c /* Flash ECC block 0 register */ 67 68 /* LBC machine select */ 69 #define LBCRES_MSEL_GPCM 0 70 #define LBCRES_MSEL_FCM 1 71 #define LBCRES_MSEL_UPMA 8 72 #define LBCRES_MSEL_UPMB 9 73 #define LBCRES_MSEL_UPMC 10 74 75 /* LBC data error checking modes */ 76 #define LBCRES_DECC_DISABLED 0 77 #define LBCRES_DECC_NORMAL 1 78 #define LBCRES_DECC_RMW 2 79 80 /* LBC atomic operation modes */ 81 #define LBCRES_ATOM_DISABLED 0 82 #define LBCRES_ATOM_RAWA 1 83 #define LBCRES_ATOM_WARA 2 84 85 struct lbc_memrange { 86 vm_paddr_t addr; 87 vm_size_t size; 88 vm_offset_t kva; 89 }; 90 91 struct lbc_bank { 92 vm_paddr_t addr; /* physical addr of the bank */ 93 vm_size_t size; /* bank size */ 94 vm_offset_t kva; /* VA of the bank */ 95 96 /* 97 * XXX the following bank attributes do not have properties specified 98 * in the LBC DTS bindings yet (11.2009), so they are mainly a 99 * placeholder for future extensions. 100 */ 101 int width; /* data bus width */ 102 uint8_t msel; /* machine select */ 103 uint8_t atom; /* atomic op mode */ 104 uint8_t wp; /* write protect */ 105 uint8_t decc; /* data error checking */ 106 }; 107 108 struct lbc_softc { 109 device_t sc_dev; 110 111 struct resource *sc_mres; 112 bus_space_handle_t sc_bsh; 113 bus_space_tag_t sc_bst; 114 int sc_mrid; 115 116 int sc_irid; 117 struct resource *sc_ires; 118 void *sc_icookie; 119 120 struct rman sc_rman; 121 122 int sc_addr_cells; 123 int sc_size_cells; 124 125 struct lbc_memrange sc_range[LBC_DEV_MAX]; 126 struct lbc_bank sc_banks[LBC_DEV_MAX]; 127 128 uint32_t sc_ltesr; 129 }; 130 131 struct lbc_devinfo { 132 struct ofw_bus_devinfo di_ofw; 133 struct resource_list di_res; 134 int di_bank; 135 }; 136 137 uint32_t lbc_read_reg(device_t child, u_int off); 138 void lbc_write_reg(device_t child, u_int off, uint32_t val); 139 140 #endif /* _MACHINE_LBC_H_ */ 141