1 /*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (c) 2017 Justin Hibbits <jhibbits@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/module.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 43 #include <cam/cam.h> 44 #include <cam/cam_ccb.h> 45 #include <cam/cam_sim.h> 46 #include <cam/cam_xpt_sim.h> 47 #include <cam/cam_debug.h> 48 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 54 #include "fsl_sata.h" 55 56 struct fsl_sata_channel; 57 struct fsl_sata_slot; 58 enum fsl_sata_err_type; 59 struct fsl_sata_cmd_tab; 60 61 62 /* local prototypes */ 63 static int fsl_sata_init(device_t dev); 64 static int fsl_sata_deinit(device_t dev); 65 static int fsl_sata_suspend(device_t dev); 66 static int fsl_sata_resume(device_t dev); 67 static void fsl_sata_pm(void *arg); 68 static void fsl_sata_intr(void *arg); 69 static void fsl_sata_intr_main(struct fsl_sata_channel *ch, uint32_t istatus); 70 static void fsl_sata_begin_transaction(struct fsl_sata_channel *ch, union ccb *ccb); 71 static void fsl_sata_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72 static void fsl_sata_execute_transaction(struct fsl_sata_slot *slot); 73 static void fsl_sata_timeout(struct fsl_sata_slot *slot); 74 static void fsl_sata_end_transaction(struct fsl_sata_slot *slot, enum fsl_sata_err_type et); 75 static int fsl_sata_setup_fis(struct fsl_sata_channel *ch, struct fsl_sata_cmd_tab *ctp, union ccb *ccb, int tag); 76 static void fsl_sata_dmainit(device_t dev); 77 static void fsl_sata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78 static void fsl_sata_dmafini(device_t dev); 79 static void fsl_sata_slotsalloc(device_t dev); 80 static void fsl_sata_slotsfree(device_t dev); 81 static void fsl_sata_reset(struct fsl_sata_channel *ch); 82 static void fsl_sata_start(struct fsl_sata_channel *ch); 83 static void fsl_sata_stop(struct fsl_sata_channel *ch); 84 85 static void fsl_sata_issue_recovery(struct fsl_sata_channel *ch); 86 static void fsl_sata_process_read_log(struct fsl_sata_channel *ch, union ccb *ccb); 87 static void fsl_sata_process_request_sense(struct fsl_sata_channel *ch, union ccb *ccb); 88 89 static void fsl_sataaction(struct cam_sim *sim, union ccb *ccb); 90 static void fsl_satapoll(struct cam_sim *sim); 91 92 static MALLOC_DEFINE(M_FSL_SATA, "FSL SATA driver", "FSL SATA driver data buffers"); 93 94 #define recovery_type spriv_field0 95 #define RECOVERY_NONE 0 96 #define RECOVERY_READ_LOG 1 97 #define RECOVERY_REQUEST_SENSE 2 98 #define recovery_slot spriv_field1 99 100 #define FSL_SATA_P_CQR 0x0 101 #define FSL_SATA_P_CAR 0x4 102 #define FSL_SATA_P_CCR 0x10 103 #define FSL_SATA_P_CER 0x18 104 #define FSL_SATA_P_DER 0x20 105 #define FSL_SATA_P_CHBA 0x24 106 #define FSL_SATA_P_HSTS 0x28 107 #define FSL_SATA_P_HSTS_HS_ON 0x80000000 108 #define FSL_SATA_P_HSTS_ME 0x00040000 109 #define FSL_SATA_P_HSTS_DLM 0x00001000 110 #define FSL_SATA_P_HSTS_FOT 0x00000200 111 #define FSL_SATA_P_HSTS_FOR 0x00000100 112 #define FSL_SATA_P_HSTS_FE 0x00000020 113 #define FSL_SATA_P_HSTS_PR 0x00000010 114 #define FSL_SATA_P_HSTS_SNTFU 0x00000004 115 #define FSL_SATA_P_HSTS_DE 0x00000002 116 #define FSL_SATA_P_HCTRL 0x2c 117 #define FSL_SATA_P_HCTRL_HC_ON 0x80000000 118 #define FSL_SATA_P_HCTRL_HC_FORCE_OFF 0x40000000 119 #define FSL_SATA_P_HCTRL_ENT 0x10000000 120 #define FSL_SATA_P_HCTRL_SNOOP 0x00000400 121 #define FSL_SATA_P_HCTRL_PM 0x00000200 122 #define FSL_SATA_P_HCTRL_FATAL 0x00000020 123 #define FSL_SATA_P_HCTRL_PHYRDY 0x00000010 124 #define FSL_SATA_P_HCTRL_SIG 0x00000008 125 #define FSL_SATA_P_HCTRL_SNTFY 0x00000004 126 #define FSL_SATA_P_HCTRL_DE 0x00000002 127 #define FSL_SATA_P_HCTRL_CC 0x00000001 128 #define FSL_SATA_P_HCTRL_INT_MASK 0x0000003f 129 #define FSL_SATA_P_CQPMP 0x30 130 #define FSL_SATA_P_SIG 0x34 131 #define FSL_SATA_P_ICC 0x38 132 #define FSL_SATA_P_ICC_ITC_M 0x1f000000 133 #define FSL_SATA_P_ICC_ITC_S 24 134 #define FSL_SATA_P_ICC_ITTCV_M 0x0007ffff 135 #define FSL_SATA_P_PCC 0x15c 136 #define FSL_SATA_P_PCC_SLUMBER 0x0000000c 137 #define FSL_SATA_P_PCC_PARTIAL 0x0000000a 138 #define FSL_SATA_PCC_LPB_EN 0x0000000e 139 140 #define FSL_SATA_MAX_SLOTS 16 141 /* FSL_SATA register defines */ 142 143 #define FSL_SATA_P_SSTS 0x100 144 #define FSL_SATA_P_SERR 0x104 145 #define FSL_SATA_P_SCTL 0x108 146 #define FSL_SATA_P_SNTF 0x10c 147 148 /* Pessimistic prognosis on number of required S/G entries */ 149 #define FSL_SATA_SG_ENTRIES 63 150 /* Command list. 16 commands. First, 1Kbyte aligned. */ 151 #define FSL_SATA_CL_OFFSET 0 152 #define FSL_SATA_CL_SIZE 16 153 /* Command tables. Up to 32 commands, Each, 4-byte aligned. */ 154 #define FSL_SATA_CT_OFFSET (FSL_SATA_CL_OFFSET + FSL_SATA_CL_SIZE * FSL_SATA_MAX_SLOTS) 155 #define FSL_SATA_CT_SIZE (96 + FSL_SATA_SG_ENTRIES * 16) 156 /* Total main work area. */ 157 #define FSL_SATA_WORK_SIZE (FSL_SATA_CT_OFFSET + FSL_SATA_CT_SIZE * FSL_SATA_MAX_SLOTS) 158 #define FSL_SATA_MAX_XFER (64 * 1024 * 1024) 159 160 /* Some convenience macros for getting the CTP and CLP */ 161 #define FSL_SATA_CTP_BUS(ch, slot) \ 162 ((ch->dma.work_bus + FSL_SATA_CT_OFFSET + (FSL_SATA_CT_SIZE * slot->slot))) 163 #define FSL_SATA_PRD_OFFSET(prd) (96 + (prd) * 16) 164 #define FSL_SATA_CTP(ch, slot) \ 165 ((struct fsl_sata_cmd_tab *)(ch->dma.work + FSL_SATA_CT_OFFSET + \ 166 (FSL_SATA_CT_SIZE * slot->slot))) 167 #define FSL_SATA_CLP(ch, slot) \ 168 ((struct fsl_sata_cmd_list *) (ch->dma.work + FSL_SATA_CL_OFFSET + \ 169 (FSL_SATA_CL_SIZE * slot->slot))) 170 171 struct fsl_sata_dma_prd { 172 uint32_t dba; 173 uint32_t reserved; 174 uint32_t reserved2; 175 uint32_t dwc_flg; /* 0 based */ 176 #define FSL_SATA_PRD_MASK 0x01fffffc /* max 32MB */ 177 #define FSL_SATA_PRD_MAX (FSL_SATA_PRD_MASK + 4) 178 #define FSL_SATA_PRD_SNOOP 0x10000000 179 #define FSL_SATA_PRD_EXT 0x80000000 180 } __packed; 181 182 struct fsl_sata_cmd_tab { 183 uint8_t cfis[32]; 184 uint8_t sfis[32]; 185 uint8_t acmd[16]; 186 uint8_t reserved[16]; 187 struct fsl_sata_dma_prd prd_tab[FSL_SATA_SG_ENTRIES]; 188 #define FSL_SATA_PRD_EXT_INDEX 15 189 #define FSL_SATA_PRD_MAX_DIRECT 16 190 } __packed; 191 192 struct fsl_sata_cmd_list { 193 uint32_t cda; /* word aligned */ 194 uint16_t fis_length; /* length in bytes (aligned to words) */ 195 uint16_t prd_length; /* PRD entries */ 196 uint32_t ttl; 197 uint32_t cmd_flags; 198 #define FSL_SATA_CMD_TAG_MASK 0x001f 199 #define FSL_SATA_CMD_ATAPI 0x0020 200 #define FSL_SATA_CMD_BIST 0x0040 201 #define FSL_SATA_CMD_RESET 0x0080 202 #define FSL_SATA_CMD_QUEUED 0x0100 203 #define FSL_SATA_CMD_SNOOP 0x0200 204 #define FSL_SATA_CMD_VBIST 0x0400 205 #define FSL_SATA_CMD_WRITE 0x0800 206 207 } __packed; 208 209 /* misc defines */ 210 #define ATA_IRQ_RID 0 211 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 212 213 struct ata_dmaslot { 214 bus_dmamap_t data_map; /* data DMA map */ 215 int nsegs; /* Number of segs loaded */ 216 }; 217 218 /* structure holding DMA related information */ 219 struct ata_dma { 220 bus_dma_tag_t work_tag; /* workspace DMA tag */ 221 bus_dmamap_t work_map; /* workspace DMA map */ 222 uint8_t *work; /* workspace */ 223 bus_addr_t work_bus; /* bus address of work */ 224 bus_dma_tag_t data_tag; /* data DMA tag */ 225 }; 226 227 enum fsl_sata_slot_states { 228 FSL_SATA_SLOT_EMPTY, 229 FSL_SATA_SLOT_LOADING, 230 FSL_SATA_SLOT_RUNNING, 231 FSL_SATA_SLOT_EXECUTING 232 }; 233 234 struct fsl_sata_slot { 235 struct fsl_sata_channel *ch; /* Channel */ 236 uint8_t slot; /* Number of this slot */ 237 enum fsl_sata_slot_states state; /* Slot state */ 238 union ccb *ccb; /* CCB occupying slot */ 239 struct ata_dmaslot dma; /* DMA data of this slot */ 240 struct callout timeout; /* Execution timeout */ 241 uint32_t ttl; 242 }; 243 244 struct fsl_sata_device { 245 int revision; 246 int mode; 247 u_int bytecount; 248 u_int atapi; 249 u_int tags; 250 u_int caps; 251 }; 252 253 /* structure describing an ATA channel */ 254 struct fsl_sata_channel { 255 device_t dev; /* Device handle */ 256 int unit; /* Physical channel */ 257 struct resource *r_mem; /* Memory of this channel */ 258 struct resource *r_irq; /* Interrupt of this channel */ 259 void *ih; /* Interrupt handle */ 260 struct ata_dma dma; /* DMA data */ 261 struct cam_sim *sim; 262 struct cam_path *path; 263 uint32_t caps; /* Controller capabilities */ 264 int pm_level; /* power management level */ 265 int devices; /* What is present */ 266 int pm_present; /* PM presence reported */ 267 268 union ccb *hold[FSL_SATA_MAX_SLOTS]; 269 struct fsl_sata_slot slot[FSL_SATA_MAX_SLOTS]; 270 uint32_t oslots; /* Occupied slots */ 271 uint32_t rslots; /* Running slots */ 272 uint32_t aslots; /* Slots with atomic commands */ 273 uint32_t eslots; /* Slots in error */ 274 uint32_t toslots; /* Slots in timeout */ 275 int lastslot; /* Last used slot */ 276 int taggedtarget; /* Last tagged target */ 277 int numrslots; /* Number of running slots */ 278 int numrslotspd[16];/* Number of running slots per dev */ 279 int numtslots; /* Number of tagged slots */ 280 int numtslotspd[16];/* Number of tagged slots per dev */ 281 int numhslots; /* Number of held slots */ 282 int recoverycmd; /* Our READ LOG active */ 283 int fatalerr; /* Fatal error happend */ 284 int resetting; /* Hard-reset in progress. */ 285 int resetpolldiv; /* Hard-reset poll divider. */ 286 union ccb *frozen; /* Frozen command */ 287 struct callout pm_timer; /* Power management events */ 288 struct callout reset_timer; /* Hard-reset timeout */ 289 290 struct fsl_sata_device user[16]; /* User-specified settings */ 291 struct fsl_sata_device curr[16]; /* Current settings */ 292 293 struct mtx_padalign mtx; /* state lock */ 294 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */ 295 int batch; /* doneq is in use */ 296 }; 297 298 enum fsl_sata_err_type { 299 FSL_SATA_ERR_NONE, /* No error */ 300 FSL_SATA_ERR_INVALID, /* Error detected by us before submitting. */ 301 FSL_SATA_ERR_INNOCENT, /* Innocent victim. */ 302 FSL_SATA_ERR_TFE, /* Task File Error. */ 303 FSL_SATA_ERR_SATA, /* SATA error. */ 304 FSL_SATA_ERR_TIMEOUT, /* Command execution timeout. */ 305 FSL_SATA_ERR_NCQ, /* NCQ command error. CCB should be put on hold 306 * until READ LOG executed to reveal error. */ 307 }; 308 309 /* macros to hide busspace uglyness */ 310 #define ATA_INB(res, offset) \ 311 bus_read_1((res), (offset)) 312 #define ATA_INW(res, offset) \ 313 bus_read_2((res), (offset)) 314 #define ATA_INL(res, offset) \ 315 bus_read_4((res), (offset)) 316 #define ATA_INSW(res, offset, addr, count) \ 317 bus_read_multi_2((res), (offset), (addr), (count)) 318 #define ATA_INSW_STRM(res, offset, addr, count) \ 319 bus_read_multi_stream_2((res), (offset), (addr), (count)) 320 #define ATA_INSL(res, offset, addr, count) \ 321 bus_read_multi_4((res), (offset), (addr), (count)) 322 #define ATA_INSL_STRM(res, offset, addr, count) \ 323 bus_read_multi_stream_4((res), (offset), (addr), (count)) 324 #define ATA_OUTB(res, offset, value) \ 325 bus_write_1((res), (offset), (value)) 326 #define ATA_OUTW(res, offset, value) \ 327 bus_write_2((res), (offset), (value)) 328 #define ATA_OUTL(res, offset, value) \ 329 bus_write_4((res), (offset), (value)) 330 #define ATA_OUTSW(res, offset, addr, count) \ 331 bus_write_multi_2((res), (offset), (addr), (count)) 332 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 333 bus_write_multi_stream_2((res), (offset), (addr), (count)) 334 #define ATA_OUTSL(res, offset, addr, count) \ 335 bus_write_multi_4((res), (offset), (addr), (count)) 336 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 337 bus_write_multi_stream_4((res), (offset), (addr), (count)) 338 339 static int 340 fsl_sata_probe(device_t dev) 341 { 342 343 if (!ofw_bus_is_compatible(dev, "fsl,pq-sata-v2") && 344 !ofw_bus_is_compatible(dev, "fsl,pq-sata")) 345 return (ENXIO); 346 347 device_set_desc_copy(dev, "Freescale Integrated SATA Controller"); 348 return (BUS_PROBE_DEFAULT); 349 } 350 351 static int 352 fsl_sata_attach(device_t dev) 353 { 354 struct fsl_sata_channel *ch = device_get_softc(dev); 355 struct cam_devq *devq; 356 int rid, error, i, sata_rev = 0; 357 358 ch->dev = dev; 359 ch->unit = (intptr_t)device_get_ivars(dev); 360 mtx_init(&ch->mtx, "FSL SATA channel lock", NULL, MTX_DEF); 361 ch->pm_level = 0; 362 resource_int_value(device_get_name(dev), 363 device_get_unit(dev), "pm_level", &ch->pm_level); 364 STAILQ_INIT(&ch->doneq); 365 if (ch->pm_level > 3) 366 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 367 resource_int_value(device_get_name(dev), 368 device_get_unit(dev), "sata_rev", &sata_rev); 369 for (i = 0; i < 16; i++) { 370 ch->user[i].revision = sata_rev; 371 ch->user[i].mode = 0; 372 ch->user[i].bytecount = 8192; 373 ch->user[i].tags = FSL_SATA_MAX_SLOTS; 374 ch->user[i].caps = 0; 375 ch->curr[i] = ch->user[i]; 376 if (ch->pm_level) { 377 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 378 CTS_SATA_CAPS_D_PMREQ; 379 } 380 ch->user[i].caps |= CTS_SATA_CAPS_H_AN; 381 } 382 rid = 0; 383 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 384 &rid, RF_ACTIVE))) 385 return (ENXIO); 386 rman_set_bustag(ch->r_mem, &bs_le_tag); 387 fsl_sata_dmainit(dev); 388 fsl_sata_slotsalloc(dev); 389 fsl_sata_init(dev); 390 rid = ATA_IRQ_RID; 391 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 392 &rid, RF_SHAREABLE | RF_ACTIVE))) { 393 device_printf(dev, "Unable to map interrupt\n"); 394 error = ENXIO; 395 goto err0; 396 } 397 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 398 fsl_sata_intr, ch, &ch->ih))) { 399 device_printf(dev, "Unable to setup interrupt\n"); 400 error = ENXIO; 401 goto err1; 402 } 403 mtx_lock(&ch->mtx); 404 /* Create the device queue for our SIM. */ 405 devq = cam_simq_alloc(FSL_SATA_MAX_SLOTS); 406 if (devq == NULL) { 407 device_printf(dev, "Unable to allocate simq\n"); 408 error = ENOMEM; 409 goto err1; 410 } 411 /* Construct SIM entry */ 412 ch->sim = cam_sim_alloc(fsl_sataaction, fsl_satapoll, "fslsata", ch, 413 device_get_unit(dev), (struct mtx *)&ch->mtx, 2, FSL_SATA_MAX_SLOTS, 414 devq); 415 if (ch->sim == NULL) { 416 cam_simq_free(devq); 417 device_printf(dev, "unable to allocate sim\n"); 418 error = ENOMEM; 419 goto err1; 420 } 421 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 422 device_printf(dev, "unable to register xpt bus\n"); 423 error = ENXIO; 424 goto err2; 425 } 426 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 427 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 428 device_printf(dev, "unable to create path\n"); 429 error = ENXIO; 430 goto err3; 431 } 432 if (ch->pm_level > 3) { 433 callout_reset(&ch->pm_timer, 434 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 435 fsl_sata_pm, ch); 436 } 437 mtx_unlock(&ch->mtx); 438 return (0); 439 440 err3: 441 xpt_bus_deregister(cam_sim_path(ch->sim)); 442 err2: 443 cam_sim_free(ch->sim, /*free_devq*/TRUE); 444 err1: 445 mtx_unlock(&ch->mtx); 446 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 447 err0: 448 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 449 mtx_destroy(&ch->mtx); 450 return (error); 451 } 452 453 static int 454 fsl_sata_detach(device_t dev) 455 { 456 struct fsl_sata_channel *ch = device_get_softc(dev); 457 458 mtx_lock(&ch->mtx); 459 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 460 461 xpt_free_path(ch->path); 462 xpt_bus_deregister(cam_sim_path(ch->sim)); 463 cam_sim_free(ch->sim, /*free_devq*/TRUE); 464 mtx_unlock(&ch->mtx); 465 466 if (ch->pm_level > 3) 467 callout_drain(&ch->pm_timer); 468 bus_teardown_intr(dev, ch->r_irq, ch->ih); 469 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 470 471 fsl_sata_deinit(dev); 472 fsl_sata_slotsfree(dev); 473 fsl_sata_dmafini(dev); 474 475 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 476 mtx_destroy(&ch->mtx); 477 return (0); 478 } 479 480 static int 481 fsl_sata_wait_register(struct fsl_sata_channel *ch, bus_size_t off, 482 unsigned int mask, unsigned int val, int t) 483 { 484 int timeout = 0; 485 uint32_t rval; 486 487 while (((rval = ATA_INL(ch->r_mem, off)) & mask) != val) { 488 if (timeout > t) { 489 return (EBUSY); 490 } 491 DELAY(1000); 492 timeout++; 493 } 494 return (0); 495 } 496 497 static int 498 fsl_sata_init(device_t dev) 499 { 500 struct fsl_sata_channel *ch = device_get_softc(dev); 501 uint64_t work; 502 uint32_t r; 503 504 /* Disable port interrupts */ 505 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 506 r &= ~FSL_SATA_P_HCTRL_HC_ON; 507 r |= FSL_SATA_P_HCTRL_HC_FORCE_OFF; 508 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r & ~FSL_SATA_P_HCTRL_INT_MASK); 509 fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 510 FSL_SATA_P_HSTS_HS_ON, 0, 1000); 511 /* Setup work areas */ 512 work = ch->dma.work_bus + FSL_SATA_CL_OFFSET; 513 ATA_OUTL(ch->r_mem, FSL_SATA_P_CHBA, work); 514 r &= ~FSL_SATA_P_HCTRL_ENT; 515 r &= ~FSL_SATA_P_HCTRL_PM; 516 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r); 517 r = ATA_INL(ch->r_mem, FSL_SATA_P_PCC); 518 ATA_OUTL(ch->r_mem, FSL_SATA_P_PCC, r & ~FSL_SATA_PCC_LPB_EN); 519 ATA_OUTL(ch->r_mem, FSL_SATA_P_ICC, (1 << FSL_SATA_P_ICC_ITC_S)); 520 fsl_sata_start(ch); 521 return (0); 522 } 523 524 static int 525 fsl_sata_deinit(device_t dev) 526 { 527 struct fsl_sata_channel *ch = device_get_softc(dev); 528 uint32_t r; 529 530 /* Disable port interrupts. */ 531 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 532 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r & ~FSL_SATA_P_HCTRL_INT_MASK); 533 /* Reset command register. */ 534 fsl_sata_stop(ch); 535 /* Allow everything, including partial and slumber modes. */ 536 ATA_OUTL(ch->r_mem, FSL_SATA_P_SCTL, 0); 537 DELAY(100); 538 /* Disable PHY. */ 539 ATA_OUTL(ch->r_mem, FSL_SATA_P_SCTL, ATA_SC_DET_DISABLE); 540 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 541 /* Turn off the controller. */ 542 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r & ~FSL_SATA_P_HCTRL_HC_ON); 543 return (0); 544 } 545 546 static int 547 fsl_sata_suspend(device_t dev) 548 { 549 struct fsl_sata_channel *ch = device_get_softc(dev); 550 551 mtx_lock(&ch->mtx); 552 xpt_freeze_simq(ch->sim, 1); 553 while (ch->oslots) 554 msleep(ch, &ch->mtx, PRIBIO, "fsl_satasusp", hz/100); 555 fsl_sata_deinit(dev); 556 mtx_unlock(&ch->mtx); 557 return (0); 558 } 559 560 static int 561 fsl_sata_resume(device_t dev) 562 { 563 struct fsl_sata_channel *ch = device_get_softc(dev); 564 565 mtx_lock(&ch->mtx); 566 fsl_sata_init(dev); 567 fsl_sata_reset(ch); 568 xpt_release_simq(ch->sim, TRUE); 569 mtx_unlock(&ch->mtx); 570 return (0); 571 } 572 573 devclass_t fsl_satach_devclass; 574 static device_method_t fsl_satach_methods[] = { 575 DEVMETHOD(device_probe, fsl_sata_probe), 576 DEVMETHOD(device_attach, fsl_sata_attach), 577 DEVMETHOD(device_detach, fsl_sata_detach), 578 DEVMETHOD(device_suspend, fsl_sata_suspend), 579 DEVMETHOD(device_resume, fsl_sata_resume), 580 DEVMETHOD_END 581 }; 582 static driver_t fsl_satach_driver = { 583 "fslsata", 584 fsl_satach_methods, 585 sizeof(struct fsl_sata_channel) 586 }; 587 DRIVER_MODULE(fsl_satach, simplebus, fsl_satach_driver, fsl_satach_devclass, NULL, NULL); 588 589 struct fsl_sata_dc_cb_args { 590 bus_addr_t maddr; 591 int error; 592 }; 593 594 static void 595 fsl_sata_dmainit(device_t dev) 596 { 597 struct fsl_sata_channel *ch = device_get_softc(dev); 598 struct fsl_sata_dc_cb_args dcba; 599 600 /* Command area. */ 601 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 602 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 603 NULL, NULL, FSL_SATA_WORK_SIZE, 1, FSL_SATA_WORK_SIZE, 604 0, NULL, NULL, &ch->dma.work_tag)) 605 goto error; 606 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 607 BUS_DMA_ZERO, &ch->dma.work_map)) 608 goto error; 609 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 610 FSL_SATA_WORK_SIZE, fsl_sata_dmasetupc_cb, &dcba, 0) || dcba.error) { 611 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 612 goto error; 613 } 614 ch->dma.work_bus = dcba.maddr; 615 /* Data area. */ 616 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 617 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 618 NULL, NULL, FSL_SATA_MAX_XFER, 619 FSL_SATA_SG_ENTRIES - 1, FSL_SATA_PRD_MAX, 620 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 621 goto error; 622 } 623 if (bootverbose) 624 device_printf(dev, "work area: %p\n", ch->dma.work); 625 return; 626 627 error: 628 device_printf(dev, "WARNING - DMA initialization failed\n"); 629 fsl_sata_dmafini(dev); 630 } 631 632 static void 633 fsl_sata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 634 { 635 struct fsl_sata_dc_cb_args *dcba = (struct fsl_sata_dc_cb_args *)xsc; 636 637 if (!(dcba->error = error)) 638 dcba->maddr = segs[0].ds_addr; 639 } 640 641 static void 642 fsl_sata_dmafini(device_t dev) 643 { 644 struct fsl_sata_channel *ch = device_get_softc(dev); 645 646 if (ch->dma.data_tag) { 647 bus_dma_tag_destroy(ch->dma.data_tag); 648 ch->dma.data_tag = NULL; 649 } 650 if (ch->dma.work_bus) { 651 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 652 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 653 ch->dma.work_bus = 0; 654 ch->dma.work = NULL; 655 } 656 if (ch->dma.work_tag) { 657 bus_dma_tag_destroy(ch->dma.work_tag); 658 ch->dma.work_tag = NULL; 659 } 660 } 661 662 static void 663 fsl_sata_slotsalloc(device_t dev) 664 { 665 struct fsl_sata_channel *ch = device_get_softc(dev); 666 int i; 667 668 /* Alloc and setup command/dma slots */ 669 bzero(ch->slot, sizeof(ch->slot)); 670 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 671 struct fsl_sata_slot *slot = &ch->slot[i]; 672 673 slot->ch = ch; 674 slot->slot = i; 675 slot->state = FSL_SATA_SLOT_EMPTY; 676 slot->ccb = NULL; 677 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 678 679 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 680 device_printf(ch->dev, "FAILURE - create data_map\n"); 681 } 682 } 683 684 static void 685 fsl_sata_slotsfree(device_t dev) 686 { 687 struct fsl_sata_channel *ch = device_get_softc(dev); 688 int i; 689 690 /* Free all dma slots */ 691 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 692 struct fsl_sata_slot *slot = &ch->slot[i]; 693 694 callout_drain(&slot->timeout); 695 if (slot->dma.data_map) { 696 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 697 slot->dma.data_map = NULL; 698 } 699 } 700 } 701 702 static int 703 fsl_sata_phy_check_events(struct fsl_sata_channel *ch, u_int32_t serr) 704 { 705 706 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 707 ((ch->pm_level != 0) && (serr & ATA_SE_EXCHANGED))) { 708 u_int32_t status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS); 709 union ccb *ccb; 710 711 if (bootverbose) { 712 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 713 device_printf(ch->dev, "CONNECT requested\n"); 714 else 715 device_printf(ch->dev, "DISCONNECT requested\n"); 716 } 717 /* Issue soft reset */ 718 xpt_async(AC_BUS_RESET, ch->path, NULL); 719 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 720 return (0); 721 if (xpt_create_path(&ccb->ccb_h.path, NULL, 722 cam_sim_path(ch->sim), 723 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 724 xpt_free_ccb(ccb); 725 return (0); 726 } 727 xpt_rescan(ccb); 728 return (1); 729 } 730 return (0); 731 } 732 733 static void 734 fsl_sata_notify_events(struct fsl_sata_channel *ch, u_int32_t status) 735 { 736 struct cam_path *dpath; 737 int i; 738 739 ATA_OUTL(ch->r_mem, FSL_SATA_P_SNTF, status); 740 if (bootverbose) 741 device_printf(ch->dev, "SNTF 0x%04x\n", status); 742 for (i = 0; i < 16; i++) { 743 if ((status & (1 << i)) == 0) 744 continue; 745 if (xpt_create_path(&dpath, NULL, 746 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 747 xpt_async(AC_SCSI_AEN, dpath, NULL); 748 xpt_free_path(dpath); 749 } 750 } 751 } 752 753 static void 754 fsl_sata_done(struct fsl_sata_channel *ch, union ccb *ccb) 755 { 756 757 mtx_assert(&ch->mtx, MA_OWNED); 758 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 759 ch->batch == 0) { 760 xpt_done(ccb); 761 return; 762 } 763 764 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 765 } 766 767 static void 768 fsl_sata_intr(void *arg) 769 { 770 struct fsl_sata_channel *ch = (struct fsl_sata_channel *)arg; 771 struct ccb_hdr *ccb_h; 772 uint32_t istatus; 773 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 774 775 /* Read interrupt statuses. */ 776 istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & 0x7ffff; 777 if ((istatus & 0x3f) == 0) 778 return; 779 780 mtx_lock(&ch->mtx); 781 ch->batch = 1; 782 fsl_sata_intr_main(ch, istatus); 783 ch->batch = 0; 784 /* 785 * Prevent the possibility of issues caused by processing the queue 786 * while unlocked below by moving the contents to a local queue. 787 */ 788 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 789 mtx_unlock(&ch->mtx); 790 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 791 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 792 xpt_done_direct((union ccb *)ccb_h); 793 } 794 /* Clear interrupt statuses. */ 795 ATA_OUTL(ch->r_mem, FSL_SATA_P_HSTS, istatus & 0x3f); 796 797 } 798 799 static void 800 fsl_sata_pm(void *arg) 801 { 802 struct fsl_sata_channel *ch = (struct fsl_sata_channel *)arg; 803 uint32_t work; 804 805 if (ch->numrslots != 0) 806 return; 807 work = ATA_INL(ch->r_mem, FSL_SATA_P_PCC) & ~FSL_SATA_PCC_LPB_EN; 808 if (ch->pm_level == 4) 809 work |= FSL_SATA_P_PCC_PARTIAL; 810 else 811 work |= FSL_SATA_P_PCC_SLUMBER; 812 ATA_OUTL(ch->r_mem, FSL_SATA_P_PCC, work); 813 } 814 815 /* XXX: interrupt todo */ 816 static void 817 fsl_sata_intr_main(struct fsl_sata_channel *ch, uint32_t istatus) 818 { 819 uint32_t cer, der, serr = 0, sntf = 0, ok, err; 820 enum fsl_sata_err_type et; 821 int i; 822 823 /* Complete all successful commands. */ 824 ok = ATA_INL(ch->r_mem, FSL_SATA_P_CCR); 825 if (ch->aslots == 0) 826 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 827 if (((ok >> i) & 1) && ch->slot[i].ccb != NULL) 828 fsl_sata_end_transaction(&ch->slot[i], FSL_SATA_ERR_NONE); 829 } 830 /* Read command statuses. */ 831 if (istatus & FSL_SATA_P_HSTS_SNTFU) 832 sntf = ATA_INL(ch->r_mem, FSL_SATA_P_SNTF); 833 /* XXX: Process PHY events */ 834 serr = ATA_INL(ch->r_mem, FSL_SATA_P_SERR); 835 ATA_OUTL(ch->r_mem, FSL_SATA_P_SERR, serr); 836 if (istatus & (FSL_SATA_P_HSTS_PR)) { 837 if (serr) { 838 fsl_sata_phy_check_events(ch, serr); 839 } 840 } 841 /* Process command errors */ 842 err = (istatus & (FSL_SATA_P_HSTS_FE | FSL_SATA_P_HSTS_DE)); 843 cer = ATA_INL(ch->r_mem, FSL_SATA_P_CER); 844 ATA_OUTL(ch->r_mem, FSL_SATA_P_CER, cer); 845 der = ATA_INL(ch->r_mem, FSL_SATA_P_DER); 846 ATA_OUTL(ch->r_mem, FSL_SATA_P_DER, der); 847 /* On error, complete the rest of commands with error statuses. */ 848 if (err) { 849 if (ch->frozen) { 850 union ccb *fccb = ch->frozen; 851 ch->frozen = NULL; 852 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 853 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 854 xpt_freeze_devq(fccb->ccb_h.path, 1); 855 fccb->ccb_h.status |= CAM_DEV_QFRZN; 856 } 857 fsl_sata_done(ch, fccb); 858 } 859 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 860 if (ch->slot[i].ccb == NULL) 861 continue; 862 if ((cer & (1 << i)) != 0) 863 et = FSL_SATA_ERR_TFE; 864 else if ((der & (1 << ch->slot[i].ccb->ccb_h.target_id)) != 0) 865 et = FSL_SATA_ERR_SATA; 866 else 867 et = FSL_SATA_ERR_INVALID; 868 fsl_sata_end_transaction(&ch->slot[i], et); 869 } 870 } 871 /* Process NOTIFY events */ 872 if (sntf) 873 fsl_sata_notify_events(ch, sntf); 874 } 875 876 /* Must be called with channel locked. */ 877 static int 878 fsl_sata_check_collision(struct fsl_sata_channel *ch, union ccb *ccb) 879 { 880 int t = ccb->ccb_h.target_id; 881 882 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 883 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 884 /* Tagged command while we have no supported tag free. */ 885 if (((~ch->oslots) & (0xffffffff >> (32 - 886 ch->curr[t].tags))) == 0) 887 return (1); 888 /* Tagged command while untagged are active. */ 889 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 890 return (1); 891 } else { 892 /* Untagged command while tagged are active. */ 893 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 894 return (1); 895 } 896 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 897 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 898 /* Atomic command while anything active. */ 899 if (ch->numrslots != 0) 900 return (1); 901 } 902 /* We have some atomic command running. */ 903 if (ch->aslots != 0) 904 return (1); 905 return (0); 906 } 907 908 /* Must be called with channel locked. */ 909 static void 910 fsl_sata_begin_transaction(struct fsl_sata_channel *ch, union ccb *ccb) 911 { 912 struct fsl_sata_slot *slot; 913 int tag, tags; 914 915 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 916 ("fsl_sata_begin_transaction func_code=0x%x\n", ccb->ccb_h.func_code)); 917 /* Choose empty slot. */ 918 tags = FSL_SATA_MAX_SLOTS; 919 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 920 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 921 tags = ch->curr[ccb->ccb_h.target_id].tags; 922 if (ch->lastslot + 1 < tags) 923 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 924 else 925 tag = 0; 926 if (tag == 0 || tag + ch->lastslot >= tags) 927 tag = ffs(~ch->oslots) - 1; 928 else 929 tag += ch->lastslot; 930 ch->lastslot = tag; 931 /* Occupy chosen slot. */ 932 slot = &ch->slot[tag]; 933 slot->ccb = ccb; 934 slot->ttl = 0; 935 /* Stop PM timer. */ 936 if (ch->numrslots == 0 && ch->pm_level > 3) 937 callout_stop(&ch->pm_timer); 938 /* Update channel stats. */ 939 ch->oslots |= (1 << tag); 940 ch->numrslots++; 941 ch->numrslotspd[ccb->ccb_h.target_id]++; 942 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 943 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 944 ch->numtslots++; 945 ch->numtslotspd[ccb->ccb_h.target_id]++; 946 ch->taggedtarget = ccb->ccb_h.target_id; 947 } 948 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 949 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 950 ch->aslots |= (1 << tag); 951 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 952 slot->state = FSL_SATA_SLOT_LOADING; 953 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 954 fsl_sata_dmasetprd, slot, 0); 955 } else { 956 slot->dma.nsegs = 0; 957 fsl_sata_execute_transaction(slot); 958 } 959 960 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 961 ("fsl_sata_begin_transaction exit\n")); 962 } 963 964 /* Locked by busdma engine. */ 965 static void 966 fsl_sata_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 967 { 968 struct fsl_sata_slot *slot = arg; 969 struct fsl_sata_channel *ch = slot->ch; 970 struct fsl_sata_cmd_tab *ctp; 971 struct fsl_sata_dma_prd *prd; 972 int i, j, len, extlen; 973 974 if (error) { 975 device_printf(ch->dev, "DMA load error %d\n", error); 976 fsl_sata_end_transaction(slot, FSL_SATA_ERR_INVALID); 977 return; 978 } 979 KASSERT(nsegs <= FSL_SATA_SG_ENTRIES - 1, 980 ("too many DMA segment entries\n")); 981 /* Get a piece of the workspace for this request */ 982 ctp = FSL_SATA_CTP(ch, slot); 983 /* Fill S/G table */ 984 prd = &ctp->prd_tab[0]; 985 for (i = 0, j = 0; i < nsegs; i++, j++) { 986 if (j == FSL_SATA_PRD_EXT_INDEX && 987 FSL_SATA_PRD_MAX_DIRECT < nsegs) { 988 prd[j].dba = htole32(FSL_SATA_CTP_BUS(ch, slot) + 989 FSL_SATA_PRD_OFFSET(j+1)); 990 j++; 991 extlen = 0; 992 } 993 len = segs[i].ds_len; 994 len = roundup2(len, sizeof(uint32_t)); 995 prd[j].dba = htole32((uint32_t)segs[i].ds_addr); 996 prd[j].dwc_flg = htole32(FSL_SATA_PRD_SNOOP | len); 997 slot->ttl += len; 998 if (j > FSL_SATA_PRD_MAX_DIRECT) 999 extlen += len; 1000 } 1001 slot->dma.nsegs = j; 1002 if (j > FSL_SATA_PRD_MAX_DIRECT) 1003 prd[FSL_SATA_PRD_EXT_INDEX].dwc_flg = 1004 htole32(FSL_SATA_PRD_SNOOP | FSL_SATA_PRD_EXT | extlen); 1005 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1006 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1007 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1008 fsl_sata_execute_transaction(slot); 1009 } 1010 1011 /* Must be called with channel locked. */ 1012 static void 1013 fsl_sata_execute_transaction(struct fsl_sata_slot *slot) 1014 { 1015 struct fsl_sata_channel *ch = slot->ch; 1016 struct fsl_sata_cmd_tab *ctp; 1017 struct fsl_sata_cmd_list *clp; 1018 union ccb *ccb = slot->ccb; 1019 int port = ccb->ccb_h.target_id & 0x0f; 1020 int fis_size, i, softreset; 1021 uint32_t tmp; 1022 uint32_t cmd_flags = FSL_SATA_CMD_WRITE | FSL_SATA_CMD_SNOOP; 1023 1024 softreset = 0; 1025 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 1026 ("fsl_sata_execute_transaction func_code=0x%x\n", ccb->ccb_h.func_code)); 1027 /* Get a piece of the workspace for this request */ 1028 ctp = FSL_SATA_CTP(ch, slot); 1029 /* Setup the FIS for this request */ 1030 if (!(fis_size = fsl_sata_setup_fis(ch, ctp, ccb, slot->slot))) { 1031 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1032 fsl_sata_end_transaction(slot, FSL_SATA_ERR_INVALID); 1033 return; 1034 } 1035 /* Setup the command list entry */ 1036 clp = FSL_SATA_CLP(ch, slot); 1037 clp->fis_length = htole16(fis_size); 1038 clp->prd_length = htole16(slot->dma.nsegs); 1039 /* Special handling for Soft Reset command. */ 1040 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1041 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1042 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1043 softreset = 1; 1044 cmd_flags |= FSL_SATA_CMD_RESET; 1045 } else { 1046 /* Prepare FIS receive area for check. */ 1047 for (i = 0; i < 32; i++) 1048 ctp->sfis[i] = 0xff; 1049 softreset = 2; 1050 } 1051 } 1052 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) 1053 cmd_flags |= FSL_SATA_CMD_QUEUED; 1054 clp->cmd_flags = htole32(cmd_flags | 1055 (ccb->ccb_h.func_code == XPT_SCSI_IO ? FSL_SATA_CMD_ATAPI : 0) | 1056 slot->slot); 1057 clp->ttl = htole32(slot->ttl); 1058 clp->cda = htole32(FSL_SATA_CTP_BUS(ch, slot)); 1059 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1060 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1061 /* Issue command to the controller. */ 1062 slot->state = FSL_SATA_SLOT_RUNNING; 1063 ch->rslots |= (1 << slot->slot); 1064 ATA_OUTL(ch->r_mem, FSL_SATA_P_CQPMP, port); 1065 ATA_OUTL(ch->r_mem, FSL_SATA_P_CQR, (1 << slot->slot)); 1066 /* Device reset commands don't interrupt. Poll them. */ 1067 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1068 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1069 int count, timeout = ccb->ccb_h.timeout * 100; 1070 enum fsl_sata_err_type et = FSL_SATA_ERR_NONE; 1071 1072 for (count = 0; count < timeout; count++) { 1073 DELAY(10); 1074 tmp = 0; 1075 if (softreset == 2) { 1076 tmp = ATA_INL(ch->r_mem, FSL_SATA_P_SIG); 1077 if (tmp != 0 && tmp != 0xffffffff) 1078 break; 1079 continue; 1080 } 1081 if ((ATA_INL(ch->r_mem, FSL_SATA_P_CCR) & (1 << slot->slot)) != 0) 1082 break; 1083 } 1084 1085 if (timeout && (count >= timeout)) { 1086 device_printf(ch->dev, "Poll timeout on slot %d port %d (round %d)\n", 1087 slot->slot, port, softreset); 1088 device_printf(ch->dev, "hsts %08x cqr %08x ccr %08x ss %08x " 1089 "rs %08x cer %08x der %08x serr %08x car %08x sig %08x\n", 1090 ATA_INL(ch->r_mem, FSL_SATA_P_HSTS), 1091 ATA_INL(ch->r_mem, FSL_SATA_P_CQR), 1092 ATA_INL(ch->r_mem, FSL_SATA_P_CCR), 1093 ATA_INL(ch->r_mem, FSL_SATA_P_SSTS), ch->rslots, 1094 ATA_INL(ch->r_mem, FSL_SATA_P_CER), 1095 ATA_INL(ch->r_mem, FSL_SATA_P_DER), 1096 ATA_INL(ch->r_mem, FSL_SATA_P_SERR), 1097 ATA_INL(ch->r_mem, FSL_SATA_P_CAR), 1098 ATA_INL(ch->r_mem, FSL_SATA_P_SIG)); 1099 et = FSL_SATA_ERR_TIMEOUT; 1100 } 1101 1102 fsl_sata_end_transaction(slot, et); 1103 return; 1104 } 1105 /* Start command execution timeout */ 1106 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1107 0, (timeout_t*)fsl_sata_timeout, slot, 0); 1108 return; 1109 } 1110 1111 /* Must be called with channel locked. */ 1112 static void 1113 fsl_sata_process_timeout(struct fsl_sata_channel *ch) 1114 { 1115 int i; 1116 1117 mtx_assert(&ch->mtx, MA_OWNED); 1118 /* Handle the rest of commands. */ 1119 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1120 /* Do we have a running request on slot? */ 1121 if (ch->slot[i].state < FSL_SATA_SLOT_RUNNING) 1122 continue; 1123 fsl_sata_end_transaction(&ch->slot[i], FSL_SATA_ERR_TIMEOUT); 1124 } 1125 } 1126 1127 /* Must be called with channel locked. */ 1128 static void 1129 fsl_sata_rearm_timeout(struct fsl_sata_channel *ch) 1130 { 1131 int i; 1132 1133 mtx_assert(&ch->mtx, MA_OWNED); 1134 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1135 struct fsl_sata_slot *slot = &ch->slot[i]; 1136 1137 /* Do we have a running request on slot? */ 1138 if (slot->state < FSL_SATA_SLOT_RUNNING) 1139 continue; 1140 if ((ch->toslots & (1 << i)) == 0) 1141 continue; 1142 callout_reset_sbt(&slot->timeout, 1143 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1144 (timeout_t*)fsl_sata_timeout, slot, 0); 1145 } 1146 } 1147 1148 /* Locked by callout mechanism. */ 1149 static void 1150 fsl_sata_timeout(struct fsl_sata_slot *slot) 1151 { 1152 struct fsl_sata_channel *ch = slot->ch; 1153 device_t dev = ch->dev; 1154 uint32_t sstatus; 1155 1156 /* Check for stale timeout. */ 1157 if (slot->state < FSL_SATA_SLOT_RUNNING) 1158 return; 1159 1160 /* Check if slot was not being executed last time we checked. */ 1161 if (slot->state < FSL_SATA_SLOT_EXECUTING) { 1162 /* Check if slot started executing. */ 1163 sstatus = ATA_INL(ch->r_mem, FSL_SATA_P_CAR); 1164 if ((sstatus & (1 << slot->slot)) != 0) 1165 slot->state = FSL_SATA_SLOT_EXECUTING; 1166 1167 callout_reset_sbt(&slot->timeout, 1168 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1169 (timeout_t*)fsl_sata_timeout, slot, 0); 1170 return; 1171 } 1172 1173 device_printf(dev, "Timeout on slot %d port %d\n", 1174 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1175 1176 /* Handle frozen command. */ 1177 if (ch->frozen) { 1178 union ccb *fccb = ch->frozen; 1179 ch->frozen = NULL; 1180 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1181 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1182 xpt_freeze_devq(fccb->ccb_h.path, 1); 1183 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1184 } 1185 fsl_sata_done(ch, fccb); 1186 } 1187 if (ch->toslots == 0) 1188 xpt_freeze_simq(ch->sim, 1); 1189 ch->toslots |= (1 << slot->slot); 1190 if ((ch->rslots & ~ch->toslots) == 0) 1191 fsl_sata_process_timeout(ch); 1192 else 1193 device_printf(dev, " ... waiting for slots %08x\n", 1194 ch->rslots & ~ch->toslots); 1195 } 1196 1197 /* Must be called with channel locked. */ 1198 static void 1199 fsl_sata_end_transaction(struct fsl_sata_slot *slot, enum fsl_sata_err_type et) 1200 { 1201 struct fsl_sata_channel *ch = slot->ch; 1202 union ccb *ccb = slot->ccb; 1203 struct fsl_sata_cmd_list *clp; 1204 int lastto; 1205 uint32_t sig; 1206 1207 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1208 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1209 clp = FSL_SATA_CLP(ch, slot); 1210 /* Read result registers to the result struct */ 1211 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1212 struct ata_res *res = &ccb->ataio.res; 1213 1214 if ((et == FSL_SATA_ERR_TFE) || 1215 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1216 struct fsl_sata_cmd_tab *ctp = FSL_SATA_CTP(ch, slot); 1217 uint8_t *fis = ctp->sfis; 1218 1219 res->status = fis[2]; 1220 res->error = fis[3]; 1221 res->lba_low = fis[4]; 1222 res->lba_mid = fis[5]; 1223 res->lba_high = fis[6]; 1224 res->device = fis[7]; 1225 res->lba_low_exp = fis[8]; 1226 res->lba_mid_exp = fis[9]; 1227 res->lba_high_exp = fis[10]; 1228 res->sector_count = fis[12]; 1229 res->sector_count_exp = fis[13]; 1230 1231 if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1232 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1233 sig = ATA_INL(ch->r_mem, FSL_SATA_P_SIG); 1234 res->lba_high = sig >> 24; 1235 res->lba_mid = sig >> 16; 1236 res->lba_low = sig >> 8; 1237 res->sector_count = sig; 1238 } 1239 } else 1240 bzero(res, sizeof(*res)); 1241 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1242 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1243 ccb->ataio.resid = 1244 ccb->ataio.dxfer_len - le32toh(clp->ttl); 1245 } 1246 } else { 1247 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1248 ccb->csio.resid = 1249 ccb->csio.dxfer_len - le32toh(clp->ttl); 1250 } 1251 } 1252 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1253 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1254 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1255 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1256 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1257 } 1258 if (et != FSL_SATA_ERR_NONE) 1259 ch->eslots |= (1 << slot->slot); 1260 /* In case of error, freeze device for proper recovery. */ 1261 if ((et != FSL_SATA_ERR_NONE) && (!ch->recoverycmd) && 1262 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1263 xpt_freeze_devq(ccb->ccb_h.path, 1); 1264 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1265 } 1266 /* Set proper result status. */ 1267 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1268 switch (et) { 1269 case FSL_SATA_ERR_NONE: 1270 ccb->ccb_h.status |= CAM_REQ_CMP; 1271 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1272 ccb->csio.scsi_status = SCSI_STATUS_OK; 1273 break; 1274 case FSL_SATA_ERR_INVALID: 1275 ch->fatalerr = 1; 1276 ccb->ccb_h.status |= CAM_REQ_INVALID; 1277 break; 1278 case FSL_SATA_ERR_INNOCENT: 1279 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1280 break; 1281 case FSL_SATA_ERR_TFE: 1282 case FSL_SATA_ERR_NCQ: 1283 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1284 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1285 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1286 } else { 1287 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1288 } 1289 break; 1290 case FSL_SATA_ERR_SATA: 1291 ch->fatalerr = 1; 1292 if (!ch->recoverycmd) { 1293 xpt_freeze_simq(ch->sim, 1); 1294 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1295 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1296 } 1297 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1298 break; 1299 case FSL_SATA_ERR_TIMEOUT: 1300 if (!ch->recoverycmd) { 1301 xpt_freeze_simq(ch->sim, 1); 1302 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1303 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1304 } 1305 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1306 break; 1307 default: 1308 ch->fatalerr = 1; 1309 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1310 } 1311 /* Free slot. */ 1312 ch->oslots &= ~(1 << slot->slot); 1313 ch->rslots &= ~(1 << slot->slot); 1314 ch->aslots &= ~(1 << slot->slot); 1315 slot->state = FSL_SATA_SLOT_EMPTY; 1316 slot->ccb = NULL; 1317 /* Update channel stats. */ 1318 ch->numrslots--; 1319 ch->numrslotspd[ccb->ccb_h.target_id]--; 1320 ATA_OUTL(ch->r_mem, FSL_SATA_P_CCR, 1 << slot->slot); 1321 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1322 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1323 ch->numtslots--; 1324 ch->numtslotspd[ccb->ccb_h.target_id]--; 1325 } 1326 /* Cancel timeout state if request completed normally. */ 1327 if (et != FSL_SATA_ERR_TIMEOUT) { 1328 lastto = (ch->toslots == (1 << slot->slot)); 1329 ch->toslots &= ~(1 << slot->slot); 1330 if (lastto) 1331 xpt_release_simq(ch->sim, TRUE); 1332 } 1333 /* If it was first request of reset sequence and there is no error, 1334 * proceed to second request. */ 1335 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1336 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1337 (ccb->ataio.cmd.control & ATA_A_RESET) && 1338 et == FSL_SATA_ERR_NONE) { 1339 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1340 fsl_sata_begin_transaction(ch, ccb); 1341 return; 1342 } 1343 /* If it was our READ LOG command - process it. */ 1344 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1345 fsl_sata_process_read_log(ch, ccb); 1346 /* If it was our REQUEST SENSE command - process it. */ 1347 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1348 fsl_sata_process_request_sense(ch, ccb); 1349 /* If it was NCQ or ATAPI command error, put result on hold. */ 1350 } else if (et == FSL_SATA_ERR_NCQ || 1351 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1352 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1353 ch->hold[slot->slot] = ccb; 1354 ch->numhslots++; 1355 } else 1356 fsl_sata_done(ch, ccb); 1357 /* If we have no other active commands, ... */ 1358 if (ch->rslots == 0) { 1359 /* if there was fatal error - reset port. */ 1360 if (ch->toslots != 0 || ch->fatalerr) { 1361 fsl_sata_reset(ch); 1362 } else { 1363 /* if we have slots in error, we can reinit port. */ 1364 if (ch->eslots != 0) { 1365 fsl_sata_stop(ch); 1366 fsl_sata_start(ch); 1367 } 1368 /* if there commands on hold, we can do READ LOG. */ 1369 if (!ch->recoverycmd && ch->numhslots) 1370 fsl_sata_issue_recovery(ch); 1371 } 1372 /* If all the rest of commands are in timeout - give them chance. */ 1373 } else if ((ch->rslots & ~ch->toslots) == 0 && 1374 et != FSL_SATA_ERR_TIMEOUT) 1375 fsl_sata_rearm_timeout(ch); 1376 /* Unfreeze frozen command. */ 1377 if (ch->frozen && !fsl_sata_check_collision(ch, ch->frozen)) { 1378 union ccb *fccb = ch->frozen; 1379 ch->frozen = NULL; 1380 fsl_sata_begin_transaction(ch, fccb); 1381 xpt_release_simq(ch->sim, TRUE); 1382 } 1383 /* Start PM timer. */ 1384 if (ch->numrslots == 0 && ch->pm_level > 3 && 1385 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1386 callout_schedule(&ch->pm_timer, 1387 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1388 } 1389 } 1390 1391 static void 1392 fsl_sata_issue_recovery(struct fsl_sata_channel *ch) 1393 { 1394 union ccb *ccb; 1395 struct ccb_ataio *ataio; 1396 struct ccb_scsiio *csio; 1397 int i; 1398 1399 /* Find some held command. */ 1400 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1401 if (ch->hold[i]) 1402 break; 1403 } 1404 ccb = xpt_alloc_ccb_nowait(); 1405 if (ccb == NULL) { 1406 device_printf(ch->dev, "Unable to allocate recovery command\n"); 1407 completeall: 1408 /* We can't do anything -- complete held commands. */ 1409 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1410 if (ch->hold[i] == NULL) 1411 continue; 1412 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1413 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1414 fsl_sata_done(ch, ch->hold[i]); 1415 ch->hold[i] = NULL; 1416 ch->numhslots--; 1417 } 1418 fsl_sata_reset(ch); 1419 return; 1420 } 1421 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1422 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1423 /* READ LOG */ 1424 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1425 ccb->ccb_h.func_code = XPT_ATA_IO; 1426 ccb->ccb_h.flags = CAM_DIR_IN; 1427 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1428 ataio = &ccb->ataio; 1429 ataio->data_ptr = malloc(512, M_FSL_SATA, M_NOWAIT); 1430 if (ataio->data_ptr == NULL) { 1431 xpt_free_ccb(ccb); 1432 device_printf(ch->dev, 1433 "Unable to allocate memory for READ LOG command\n"); 1434 goto completeall; 1435 } 1436 ataio->dxfer_len = 512; 1437 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1438 ataio->cmd.flags = CAM_ATAIO_48BIT; 1439 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1440 ataio->cmd.sector_count = 1; 1441 ataio->cmd.sector_count_exp = 0; 1442 ataio->cmd.lba_low = 0x10; 1443 ataio->cmd.lba_mid = 0; 1444 ataio->cmd.lba_mid_exp = 0; 1445 } else { 1446 /* REQUEST SENSE */ 1447 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 1448 ccb->ccb_h.recovery_slot = i; 1449 ccb->ccb_h.func_code = XPT_SCSI_IO; 1450 ccb->ccb_h.flags = CAM_DIR_IN; 1451 ccb->ccb_h.status = 0; 1452 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1453 csio = &ccb->csio; 1454 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 1455 csio->dxfer_len = ch->hold[i]->csio.sense_len; 1456 csio->cdb_len = 6; 1457 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 1458 csio->cdb_io.cdb_bytes[0] = 0x03; 1459 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 1460 } 1461 /* Freeze SIM while doing recovery. */ 1462 ch->recoverycmd = 1; 1463 xpt_freeze_simq(ch->sim, 1); 1464 fsl_sata_begin_transaction(ch, ccb); 1465 } 1466 1467 static void 1468 fsl_sata_process_read_log(struct fsl_sata_channel *ch, union ccb *ccb) 1469 { 1470 uint8_t *data; 1471 struct ata_res *res; 1472 int i; 1473 1474 ch->recoverycmd = 0; 1475 1476 data = ccb->ataio.data_ptr; 1477 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1478 (data[0] & 0x80) == 0) { 1479 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1480 if (!ch->hold[i]) 1481 continue; 1482 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 1483 continue; 1484 if ((data[0] & 0x1F) == i) { 1485 res = &ch->hold[i]->ataio.res; 1486 res->status = data[2]; 1487 res->error = data[3]; 1488 res->lba_low = data[4]; 1489 res->lba_mid = data[5]; 1490 res->lba_high = data[6]; 1491 res->device = data[7]; 1492 res->lba_low_exp = data[8]; 1493 res->lba_mid_exp = data[9]; 1494 res->lba_high_exp = data[10]; 1495 res->sector_count = data[12]; 1496 res->sector_count_exp = data[13]; 1497 } else { 1498 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1499 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1500 } 1501 fsl_sata_done(ch, ch->hold[i]); 1502 ch->hold[i] = NULL; 1503 ch->numhslots--; 1504 } 1505 } else { 1506 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1507 device_printf(ch->dev, "Error while READ LOG EXT\n"); 1508 else if ((data[0] & 0x80) == 0) { 1509 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 1510 } 1511 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1512 if (!ch->hold[i]) 1513 continue; 1514 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 1515 continue; 1516 fsl_sata_done(ch, ch->hold[i]); 1517 ch->hold[i] = NULL; 1518 ch->numhslots--; 1519 } 1520 } 1521 free(ccb->ataio.data_ptr, M_FSL_SATA); 1522 xpt_free_ccb(ccb); 1523 xpt_release_simq(ch->sim, TRUE); 1524 } 1525 1526 static void 1527 fsl_sata_process_request_sense(struct fsl_sata_channel *ch, union ccb *ccb) 1528 { 1529 int i; 1530 1531 ch->recoverycmd = 0; 1532 1533 i = ccb->ccb_h.recovery_slot; 1534 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 1535 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 1536 } else { 1537 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1538 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 1539 } 1540 fsl_sata_done(ch, ch->hold[i]); 1541 ch->hold[i] = NULL; 1542 ch->numhslots--; 1543 xpt_free_ccb(ccb); 1544 xpt_release_simq(ch->sim, TRUE); 1545 } 1546 1547 static void 1548 fsl_sata_start(struct fsl_sata_channel *ch) 1549 { 1550 u_int32_t cmd; 1551 1552 /* Clear SATA error register */ 1553 ATA_OUTL(ch->r_mem, FSL_SATA_P_SERR, 0xFFFFFFFF); 1554 /* Clear any interrupts pending on this channel */ 1555 ATA_OUTL(ch->r_mem, FSL_SATA_P_HSTS, 0x3F); 1556 ATA_OUTL(ch->r_mem, FSL_SATA_P_CER, 0xFFFF); 1557 ATA_OUTL(ch->r_mem, FSL_SATA_P_DER, 0xFFFF); 1558 /* Start operations on this channel */ 1559 cmd = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 1560 cmd |= FSL_SATA_P_HCTRL_HC_ON | FSL_SATA_P_HCTRL_SNOOP; 1561 cmd &= ~FSL_SATA_P_HCTRL_HC_FORCE_OFF; 1562 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, cmd | 1563 (ch->pm_present ? FSL_SATA_P_HCTRL_PM : 0)); 1564 fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 1565 FSL_SATA_P_HSTS_PR, FSL_SATA_P_HSTS_PR, 500); 1566 ATA_OUTL(ch->r_mem, FSL_SATA_P_HSTS, 1567 ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & FSL_SATA_P_HSTS_PR); 1568 } 1569 1570 static void 1571 fsl_sata_stop(struct fsl_sata_channel *ch) 1572 { 1573 uint32_t cmd; 1574 int i; 1575 1576 /* Kill all activity on this channel */ 1577 cmd = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 1578 cmd &= ~FSL_SATA_P_HCTRL_HC_ON; 1579 1580 for (i = 0; i < 2; i++) { 1581 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, cmd); 1582 if (fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 1583 FSL_SATA_P_HSTS_HS_ON, 0, 500)) { 1584 if (i != 0) 1585 device_printf(ch->dev, 1586 "stopping FSL SATA engine failed\n"); 1587 cmd |= FSL_SATA_P_HCTRL_HC_FORCE_OFF; 1588 } else 1589 break; 1590 } 1591 ch->eslots = 0; 1592 } 1593 1594 static void 1595 fsl_sata_reset(struct fsl_sata_channel *ch) 1596 { 1597 uint32_t ctrl; 1598 int i; 1599 1600 xpt_freeze_simq(ch->sim, 1); 1601 if (bootverbose) 1602 device_printf(ch->dev, "FSL SATA reset...\n"); 1603 1604 /* Requeue freezed command. */ 1605 if (ch->frozen) { 1606 union ccb *fccb = ch->frozen; 1607 ch->frozen = NULL; 1608 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1609 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1610 xpt_freeze_devq(fccb->ccb_h.path, 1); 1611 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1612 } 1613 fsl_sata_done(ch, fccb); 1614 } 1615 /* Kill the engine and requeue all running commands. */ 1616 fsl_sata_stop(ch); 1617 DELAY(1000); /* sleep for 1ms */ 1618 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1619 /* Do we have a running request on slot? */ 1620 if (ch->slot[i].state < FSL_SATA_SLOT_RUNNING) 1621 continue; 1622 /* XXX; Commands in loading state. */ 1623 fsl_sata_end_transaction(&ch->slot[i], FSL_SATA_ERR_INNOCENT); 1624 } 1625 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1626 if (!ch->hold[i]) 1627 continue; 1628 fsl_sata_done(ch, ch->hold[i]); 1629 ch->hold[i] = NULL; 1630 ch->numhslots--; 1631 } 1632 if (ch->toslots != 0) 1633 xpt_release_simq(ch->sim, TRUE); 1634 ch->eslots = 0; 1635 ch->toslots = 0; 1636 ch->fatalerr = 0; 1637 /* Tell the XPT about the event */ 1638 xpt_async(AC_BUS_RESET, ch->path, NULL); 1639 /* Disable port interrupts */ 1640 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, 1641 ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f); 1642 /* Reset and reconnect PHY, */ 1643 fsl_sata_start(ch); 1644 if (fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 0x08, 0x08, 500)) { 1645 if (bootverbose) 1646 device_printf(ch->dev, 1647 "FSL SATA reset: device not found\n"); 1648 ch->devices = 0; 1649 /* Enable wanted port interrupts */ 1650 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, 1651 ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) | FSL_SATA_P_HCTRL_PHYRDY); 1652 xpt_release_simq(ch->sim, TRUE); 1653 return; 1654 } 1655 if (bootverbose) 1656 device_printf(ch->dev, "FSL SATA reset: device found\n"); 1657 ch->devices = 1; 1658 /* Enable wanted port interrupts */ 1659 ctrl = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f; 1660 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, 1661 ctrl | FSL_SATA_P_HCTRL_FATAL | FSL_SATA_P_HCTRL_PHYRDY | 1662 FSL_SATA_P_HCTRL_SIG | FSL_SATA_P_HCTRL_SNTFY | 1663 FSL_SATA_P_HCTRL_DE | FSL_SATA_P_HCTRL_CC); 1664 xpt_release_simq(ch->sim, TRUE); 1665 } 1666 1667 static int 1668 fsl_sata_setup_fis(struct fsl_sata_channel *ch, struct fsl_sata_cmd_tab *ctp, union ccb *ccb, int tag) 1669 { 1670 uint8_t *fis = &ctp->cfis[0]; 1671 1672 bzero(fis, 32); 1673 fis[0] = 0x27; /* host to device */ 1674 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1675 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1676 fis[1] |= 0x80; 1677 fis[2] = ATA_PACKET_CMD; 1678 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1679 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 1680 fis[3] = ATA_F_DMA; 1681 else { 1682 fis[5] = ccb->csio.dxfer_len; 1683 fis[6] = ccb->csio.dxfer_len >> 8; 1684 } 1685 fis[7] = ATA_D_LBA; 1686 fis[15] = ATA_A_4BIT; 1687 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1688 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1689 ctp->acmd, ccb->csio.cdb_len); 1690 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 1691 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1692 fis[1] |= 0x80; 1693 fis[2] = ccb->ataio.cmd.command; 1694 fis[3] = ccb->ataio.cmd.features; 1695 fis[4] = ccb->ataio.cmd.lba_low; 1696 fis[5] = ccb->ataio.cmd.lba_mid; 1697 fis[6] = ccb->ataio.cmd.lba_high; 1698 fis[7] = ccb->ataio.cmd.device; 1699 fis[8] = ccb->ataio.cmd.lba_low_exp; 1700 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1701 fis[10] = ccb->ataio.cmd.lba_high_exp; 1702 fis[11] = ccb->ataio.cmd.features_exp; 1703 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1704 fis[12] = tag << 3; 1705 fis[13] = 0; 1706 } else { 1707 fis[12] = ccb->ataio.cmd.sector_count; 1708 fis[13] = ccb->ataio.cmd.sector_count_exp; 1709 } 1710 fis[15] = ATA_A_4BIT; 1711 } else { 1712 fis[15] = ccb->ataio.cmd.control; 1713 } 1714 return (20); 1715 } 1716 1717 static int 1718 fsl_sata_check_ids(struct fsl_sata_channel *ch, union ccb *ccb) 1719 { 1720 1721 if (ccb->ccb_h.target_id > 15) { 1722 ccb->ccb_h.status = CAM_TID_INVALID; 1723 fsl_sata_done(ch, ccb); 1724 return (-1); 1725 } 1726 if (ccb->ccb_h.target_lun != 0) { 1727 ccb->ccb_h.status = CAM_LUN_INVALID; 1728 fsl_sata_done(ch, ccb); 1729 return (-1); 1730 } 1731 return (0); 1732 } 1733 1734 static void 1735 fsl_sataaction(struct cam_sim *sim, union ccb *ccb) 1736 { 1737 struct fsl_sata_channel *ch; 1738 1739 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 1740 ("fsl_sataaction func_code=0x%x\n", ccb->ccb_h.func_code)); 1741 1742 ch = (struct fsl_sata_channel *)cam_sim_softc(sim); 1743 switch (ccb->ccb_h.func_code) { 1744 /* Common cases first */ 1745 case XPT_ATA_IO: /* Execute the requested I/O operation */ 1746 case XPT_SCSI_IO: 1747 if (fsl_sata_check_ids(ch, ccb)) 1748 return; 1749 if (ch->devices == 0 || 1750 (ch->pm_present == 0 && 1751 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 1752 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1753 break; 1754 } 1755 ccb->ccb_h.recovery_type = RECOVERY_NONE; 1756 /* Check for command collision. */ 1757 if (fsl_sata_check_collision(ch, ccb)) { 1758 /* Freeze command. */ 1759 ch->frozen = ccb; 1760 /* We have only one frozen slot, so freeze simq also. */ 1761 xpt_freeze_simq(ch->sim, 1); 1762 return; 1763 } 1764 fsl_sata_begin_transaction(ch, ccb); 1765 return; 1766 case XPT_ABORT: /* Abort the specified CCB */ 1767 /* XXX Implement */ 1768 ccb->ccb_h.status = CAM_REQ_INVALID; 1769 break; 1770 case XPT_SET_TRAN_SETTINGS: 1771 { 1772 struct ccb_trans_settings *cts = &ccb->cts; 1773 struct fsl_sata_device *d; 1774 1775 if (fsl_sata_check_ids(ch, ccb)) 1776 return; 1777 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1778 d = &ch->curr[ccb->ccb_h.target_id]; 1779 else 1780 d = &ch->user[ccb->ccb_h.target_id]; 1781 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 1782 d->revision = cts->xport_specific.sata.revision; 1783 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 1784 d->mode = cts->xport_specific.sata.mode; 1785 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 1786 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 1787 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 1788 d->tags = min(FSL_SATA_MAX_SLOTS, cts->xport_specific.sata.tags); 1789 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 1790 ch->pm_present = cts->xport_specific.sata.pm_present; 1791 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 1792 d->atapi = cts->xport_specific.sata.atapi; 1793 ccb->ccb_h.status = CAM_REQ_CMP; 1794 break; 1795 } 1796 case XPT_GET_TRAN_SETTINGS: 1797 /* Get default/user set transfer settings for the target */ 1798 { 1799 struct ccb_trans_settings *cts = &ccb->cts; 1800 struct fsl_sata_device *d; 1801 uint32_t status; 1802 1803 if (fsl_sata_check_ids(ch, ccb)) 1804 return; 1805 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1806 d = &ch->curr[ccb->ccb_h.target_id]; 1807 else 1808 d = &ch->user[ccb->ccb_h.target_id]; 1809 cts->protocol = PROTO_UNSPECIFIED; 1810 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1811 cts->transport = XPORT_SATA; 1812 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1813 cts->proto_specific.valid = 0; 1814 cts->xport_specific.sata.valid = 0; 1815 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 1816 (ccb->ccb_h.target_id == 15 || 1817 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 1818 status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS) & ATA_SS_SPD_MASK; 1819 if (status & 0x0f0) { 1820 cts->xport_specific.sata.revision = 1821 (status & 0x0f0) >> 4; 1822 cts->xport_specific.sata.valid |= 1823 CTS_SATA_VALID_REVISION; 1824 } 1825 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 1826 if (ch->pm_level) { 1827 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 1828 } 1829 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 1830 cts->xport_specific.sata.caps &= 1831 ch->user[ccb->ccb_h.target_id].caps; 1832 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1833 } else { 1834 cts->xport_specific.sata.revision = d->revision; 1835 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 1836 cts->xport_specific.sata.caps = d->caps; 1837 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1838 } 1839 cts->xport_specific.sata.mode = d->mode; 1840 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 1841 cts->xport_specific.sata.bytecount = d->bytecount; 1842 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 1843 cts->xport_specific.sata.pm_present = ch->pm_present; 1844 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 1845 cts->xport_specific.sata.tags = d->tags; 1846 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 1847 cts->xport_specific.sata.atapi = d->atapi; 1848 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 1849 ccb->ccb_h.status = CAM_REQ_CMP; 1850 break; 1851 } 1852 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1853 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1854 fsl_sata_reset(ch); 1855 ccb->ccb_h.status = CAM_REQ_CMP; 1856 break; 1857 case XPT_TERM_IO: /* Terminate the I/O process */ 1858 /* XXX Implement */ 1859 ccb->ccb_h.status = CAM_REQ_INVALID; 1860 break; 1861 case XPT_PATH_INQ: /* Path routing inquiry */ 1862 { 1863 struct ccb_pathinq *cpi = &ccb->cpi; 1864 1865 cpi->version_num = 1; /* XXX??? */ 1866 cpi->hba_inquiry = PI_SDTR_ABLE; 1867 cpi->hba_inquiry |= PI_TAG_ABLE; 1868 #if 0 1869 /* 1870 * XXX: CAM tries to reset port 15 if it sees port multiplier 1871 * support. Disable it for now. 1872 */ 1873 cpi->hba_inquiry |= PI_SATAPM; 1874 #endif 1875 cpi->target_sprt = 0; 1876 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 1877 cpi->hba_eng_cnt = 0; 1878 /* 1879 * XXX: This should be 15, since hardware *does* support a port 1880 * multiplier. See above. 1881 */ 1882 cpi->max_target = 0; 1883 cpi->max_lun = 0; 1884 cpi->initiator_id = 0; 1885 cpi->bus_id = cam_sim_bus(sim); 1886 cpi->base_transfer_speed = 150000; 1887 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1888 strncpy(cpi->hba_vid, "FSL SATA", HBA_IDLEN); 1889 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1890 cpi->unit_number = cam_sim_unit(sim); 1891 cpi->transport = XPORT_SATA; 1892 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1893 cpi->protocol = PROTO_ATA; 1894 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1895 cpi->maxio = MAXPHYS; 1896 cpi->ccb_h.status = CAM_REQ_CMP; 1897 break; 1898 } 1899 default: 1900 ccb->ccb_h.status = CAM_REQ_INVALID; 1901 break; 1902 } 1903 fsl_sata_done(ch, ccb); 1904 } 1905 1906 static void 1907 fsl_satapoll(struct cam_sim *sim) 1908 { 1909 struct fsl_sata_channel *ch = (struct fsl_sata_channel *)cam_sim_softc(sim); 1910 uint32_t istatus; 1911 1912 /* Read interrupt statuses and process if any. */ 1913 istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS); 1914 if (istatus != 0) 1915 fsl_sata_intr_main(ch, istatus); 1916 } 1917 MODULE_VERSION(fsl_sata, 1); 1918 MODULE_DEPEND(fsl_sata, cam, 1, 1, 1); 1919