1 /*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (c) 2017 Justin Hibbits <jhibbits@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/module.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/endian.h> 35 #include <sys/lock.h> 36 #include <sys/malloc.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 40 #include <cam/cam.h> 41 #include <cam/cam_ccb.h> 42 #include <cam/cam_sim.h> 43 #include <cam/cam_xpt_sim.h> 44 #include <cam/cam_debug.h> 45 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include "fsl_sata.h" 52 53 struct fsl_sata_channel; 54 struct fsl_sata_slot; 55 enum fsl_sata_err_type; 56 struct fsl_sata_cmd_tab; 57 58 /* local prototypes */ 59 static int fsl_sata_init(device_t dev); 60 static int fsl_sata_deinit(device_t dev); 61 static int fsl_sata_suspend(device_t dev); 62 static int fsl_sata_resume(device_t dev); 63 static void fsl_sata_pm(void *arg); 64 static void fsl_sata_intr(void *arg); 65 static void fsl_sata_intr_main(struct fsl_sata_channel *ch, uint32_t istatus); 66 static void fsl_sata_begin_transaction(struct fsl_sata_channel *ch, union ccb *ccb); 67 static void fsl_sata_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 68 static void fsl_sata_execute_transaction(struct fsl_sata_slot *slot); 69 static void fsl_sata_timeout(void *arg); 70 static void fsl_sata_end_transaction(struct fsl_sata_slot *slot, enum fsl_sata_err_type et); 71 static int fsl_sata_setup_fis(struct fsl_sata_channel *ch, struct fsl_sata_cmd_tab *ctp, union ccb *ccb, int tag); 72 static void fsl_sata_dmainit(device_t dev); 73 static void fsl_sata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 74 static void fsl_sata_dmafini(device_t dev); 75 static void fsl_sata_slotsalloc(device_t dev); 76 static void fsl_sata_slotsfree(device_t dev); 77 static void fsl_sata_reset(struct fsl_sata_channel *ch); 78 static void fsl_sata_start(struct fsl_sata_channel *ch); 79 static void fsl_sata_stop(struct fsl_sata_channel *ch); 80 81 static void fsl_sata_issue_recovery(struct fsl_sata_channel *ch); 82 static void fsl_sata_process_read_log(struct fsl_sata_channel *ch, union ccb *ccb); 83 static void fsl_sata_process_request_sense(struct fsl_sata_channel *ch, union ccb *ccb); 84 85 static void fsl_sataaction(struct cam_sim *sim, union ccb *ccb); 86 static void fsl_satapoll(struct cam_sim *sim); 87 88 static MALLOC_DEFINE(M_FSL_SATA, "FSL SATA driver", "FSL SATA driver data buffers"); 89 90 #define recovery_type spriv_field0 91 #define RECOVERY_NONE 0 92 #define RECOVERY_READ_LOG 1 93 #define RECOVERY_REQUEST_SENSE 2 94 #define recovery_slot spriv_field1 95 96 #define FSL_SATA_P_CQR 0x0 97 #define FSL_SATA_P_CAR 0x4 98 #define FSL_SATA_P_CCR 0x10 99 #define FSL_SATA_P_CER 0x18 100 #define FSL_SATA_P_DER 0x20 101 #define FSL_SATA_P_CHBA 0x24 102 #define FSL_SATA_P_HSTS 0x28 103 #define FSL_SATA_P_HSTS_HS_ON 0x80000000 104 #define FSL_SATA_P_HSTS_ME 0x00040000 105 #define FSL_SATA_P_HSTS_DLM 0x00001000 106 #define FSL_SATA_P_HSTS_FOT 0x00000200 107 #define FSL_SATA_P_HSTS_FOR 0x00000100 108 #define FSL_SATA_P_HSTS_FE 0x00000020 109 #define FSL_SATA_P_HSTS_PR 0x00000010 110 #define FSL_SATA_P_HSTS_SNTFU 0x00000004 111 #define FSL_SATA_P_HSTS_DE 0x00000002 112 #define FSL_SATA_P_HCTRL 0x2c 113 #define FSL_SATA_P_HCTRL_HC_ON 0x80000000 114 #define FSL_SATA_P_HCTRL_HC_FORCE_OFF 0x40000000 115 #define FSL_SATA_P_HCTRL_ENT 0x10000000 116 #define FSL_SATA_P_HCTRL_SNOOP 0x00000400 117 #define FSL_SATA_P_HCTRL_PM 0x00000200 118 #define FSL_SATA_P_HCTRL_FATAL 0x00000020 119 #define FSL_SATA_P_HCTRL_PHYRDY 0x00000010 120 #define FSL_SATA_P_HCTRL_SIG 0x00000008 121 #define FSL_SATA_P_HCTRL_SNTFY 0x00000004 122 #define FSL_SATA_P_HCTRL_DE 0x00000002 123 #define FSL_SATA_P_HCTRL_CC 0x00000001 124 #define FSL_SATA_P_HCTRL_INT_MASK 0x0000003f 125 #define FSL_SATA_P_CQPMP 0x30 126 #define FSL_SATA_P_SIG 0x34 127 #define FSL_SATA_P_ICC 0x38 128 #define FSL_SATA_P_ICC_ITC_M 0x1f000000 129 #define FSL_SATA_P_ICC_ITC_S 24 130 #define FSL_SATA_P_ICC_ITTCV_M 0x0007ffff 131 #define FSL_SATA_P_PCC 0x15c 132 #define FSL_SATA_P_PCC_SLUMBER 0x0000000c 133 #define FSL_SATA_P_PCC_PARTIAL 0x0000000a 134 #define FSL_SATA_PCC_LPB_EN 0x0000000e 135 136 #define FSL_SATA_MAX_SLOTS 16 137 /* FSL_SATA register defines */ 138 139 #define FSL_SATA_P_SSTS 0x100 140 #define FSL_SATA_P_SERR 0x104 141 #define FSL_SATA_P_SCTL 0x108 142 #define FSL_SATA_P_SNTF 0x10c 143 144 /* Pessimistic prognosis on number of required S/G entries */ 145 #define FSL_SATA_SG_ENTRIES 63 146 /* Command list. 16 commands. First, 1Kbyte aligned. */ 147 #define FSL_SATA_CL_OFFSET 0 148 #define FSL_SATA_CL_SIZE 16 149 /* Command tables. Up to 32 commands, Each, 4-byte aligned. */ 150 #define FSL_SATA_CT_OFFSET (FSL_SATA_CL_OFFSET + FSL_SATA_CL_SIZE * FSL_SATA_MAX_SLOTS) 151 #define FSL_SATA_CT_SIZE (96 + FSL_SATA_SG_ENTRIES * 16) 152 /* Total main work area. */ 153 #define FSL_SATA_WORK_SIZE (FSL_SATA_CT_OFFSET + FSL_SATA_CT_SIZE * FSL_SATA_MAX_SLOTS) 154 #define FSL_SATA_MAX_XFER (64 * 1024 * 1024) 155 156 /* Some convenience macros for getting the CTP and CLP */ 157 #define FSL_SATA_CTP_BUS(ch, slot) \ 158 ((ch->dma.work_bus + FSL_SATA_CT_OFFSET + (FSL_SATA_CT_SIZE * slot->slot))) 159 #define FSL_SATA_PRD_OFFSET(prd) (96 + (prd) * 16) 160 #define FSL_SATA_CTP(ch, slot) \ 161 ((struct fsl_sata_cmd_tab *)(ch->dma.work + FSL_SATA_CT_OFFSET + \ 162 (FSL_SATA_CT_SIZE * slot->slot))) 163 #define FSL_SATA_CLP(ch, slot) \ 164 ((struct fsl_sata_cmd_list *) (ch->dma.work + FSL_SATA_CL_OFFSET + \ 165 (FSL_SATA_CL_SIZE * slot->slot))) 166 167 struct fsl_sata_dma_prd { 168 uint32_t dba; 169 uint32_t reserved; 170 uint32_t reserved2; 171 uint32_t dwc_flg; /* 0 based */ 172 #define FSL_SATA_PRD_MASK 0x01fffffc /* max 32MB */ 173 #define FSL_SATA_PRD_MAX (FSL_SATA_PRD_MASK + 4) 174 #define FSL_SATA_PRD_SNOOP 0x10000000 175 #define FSL_SATA_PRD_EXT 0x80000000 176 } __packed; 177 178 struct fsl_sata_cmd_tab { 179 uint8_t cfis[32]; 180 uint8_t sfis[32]; 181 uint8_t acmd[16]; 182 uint8_t reserved[16]; 183 struct fsl_sata_dma_prd prd_tab[FSL_SATA_SG_ENTRIES]; 184 #define FSL_SATA_PRD_EXT_INDEX 15 185 #define FSL_SATA_PRD_MAX_DIRECT 16 186 } __packed; 187 188 struct fsl_sata_cmd_list { 189 uint32_t cda; /* word aligned */ 190 uint16_t fis_length; /* length in bytes (aligned to words) */ 191 uint16_t prd_length; /* PRD entries */ 192 uint32_t ttl; 193 uint32_t cmd_flags; 194 #define FSL_SATA_CMD_TAG_MASK 0x001f 195 #define FSL_SATA_CMD_ATAPI 0x0020 196 #define FSL_SATA_CMD_BIST 0x0040 197 #define FSL_SATA_CMD_RESET 0x0080 198 #define FSL_SATA_CMD_QUEUED 0x0100 199 #define FSL_SATA_CMD_SNOOP 0x0200 200 #define FSL_SATA_CMD_VBIST 0x0400 201 #define FSL_SATA_CMD_WRITE 0x0800 202 203 } __packed; 204 205 /* misc defines */ 206 #define ATA_IRQ_RID 0 207 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 208 209 struct ata_dmaslot { 210 bus_dmamap_t data_map; /* data DMA map */ 211 int nsegs; /* Number of segs loaded */ 212 }; 213 214 /* structure holding DMA related information */ 215 struct ata_dma { 216 bus_dma_tag_t work_tag; /* workspace DMA tag */ 217 bus_dmamap_t work_map; /* workspace DMA map */ 218 uint8_t *work; /* workspace */ 219 bus_addr_t work_bus; /* bus address of work */ 220 bus_dma_tag_t data_tag; /* data DMA tag */ 221 }; 222 223 enum fsl_sata_slot_states { 224 FSL_SATA_SLOT_EMPTY, 225 FSL_SATA_SLOT_LOADING, 226 FSL_SATA_SLOT_RUNNING, 227 FSL_SATA_SLOT_EXECUTING 228 }; 229 230 struct fsl_sata_slot { 231 struct fsl_sata_channel *ch; /* Channel */ 232 uint8_t slot; /* Number of this slot */ 233 enum fsl_sata_slot_states state; /* Slot state */ 234 union ccb *ccb; /* CCB occupying slot */ 235 struct ata_dmaslot dma; /* DMA data of this slot */ 236 struct callout timeout; /* Execution timeout */ 237 uint32_t ttl; 238 }; 239 240 struct fsl_sata_device { 241 int revision; 242 int mode; 243 u_int bytecount; 244 u_int atapi; 245 u_int tags; 246 u_int caps; 247 }; 248 249 /* structure describing an ATA channel */ 250 struct fsl_sata_channel { 251 device_t dev; /* Device handle */ 252 int r_mid; /* Physical channel RID */ 253 struct resource *r_mem; /* Memory of this channel */ 254 struct resource *r_irq; /* Interrupt of this channel */ 255 void *ih; /* Interrupt handle */ 256 struct ata_dma dma; /* DMA data */ 257 struct cam_sim *sim; 258 struct cam_path *path; 259 uint32_t caps; /* Controller capabilities */ 260 int pm_level; /* power management level */ 261 int devices; /* What is present */ 262 int pm_present; /* PM presence reported */ 263 264 union ccb *hold[FSL_SATA_MAX_SLOTS]; 265 struct fsl_sata_slot slot[FSL_SATA_MAX_SLOTS]; 266 uint32_t oslots; /* Occupied slots */ 267 uint32_t rslots; /* Running slots */ 268 uint32_t aslots; /* Slots with atomic commands */ 269 uint32_t eslots; /* Slots in error */ 270 uint32_t toslots; /* Slots in timeout */ 271 int lastslot; /* Last used slot */ 272 int taggedtarget; /* Last tagged target */ 273 int numrslots; /* Number of running slots */ 274 int numrslotspd[16];/* Number of running slots per dev */ 275 int numtslots; /* Number of tagged slots */ 276 int numtslotspd[16];/* Number of tagged slots per dev */ 277 int numhslots; /* Number of held slots */ 278 int recoverycmd; /* Our READ LOG active */ 279 int fatalerr; /* Fatal error happend */ 280 int resetting; /* Hard-reset in progress. */ 281 int resetpolldiv; /* Hard-reset poll divider. */ 282 union ccb *frozen; /* Frozen command */ 283 struct callout pm_timer; /* Power management events */ 284 struct callout reset_timer; /* Hard-reset timeout */ 285 286 struct fsl_sata_device user[16]; /* User-specified settings */ 287 struct fsl_sata_device curr[16]; /* Current settings */ 288 289 struct mtx_padalign mtx; /* state lock */ 290 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */ 291 int batch; /* doneq is in use */ 292 }; 293 294 enum fsl_sata_err_type { 295 FSL_SATA_ERR_NONE, /* No error */ 296 FSL_SATA_ERR_INVALID, /* Error detected by us before submitting. */ 297 FSL_SATA_ERR_INNOCENT, /* Innocent victim. */ 298 FSL_SATA_ERR_TFE, /* Task File Error. */ 299 FSL_SATA_ERR_SATA, /* SATA error. */ 300 FSL_SATA_ERR_TIMEOUT, /* Command execution timeout. */ 301 FSL_SATA_ERR_NCQ, /* NCQ command error. CCB should be put on hold 302 * until READ LOG executed to reveal error. */ 303 }; 304 305 /* macros to hide busspace uglyness */ 306 #define ATA_INL(res, offset) \ 307 bus_read_4((res), (offset)) 308 #define ATA_OUTL(res, offset, value) \ 309 bus_write_4((res), (offset), (value)) 310 311 static int 312 fsl_sata_probe(device_t dev) 313 { 314 315 if (!ofw_bus_is_compatible(dev, "fsl,pq-sata-v2") && 316 !ofw_bus_is_compatible(dev, "fsl,pq-sata")) 317 return (ENXIO); 318 319 device_set_desc_copy(dev, "Freescale Integrated SATA Controller"); 320 return (BUS_PROBE_DEFAULT); 321 } 322 323 static int 324 fsl_sata_attach(device_t dev) 325 { 326 struct fsl_sata_channel *ch = device_get_softc(dev); 327 struct cam_devq *devq; 328 int rid, error, i, sata_rev = 0; 329 330 ch->dev = dev; 331 mtx_init(&ch->mtx, "FSL SATA channel lock", NULL, MTX_DEF); 332 ch->pm_level = 0; 333 resource_int_value(device_get_name(dev), 334 device_get_unit(dev), "pm_level", &ch->pm_level); 335 STAILQ_INIT(&ch->doneq); 336 if (ch->pm_level > 3) 337 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 338 resource_int_value(device_get_name(dev), 339 device_get_unit(dev), "sata_rev", &sata_rev); 340 for (i = 0; i < 16; i++) { 341 ch->user[i].revision = sata_rev; 342 ch->user[i].mode = 0; 343 ch->user[i].bytecount = 8192; 344 ch->user[i].tags = FSL_SATA_MAX_SLOTS; 345 ch->user[i].caps = 0; 346 ch->curr[i] = ch->user[i]; 347 if (ch->pm_level) { 348 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 349 CTS_SATA_CAPS_D_PMREQ; 350 } 351 ch->user[i].caps |= CTS_SATA_CAPS_H_AN; 352 } 353 ch->r_mid = 0; 354 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 355 &ch->r_mid, RF_ACTIVE | RF_LITTLEENDIAN))) 356 return (ENXIO); 357 fsl_sata_dmainit(dev); 358 fsl_sata_slotsalloc(dev); 359 fsl_sata_init(dev); 360 rid = ATA_IRQ_RID; 361 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 362 &rid, RF_SHAREABLE | RF_ACTIVE))) { 363 device_printf(dev, "Unable to map interrupt\n"); 364 error = ENXIO; 365 goto err0; 366 } 367 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 368 fsl_sata_intr, ch, &ch->ih))) { 369 device_printf(dev, "Unable to setup interrupt\n"); 370 error = ENXIO; 371 goto err1; 372 } 373 mtx_lock(&ch->mtx); 374 /* Create the device queue for our SIM. */ 375 devq = cam_simq_alloc(FSL_SATA_MAX_SLOTS); 376 if (devq == NULL) { 377 device_printf(dev, "Unable to allocate simq\n"); 378 error = ENOMEM; 379 goto err1; 380 } 381 /* Construct SIM entry */ 382 ch->sim = cam_sim_alloc(fsl_sataaction, fsl_satapoll, "fslsata", ch, 383 device_get_unit(dev), (struct mtx *)&ch->mtx, 2, FSL_SATA_MAX_SLOTS, 384 devq); 385 if (ch->sim == NULL) { 386 cam_simq_free(devq); 387 device_printf(dev, "unable to allocate sim\n"); 388 error = ENOMEM; 389 goto err1; 390 } 391 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 392 device_printf(dev, "unable to register xpt bus\n"); 393 error = ENXIO; 394 goto err2; 395 } 396 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 397 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 398 device_printf(dev, "unable to create path\n"); 399 error = ENXIO; 400 goto err3; 401 } 402 if (ch->pm_level > 3) { 403 callout_reset(&ch->pm_timer, 404 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 405 fsl_sata_pm, ch); 406 } 407 mtx_unlock(&ch->mtx); 408 return (0); 409 410 err3: 411 xpt_bus_deregister(cam_sim_path(ch->sim)); 412 err2: 413 cam_sim_free(ch->sim, /*free_devq*/TRUE); 414 err1: 415 mtx_unlock(&ch->mtx); 416 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 417 err0: 418 bus_release_resource(dev, SYS_RES_MEMORY, ch->r_mid, ch->r_mem); 419 mtx_destroy(&ch->mtx); 420 return (error); 421 } 422 423 static int 424 fsl_sata_detach(device_t dev) 425 { 426 struct fsl_sata_channel *ch = device_get_softc(dev); 427 428 mtx_lock(&ch->mtx); 429 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 430 431 xpt_free_path(ch->path); 432 xpt_bus_deregister(cam_sim_path(ch->sim)); 433 cam_sim_free(ch->sim, /*free_devq*/TRUE); 434 mtx_unlock(&ch->mtx); 435 436 if (ch->pm_level > 3) 437 callout_drain(&ch->pm_timer); 438 bus_teardown_intr(dev, ch->r_irq, ch->ih); 439 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 440 441 fsl_sata_deinit(dev); 442 fsl_sata_slotsfree(dev); 443 fsl_sata_dmafini(dev); 444 445 bus_release_resource(dev, SYS_RES_MEMORY, ch->r_mid, ch->r_mem); 446 mtx_destroy(&ch->mtx); 447 return (0); 448 } 449 450 static int 451 fsl_sata_wait_register(struct fsl_sata_channel *ch, bus_size_t off, 452 unsigned int mask, unsigned int val, int t) 453 { 454 int timeout = 0; 455 uint32_t rval; 456 457 while (((rval = ATA_INL(ch->r_mem, off)) & mask) != val) { 458 if (timeout > t) { 459 return (EBUSY); 460 } 461 DELAY(1000); 462 timeout++; 463 } 464 return (0); 465 } 466 467 static int 468 fsl_sata_init(device_t dev) 469 { 470 struct fsl_sata_channel *ch = device_get_softc(dev); 471 uint64_t work; 472 uint32_t r; 473 474 /* Disable port interrupts */ 475 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 476 r &= ~FSL_SATA_P_HCTRL_HC_ON; 477 r |= FSL_SATA_P_HCTRL_HC_FORCE_OFF; 478 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r & ~FSL_SATA_P_HCTRL_INT_MASK); 479 fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 480 FSL_SATA_P_HSTS_HS_ON, 0, 1000); 481 /* Setup work areas */ 482 work = ch->dma.work_bus + FSL_SATA_CL_OFFSET; 483 ATA_OUTL(ch->r_mem, FSL_SATA_P_CHBA, work); 484 r &= ~FSL_SATA_P_HCTRL_ENT; 485 r &= ~FSL_SATA_P_HCTRL_PM; 486 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r); 487 r = ATA_INL(ch->r_mem, FSL_SATA_P_PCC); 488 ATA_OUTL(ch->r_mem, FSL_SATA_P_PCC, r & ~FSL_SATA_PCC_LPB_EN); 489 ATA_OUTL(ch->r_mem, FSL_SATA_P_ICC, (1 << FSL_SATA_P_ICC_ITC_S)); 490 fsl_sata_start(ch); 491 return (0); 492 } 493 494 static int 495 fsl_sata_deinit(device_t dev) 496 { 497 struct fsl_sata_channel *ch = device_get_softc(dev); 498 uint32_t r; 499 500 /* Disable port interrupts. */ 501 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 502 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r & ~FSL_SATA_P_HCTRL_INT_MASK); 503 /* Reset command register. */ 504 fsl_sata_stop(ch); 505 /* Allow everything, including partial and slumber modes. */ 506 ATA_OUTL(ch->r_mem, FSL_SATA_P_SCTL, 0); 507 DELAY(100); 508 /* Disable PHY. */ 509 ATA_OUTL(ch->r_mem, FSL_SATA_P_SCTL, ATA_SC_DET_DISABLE); 510 r = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 511 /* Turn off the controller. */ 512 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, r & ~FSL_SATA_P_HCTRL_HC_ON); 513 return (0); 514 } 515 516 static int 517 fsl_sata_suspend(device_t dev) 518 { 519 struct fsl_sata_channel *ch = device_get_softc(dev); 520 521 mtx_lock(&ch->mtx); 522 xpt_freeze_simq(ch->sim, 1); 523 while (ch->oslots) 524 msleep(ch, &ch->mtx, PRIBIO, "fsl_satasusp", hz/100); 525 fsl_sata_deinit(dev); 526 mtx_unlock(&ch->mtx); 527 return (0); 528 } 529 530 static int 531 fsl_sata_resume(device_t dev) 532 { 533 struct fsl_sata_channel *ch = device_get_softc(dev); 534 535 mtx_lock(&ch->mtx); 536 fsl_sata_init(dev); 537 fsl_sata_reset(ch); 538 xpt_release_simq(ch->sim, TRUE); 539 mtx_unlock(&ch->mtx); 540 return (0); 541 } 542 543 static device_method_t fsl_satach_methods[] = { 544 DEVMETHOD(device_probe, fsl_sata_probe), 545 DEVMETHOD(device_attach, fsl_sata_attach), 546 DEVMETHOD(device_detach, fsl_sata_detach), 547 DEVMETHOD(device_suspend, fsl_sata_suspend), 548 DEVMETHOD(device_resume, fsl_sata_resume), 549 DEVMETHOD_END 550 }; 551 552 static driver_t fsl_satach_driver = { 553 "fslsata", 554 fsl_satach_methods, 555 sizeof(struct fsl_sata_channel) 556 }; 557 558 DRIVER_MODULE(fsl_satach, simplebus, fsl_satach_driver, NULL, NULL); 559 560 struct fsl_sata_dc_cb_args { 561 bus_addr_t maddr; 562 int error; 563 }; 564 565 static void 566 fsl_sata_dmainit(device_t dev) 567 { 568 struct fsl_sata_channel *ch = device_get_softc(dev); 569 struct fsl_sata_dc_cb_args dcba; 570 571 /* Command area. */ 572 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 573 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 574 NULL, NULL, FSL_SATA_WORK_SIZE, 1, FSL_SATA_WORK_SIZE, 575 0, NULL, NULL, &ch->dma.work_tag)) 576 goto error; 577 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 578 BUS_DMA_ZERO, &ch->dma.work_map)) 579 goto error; 580 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 581 FSL_SATA_WORK_SIZE, fsl_sata_dmasetupc_cb, &dcba, 0) || dcba.error) { 582 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 583 goto error; 584 } 585 ch->dma.work_bus = dcba.maddr; 586 /* Data area. */ 587 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0, 588 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 589 NULL, NULL, FSL_SATA_MAX_XFER, 590 FSL_SATA_SG_ENTRIES - 1, FSL_SATA_PRD_MAX, 591 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 592 goto error; 593 } 594 if (bootverbose) 595 device_printf(dev, "work area: %p\n", ch->dma.work); 596 return; 597 598 error: 599 device_printf(dev, "WARNING - DMA initialization failed\n"); 600 fsl_sata_dmafini(dev); 601 } 602 603 static void 604 fsl_sata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 605 { 606 struct fsl_sata_dc_cb_args *dcba = (struct fsl_sata_dc_cb_args *)xsc; 607 608 if (!(dcba->error = error)) 609 dcba->maddr = segs[0].ds_addr; 610 } 611 612 static void 613 fsl_sata_dmafini(device_t dev) 614 { 615 struct fsl_sata_channel *ch = device_get_softc(dev); 616 617 if (ch->dma.data_tag) { 618 bus_dma_tag_destroy(ch->dma.data_tag); 619 ch->dma.data_tag = NULL; 620 } 621 if (ch->dma.work_bus) { 622 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 623 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 624 ch->dma.work_bus = 0; 625 ch->dma.work = NULL; 626 } 627 if (ch->dma.work_tag) { 628 bus_dma_tag_destroy(ch->dma.work_tag); 629 ch->dma.work_tag = NULL; 630 } 631 } 632 633 static void 634 fsl_sata_slotsalloc(device_t dev) 635 { 636 struct fsl_sata_channel *ch = device_get_softc(dev); 637 int i; 638 639 /* Alloc and setup command/dma slots */ 640 bzero(ch->slot, sizeof(ch->slot)); 641 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 642 struct fsl_sata_slot *slot = &ch->slot[i]; 643 644 slot->ch = ch; 645 slot->slot = i; 646 slot->state = FSL_SATA_SLOT_EMPTY; 647 slot->ccb = NULL; 648 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 649 650 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 651 device_printf(ch->dev, "FAILURE - create data_map\n"); 652 } 653 } 654 655 static void 656 fsl_sata_slotsfree(device_t dev) 657 { 658 struct fsl_sata_channel *ch = device_get_softc(dev); 659 int i; 660 661 /* Free all dma slots */ 662 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 663 struct fsl_sata_slot *slot = &ch->slot[i]; 664 665 callout_drain(&slot->timeout); 666 if (slot->dma.data_map) { 667 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 668 slot->dma.data_map = NULL; 669 } 670 } 671 } 672 673 static int 674 fsl_sata_phy_check_events(struct fsl_sata_channel *ch, u_int32_t serr) 675 { 676 677 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 678 ((ch->pm_level != 0) && (serr & ATA_SE_EXCHANGED))) { 679 u_int32_t status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS); 680 union ccb *ccb; 681 682 if (bootverbose) { 683 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 684 device_printf(ch->dev, "CONNECT requested\n"); 685 else 686 device_printf(ch->dev, "DISCONNECT requested\n"); 687 } 688 /* Issue soft reset */ 689 xpt_async(AC_BUS_RESET, ch->path, NULL); 690 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 691 return (0); 692 if (xpt_create_path(&ccb->ccb_h.path, NULL, 693 cam_sim_path(ch->sim), 694 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 695 xpt_free_ccb(ccb); 696 return (0); 697 } 698 xpt_rescan(ccb); 699 return (1); 700 } 701 return (0); 702 } 703 704 static void 705 fsl_sata_notify_events(struct fsl_sata_channel *ch, u_int32_t status) 706 { 707 struct cam_path *dpath; 708 int i; 709 710 ATA_OUTL(ch->r_mem, FSL_SATA_P_SNTF, status); 711 if (bootverbose) 712 device_printf(ch->dev, "SNTF 0x%04x\n", status); 713 for (i = 0; i < 16; i++) { 714 if ((status & (1 << i)) == 0) 715 continue; 716 if (xpt_create_path(&dpath, NULL, 717 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 718 xpt_async(AC_SCSI_AEN, dpath, NULL); 719 xpt_free_path(dpath); 720 } 721 } 722 } 723 724 static void 725 fsl_sata_done(struct fsl_sata_channel *ch, union ccb *ccb) 726 { 727 728 mtx_assert(&ch->mtx, MA_OWNED); 729 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 730 ch->batch == 0) { 731 xpt_done(ccb); 732 return; 733 } 734 735 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 736 } 737 738 static void 739 fsl_sata_intr(void *arg) 740 { 741 struct fsl_sata_channel *ch = (struct fsl_sata_channel *)arg; 742 struct ccb_hdr *ccb_h; 743 uint32_t istatus; 744 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 745 746 /* Read interrupt statuses. */ 747 istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & 0x7ffff; 748 if ((istatus & 0x3f) == 0) 749 return; 750 751 mtx_lock(&ch->mtx); 752 ch->batch = 1; 753 fsl_sata_intr_main(ch, istatus); 754 ch->batch = 0; 755 /* 756 * Prevent the possibility of issues caused by processing the queue 757 * while unlocked below by moving the contents to a local queue. 758 */ 759 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 760 mtx_unlock(&ch->mtx); 761 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 762 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 763 xpt_done_direct((union ccb *)ccb_h); 764 } 765 /* Clear interrupt statuses. */ 766 ATA_OUTL(ch->r_mem, FSL_SATA_P_HSTS, istatus & 0x3f); 767 768 } 769 770 static void 771 fsl_sata_pm(void *arg) 772 { 773 struct fsl_sata_channel *ch = (struct fsl_sata_channel *)arg; 774 uint32_t work; 775 776 if (ch->numrslots != 0) 777 return; 778 work = ATA_INL(ch->r_mem, FSL_SATA_P_PCC) & ~FSL_SATA_PCC_LPB_EN; 779 if (ch->pm_level == 4) 780 work |= FSL_SATA_P_PCC_PARTIAL; 781 else 782 work |= FSL_SATA_P_PCC_SLUMBER; 783 ATA_OUTL(ch->r_mem, FSL_SATA_P_PCC, work); 784 } 785 786 /* XXX: interrupt todo */ 787 static void 788 fsl_sata_intr_main(struct fsl_sata_channel *ch, uint32_t istatus) 789 { 790 uint32_t cer, der, serr = 0, sntf = 0, ok, err; 791 enum fsl_sata_err_type et; 792 int i; 793 794 /* Complete all successful commands. */ 795 ok = ATA_INL(ch->r_mem, FSL_SATA_P_CCR); 796 /* Mark all commands complete, to complete the interrupt. */ 797 ATA_OUTL(ch->r_mem, FSL_SATA_P_CCR, ok); 798 if (ch->aslots == 0 && ok != 0) { 799 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 800 if (((ok >> i) & 1) && ch->slot[i].ccb != NULL) 801 fsl_sata_end_transaction(&ch->slot[i], 802 FSL_SATA_ERR_NONE); 803 } 804 } 805 /* Read command statuses. */ 806 if (istatus & FSL_SATA_P_HSTS_SNTFU) 807 sntf = ATA_INL(ch->r_mem, FSL_SATA_P_SNTF); 808 /* XXX: Process PHY events */ 809 serr = ATA_INL(ch->r_mem, FSL_SATA_P_SERR); 810 ATA_OUTL(ch->r_mem, FSL_SATA_P_SERR, serr); 811 if (istatus & (FSL_SATA_P_HSTS_PR)) { 812 if (serr) { 813 fsl_sata_phy_check_events(ch, serr); 814 } 815 } 816 /* Process command errors */ 817 err = (istatus & (FSL_SATA_P_HSTS_FE | FSL_SATA_P_HSTS_DE)); 818 cer = ATA_INL(ch->r_mem, FSL_SATA_P_CER); 819 ATA_OUTL(ch->r_mem, FSL_SATA_P_CER, cer); 820 der = ATA_INL(ch->r_mem, FSL_SATA_P_DER); 821 ATA_OUTL(ch->r_mem, FSL_SATA_P_DER, der); 822 /* On error, complete the rest of commands with error statuses. */ 823 if (err) { 824 if (ch->frozen) { 825 union ccb *fccb = ch->frozen; 826 ch->frozen = NULL; 827 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 828 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 829 xpt_freeze_devq(fccb->ccb_h.path, 1); 830 fccb->ccb_h.status |= CAM_DEV_QFRZN; 831 } 832 fsl_sata_done(ch, fccb); 833 } 834 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 835 if (ch->slot[i].ccb == NULL) 836 continue; 837 if ((cer & (1 << i)) != 0) 838 et = FSL_SATA_ERR_TFE; 839 else if ((der & (1 << ch->slot[i].ccb->ccb_h.target_id)) != 0) 840 et = FSL_SATA_ERR_SATA; 841 else 842 et = FSL_SATA_ERR_INVALID; 843 fsl_sata_end_transaction(&ch->slot[i], et); 844 } 845 } 846 /* Process NOTIFY events */ 847 if (sntf) 848 fsl_sata_notify_events(ch, sntf); 849 } 850 851 /* Must be called with channel locked. */ 852 static int 853 fsl_sata_check_collision(struct fsl_sata_channel *ch, union ccb *ccb) 854 { 855 int t = ccb->ccb_h.target_id; 856 857 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 858 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 859 /* Tagged command while we have no supported tag free. */ 860 if (((~ch->oslots) & (0xffff >> (16 - ch->curr[t].tags))) == 0) 861 return (1); 862 /* Tagged command while untagged are active. */ 863 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 864 return (1); 865 } else { 866 /* Untagged command while tagged are active. */ 867 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 868 return (1); 869 } 870 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 871 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 872 /* Atomic command while anything active. */ 873 if (ch->numrslots != 0) 874 return (1); 875 } 876 /* We have some atomic command running. */ 877 if (ch->aslots != 0) 878 return (1); 879 return (0); 880 } 881 882 /* Must be called with channel locked. */ 883 static void 884 fsl_sata_begin_transaction(struct fsl_sata_channel *ch, union ccb *ccb) 885 { 886 struct fsl_sata_slot *slot; 887 int tag, tags; 888 889 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 890 ("fsl_sata_begin_transaction func_code=0x%x\n", ccb->ccb_h.func_code)); 891 /* Choose empty slot. */ 892 tags = FSL_SATA_MAX_SLOTS; 893 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 894 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 895 tags = ch->curr[ccb->ccb_h.target_id].tags; 896 if (ch->lastslot + 1 < tags) 897 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 898 else 899 tag = 0; 900 if (tag == 0 || tag + ch->lastslot >= tags) 901 tag = ffs(~ch->oslots) - 1; 902 else 903 tag += ch->lastslot; 904 ch->lastslot = tag; 905 /* Occupy chosen slot. */ 906 slot = &ch->slot[tag]; 907 slot->ccb = ccb; 908 slot->ttl = 0; 909 /* Stop PM timer. */ 910 if (ch->numrslots == 0 && ch->pm_level > 3) 911 callout_stop(&ch->pm_timer); 912 /* Update channel stats. */ 913 ch->oslots |= (1 << tag); 914 ch->numrslots++; 915 ch->numrslotspd[ccb->ccb_h.target_id]++; 916 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 917 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 918 ch->numtslots++; 919 ch->numtslotspd[ccb->ccb_h.target_id]++; 920 ch->taggedtarget = ccb->ccb_h.target_id; 921 } 922 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 923 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 924 ch->aslots |= (1 << tag); 925 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 926 slot->state = FSL_SATA_SLOT_LOADING; 927 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 928 fsl_sata_dmasetprd, slot, 0); 929 } else { 930 slot->dma.nsegs = 0; 931 fsl_sata_execute_transaction(slot); 932 } 933 934 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 935 ("fsl_sata_begin_transaction exit\n")); 936 } 937 938 /* Locked by busdma engine. */ 939 static void 940 fsl_sata_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 941 { 942 struct fsl_sata_slot *slot = arg; 943 struct fsl_sata_channel *ch = slot->ch; 944 struct fsl_sata_cmd_tab *ctp; 945 struct fsl_sata_dma_prd *prd; 946 int i, j, len, extlen; 947 948 if (error) { 949 device_printf(ch->dev, "DMA load error %d\n", error); 950 fsl_sata_end_transaction(slot, FSL_SATA_ERR_INVALID); 951 return; 952 } 953 KASSERT(nsegs <= FSL_SATA_SG_ENTRIES - 1, 954 ("too many DMA segment entries\n")); 955 /* Get a piece of the workspace for this request */ 956 ctp = FSL_SATA_CTP(ch, slot); 957 /* Fill S/G table */ 958 prd = &ctp->prd_tab[0]; 959 for (i = 0, j = 0; i < nsegs; i++, j++) { 960 if (j == FSL_SATA_PRD_EXT_INDEX && 961 FSL_SATA_PRD_MAX_DIRECT < nsegs) { 962 prd[j].dba = htole32(FSL_SATA_CTP_BUS(ch, slot) + 963 FSL_SATA_PRD_OFFSET(j+1)); 964 j++; 965 extlen = 0; 966 } 967 len = segs[i].ds_len; 968 len = roundup2(len, sizeof(uint32_t)); 969 prd[j].dba = htole32((uint32_t)segs[i].ds_addr); 970 prd[j].dwc_flg = htole32(FSL_SATA_PRD_SNOOP | len); 971 slot->ttl += len; 972 if (j > FSL_SATA_PRD_MAX_DIRECT) 973 extlen += len; 974 } 975 slot->dma.nsegs = j; 976 if (j > FSL_SATA_PRD_MAX_DIRECT) 977 prd[FSL_SATA_PRD_EXT_INDEX].dwc_flg = 978 htole32(FSL_SATA_PRD_SNOOP | FSL_SATA_PRD_EXT | extlen); 979 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 980 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 981 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 982 fsl_sata_execute_transaction(slot); 983 } 984 985 /* Must be called with channel locked. */ 986 static void 987 fsl_sata_execute_transaction(struct fsl_sata_slot *slot) 988 { 989 struct fsl_sata_channel *ch = slot->ch; 990 struct fsl_sata_cmd_tab *ctp; 991 struct fsl_sata_cmd_list *clp; 992 union ccb *ccb = slot->ccb; 993 int port = ccb->ccb_h.target_id & 0x0f; 994 int fis_size, i, softreset; 995 uint32_t tmp; 996 uint32_t cmd_flags = FSL_SATA_CMD_WRITE | FSL_SATA_CMD_SNOOP; 997 998 softreset = 0; 999 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 1000 ("fsl_sata_execute_transaction func_code=0x%x\n", ccb->ccb_h.func_code)); 1001 /* Get a piece of the workspace for this request */ 1002 ctp = FSL_SATA_CTP(ch, slot); 1003 /* Setup the FIS for this request */ 1004 if (!(fis_size = fsl_sata_setup_fis(ch, ctp, ccb, slot->slot))) { 1005 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1006 fsl_sata_end_transaction(slot, FSL_SATA_ERR_INVALID); 1007 return; 1008 } 1009 /* Setup the command list entry */ 1010 clp = FSL_SATA_CLP(ch, slot); 1011 clp->fis_length = htole16(fis_size); 1012 clp->prd_length = htole16(slot->dma.nsegs); 1013 /* Special handling for Soft Reset command. */ 1014 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1015 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1016 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1017 softreset = 1; 1018 cmd_flags |= FSL_SATA_CMD_RESET; 1019 } else { 1020 /* Prepare FIS receive area for check. */ 1021 for (i = 0; i < 32; i++) 1022 ctp->sfis[i] = 0xff; 1023 softreset = 2; 1024 } 1025 } 1026 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) 1027 cmd_flags |= FSL_SATA_CMD_QUEUED; 1028 clp->cmd_flags = htole32(cmd_flags | 1029 (ccb->ccb_h.func_code == XPT_SCSI_IO ? FSL_SATA_CMD_ATAPI : 0) | 1030 slot->slot); 1031 clp->ttl = htole32(slot->ttl); 1032 clp->cda = htole32(FSL_SATA_CTP_BUS(ch, slot)); 1033 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1034 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1035 /* Issue command to the controller. */ 1036 slot->state = FSL_SATA_SLOT_RUNNING; 1037 ch->rslots |= (1 << slot->slot); 1038 ATA_OUTL(ch->r_mem, FSL_SATA_P_CQPMP, port); 1039 ATA_OUTL(ch->r_mem, FSL_SATA_P_CQR, (1 << slot->slot)); 1040 /* Device reset commands don't interrupt. Poll them. */ 1041 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1042 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1043 int count, timeout = ccb->ccb_h.timeout * 100; 1044 enum fsl_sata_err_type et = FSL_SATA_ERR_NONE; 1045 1046 for (count = 0; count < timeout; count++) { 1047 DELAY(10); 1048 tmp = 0; 1049 if (softreset == 2) { 1050 tmp = ATA_INL(ch->r_mem, FSL_SATA_P_SIG); 1051 if (tmp != 0 && tmp != 0xffffffff) 1052 break; 1053 continue; 1054 } 1055 if ((ATA_INL(ch->r_mem, FSL_SATA_P_CCR) & (1 << slot->slot)) != 0) 1056 break; 1057 } 1058 1059 if (timeout && (count >= timeout)) { 1060 device_printf(ch->dev, "Poll timeout on slot %d port %d (round %d)\n", 1061 slot->slot, port, softreset); 1062 device_printf(ch->dev, "hsts %08x cqr %08x ccr %08x ss %08x " 1063 "rs %08x cer %08x der %08x serr %08x car %08x sig %08x\n", 1064 ATA_INL(ch->r_mem, FSL_SATA_P_HSTS), 1065 ATA_INL(ch->r_mem, FSL_SATA_P_CQR), 1066 ATA_INL(ch->r_mem, FSL_SATA_P_CCR), 1067 ATA_INL(ch->r_mem, FSL_SATA_P_SSTS), ch->rslots, 1068 ATA_INL(ch->r_mem, FSL_SATA_P_CER), 1069 ATA_INL(ch->r_mem, FSL_SATA_P_DER), 1070 ATA_INL(ch->r_mem, FSL_SATA_P_SERR), 1071 ATA_INL(ch->r_mem, FSL_SATA_P_CAR), 1072 ATA_INL(ch->r_mem, FSL_SATA_P_SIG)); 1073 et = FSL_SATA_ERR_TIMEOUT; 1074 } 1075 1076 fsl_sata_end_transaction(slot, et); 1077 return; 1078 } 1079 /* Start command execution timeout */ 1080 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1081 0, fsl_sata_timeout, slot, 0); 1082 return; 1083 } 1084 1085 /* Must be called with channel locked. */ 1086 static void 1087 fsl_sata_process_timeout(struct fsl_sata_channel *ch) 1088 { 1089 int i; 1090 1091 mtx_assert(&ch->mtx, MA_OWNED); 1092 /* Handle the rest of commands. */ 1093 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1094 /* Do we have a running request on slot? */ 1095 if (ch->slot[i].state < FSL_SATA_SLOT_RUNNING) 1096 continue; 1097 fsl_sata_end_transaction(&ch->slot[i], FSL_SATA_ERR_TIMEOUT); 1098 } 1099 } 1100 1101 /* Must be called with channel locked. */ 1102 static void 1103 fsl_sata_rearm_timeout(struct fsl_sata_channel *ch) 1104 { 1105 int i; 1106 1107 mtx_assert(&ch->mtx, MA_OWNED); 1108 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1109 struct fsl_sata_slot *slot = &ch->slot[i]; 1110 1111 /* Do we have a running request on slot? */ 1112 if (slot->state < FSL_SATA_SLOT_RUNNING) 1113 continue; 1114 if ((ch->toslots & (1 << i)) == 0) 1115 continue; 1116 callout_reset_sbt(&slot->timeout, 1117 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1118 fsl_sata_timeout, slot, 0); 1119 } 1120 } 1121 1122 /* Locked by callout mechanism. */ 1123 static void 1124 fsl_sata_timeout(void *arg) 1125 { 1126 struct fsl_sata_slot *slot = arg; 1127 struct fsl_sata_channel *ch = slot->ch; 1128 device_t dev = ch->dev; 1129 uint32_t sstatus; 1130 1131 /* Check for stale timeout. */ 1132 if (slot->state < FSL_SATA_SLOT_RUNNING) 1133 return; 1134 1135 /* Check if slot was not being executed last time we checked. */ 1136 if (slot->state < FSL_SATA_SLOT_EXECUTING) { 1137 /* Check if slot started executing. */ 1138 sstatus = ATA_INL(ch->r_mem, FSL_SATA_P_CAR); 1139 if ((sstatus & (1 << slot->slot)) != 0) 1140 slot->state = FSL_SATA_SLOT_EXECUTING; 1141 1142 callout_reset_sbt(&slot->timeout, 1143 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1144 fsl_sata_timeout, slot, 0); 1145 return; 1146 } 1147 1148 device_printf(dev, "Timeout on slot %d port %d\n", 1149 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1150 1151 /* Handle frozen command. */ 1152 if (ch->frozen) { 1153 union ccb *fccb = ch->frozen; 1154 ch->frozen = NULL; 1155 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1156 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1157 xpt_freeze_devq(fccb->ccb_h.path, 1); 1158 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1159 } 1160 fsl_sata_done(ch, fccb); 1161 } 1162 if (ch->toslots == 0) 1163 xpt_freeze_simq(ch->sim, 1); 1164 ch->toslots |= (1 << slot->slot); 1165 if ((ch->rslots & ~ch->toslots) == 0) 1166 fsl_sata_process_timeout(ch); 1167 else 1168 device_printf(dev, " ... waiting for slots %08x\n", 1169 ch->rslots & ~ch->toslots); 1170 } 1171 1172 /* Must be called with channel locked. */ 1173 static void 1174 fsl_sata_end_transaction(struct fsl_sata_slot *slot, enum fsl_sata_err_type et) 1175 { 1176 struct fsl_sata_channel *ch = slot->ch; 1177 union ccb *ccb = slot->ccb; 1178 struct fsl_sata_cmd_list *clp; 1179 int lastto; 1180 uint32_t sig; 1181 1182 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1183 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1184 clp = FSL_SATA_CLP(ch, slot); 1185 /* Read result registers to the result struct */ 1186 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1187 struct ata_res *res = &ccb->ataio.res; 1188 1189 if ((et == FSL_SATA_ERR_TFE) || 1190 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1191 struct fsl_sata_cmd_tab *ctp = FSL_SATA_CTP(ch, slot); 1192 uint8_t *fis = ctp->sfis; 1193 1194 res->status = fis[2]; 1195 res->error = fis[3]; 1196 res->lba_low = fis[4]; 1197 res->lba_mid = fis[5]; 1198 res->lba_high = fis[6]; 1199 res->device = fis[7]; 1200 res->lba_low_exp = fis[8]; 1201 res->lba_mid_exp = fis[9]; 1202 res->lba_high_exp = fis[10]; 1203 res->sector_count = fis[12]; 1204 res->sector_count_exp = fis[13]; 1205 1206 if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1207 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1208 sig = ATA_INL(ch->r_mem, FSL_SATA_P_SIG); 1209 res->lba_high = sig >> 24; 1210 res->lba_mid = sig >> 16; 1211 res->lba_low = sig >> 8; 1212 res->sector_count = sig; 1213 } 1214 } else 1215 bzero(res, sizeof(*res)); 1216 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1217 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1218 ccb->ataio.resid = 1219 ccb->ataio.dxfer_len - le32toh(clp->ttl); 1220 } 1221 } else { 1222 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1223 ccb->csio.resid = 1224 ccb->csio.dxfer_len - le32toh(clp->ttl); 1225 } 1226 } 1227 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1228 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1229 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1230 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1231 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1232 } 1233 if (et != FSL_SATA_ERR_NONE) 1234 ch->eslots |= (1 << slot->slot); 1235 /* In case of error, freeze device for proper recovery. */ 1236 if ((et != FSL_SATA_ERR_NONE) && (!ch->recoverycmd) && 1237 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1238 xpt_freeze_devq(ccb->ccb_h.path, 1); 1239 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1240 } 1241 /* Set proper result status. */ 1242 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1243 switch (et) { 1244 case FSL_SATA_ERR_NONE: 1245 ccb->ccb_h.status |= CAM_REQ_CMP; 1246 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1247 ccb->csio.scsi_status = SCSI_STATUS_OK; 1248 break; 1249 case FSL_SATA_ERR_INVALID: 1250 ch->fatalerr = 1; 1251 ccb->ccb_h.status |= CAM_REQ_INVALID; 1252 break; 1253 case FSL_SATA_ERR_INNOCENT: 1254 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1255 break; 1256 case FSL_SATA_ERR_TFE: 1257 case FSL_SATA_ERR_NCQ: 1258 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1259 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1260 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1261 } else { 1262 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1263 } 1264 break; 1265 case FSL_SATA_ERR_SATA: 1266 ch->fatalerr = 1; 1267 if (!ch->recoverycmd) { 1268 xpt_freeze_simq(ch->sim, 1); 1269 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1270 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1271 } 1272 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1273 break; 1274 case FSL_SATA_ERR_TIMEOUT: 1275 if (!ch->recoverycmd) { 1276 xpt_freeze_simq(ch->sim, 1); 1277 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1278 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1279 } 1280 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1281 break; 1282 default: 1283 ch->fatalerr = 1; 1284 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1285 } 1286 /* Free slot. */ 1287 ch->oslots &= ~(1 << slot->slot); 1288 ch->rslots &= ~(1 << slot->slot); 1289 ch->aslots &= ~(1 << slot->slot); 1290 slot->state = FSL_SATA_SLOT_EMPTY; 1291 slot->ccb = NULL; 1292 /* Update channel stats. */ 1293 ch->numrslots--; 1294 ch->numrslotspd[ccb->ccb_h.target_id]--; 1295 ATA_OUTL(ch->r_mem, FSL_SATA_P_CCR, 1 << slot->slot); 1296 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1297 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1298 ch->numtslots--; 1299 ch->numtslotspd[ccb->ccb_h.target_id]--; 1300 } 1301 /* Cancel timeout state if request completed normally. */ 1302 if (et != FSL_SATA_ERR_TIMEOUT) { 1303 lastto = (ch->toslots == (1 << slot->slot)); 1304 ch->toslots &= ~(1 << slot->slot); 1305 if (lastto) 1306 xpt_release_simq(ch->sim, TRUE); 1307 } 1308 /* If it was first request of reset sequence and there is no error, 1309 * proceed to second request. */ 1310 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1311 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1312 (ccb->ataio.cmd.control & ATA_A_RESET) && 1313 et == FSL_SATA_ERR_NONE) { 1314 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1315 fsl_sata_begin_transaction(ch, ccb); 1316 return; 1317 } 1318 /* If it was our READ LOG command - process it. */ 1319 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1320 fsl_sata_process_read_log(ch, ccb); 1321 /* If it was our REQUEST SENSE command - process it. */ 1322 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1323 fsl_sata_process_request_sense(ch, ccb); 1324 /* If it was NCQ or ATAPI command error, put result on hold. */ 1325 } else if (et == FSL_SATA_ERR_NCQ || 1326 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1327 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1328 ch->hold[slot->slot] = ccb; 1329 ch->numhslots++; 1330 } else 1331 fsl_sata_done(ch, ccb); 1332 /* If we have no other active commands, ... */ 1333 if (ch->rslots == 0) { 1334 /* if there was fatal error - reset port. */ 1335 if (ch->toslots != 0 || ch->fatalerr) { 1336 fsl_sata_reset(ch); 1337 } else { 1338 /* if we have slots in error, we can reinit port. */ 1339 if (ch->eslots != 0) { 1340 fsl_sata_stop(ch); 1341 fsl_sata_start(ch); 1342 } 1343 /* if there commands on hold, we can do READ LOG. */ 1344 if (!ch->recoverycmd && ch->numhslots) 1345 fsl_sata_issue_recovery(ch); 1346 } 1347 /* If all the rest of commands are in timeout - give them chance. */ 1348 } else if ((ch->rslots & ~ch->toslots) == 0 && 1349 et != FSL_SATA_ERR_TIMEOUT) 1350 fsl_sata_rearm_timeout(ch); 1351 /* Unfreeze frozen command. */ 1352 if (ch->frozen && !fsl_sata_check_collision(ch, ch->frozen)) { 1353 union ccb *fccb = ch->frozen; 1354 ch->frozen = NULL; 1355 fsl_sata_begin_transaction(ch, fccb); 1356 xpt_release_simq(ch->sim, TRUE); 1357 } 1358 /* Start PM timer. */ 1359 if (ch->numrslots == 0 && ch->pm_level > 3 && 1360 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1361 callout_schedule(&ch->pm_timer, 1362 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1363 } 1364 } 1365 1366 static void 1367 fsl_sata_issue_recovery(struct fsl_sata_channel *ch) 1368 { 1369 union ccb *ccb; 1370 struct ccb_ataio *ataio; 1371 struct ccb_scsiio *csio; 1372 int i; 1373 1374 /* Find some held command. */ 1375 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1376 if (ch->hold[i]) 1377 break; 1378 } 1379 ccb = xpt_alloc_ccb_nowait(); 1380 if (ccb == NULL) { 1381 device_printf(ch->dev, "Unable to allocate recovery command\n"); 1382 completeall: 1383 /* We can't do anything -- complete held commands. */ 1384 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1385 if (ch->hold[i] == NULL) 1386 continue; 1387 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1388 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1389 fsl_sata_done(ch, ch->hold[i]); 1390 ch->hold[i] = NULL; 1391 ch->numhslots--; 1392 } 1393 fsl_sata_reset(ch); 1394 return; 1395 } 1396 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1397 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1398 /* READ LOG */ 1399 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1400 ccb->ccb_h.func_code = XPT_ATA_IO; 1401 ccb->ccb_h.flags = CAM_DIR_IN; 1402 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1403 ataio = &ccb->ataio; 1404 ataio->data_ptr = malloc(512, M_FSL_SATA, M_NOWAIT); 1405 if (ataio->data_ptr == NULL) { 1406 xpt_free_ccb(ccb); 1407 device_printf(ch->dev, 1408 "Unable to allocate memory for READ LOG command\n"); 1409 goto completeall; 1410 } 1411 ataio->dxfer_len = 512; 1412 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1413 ataio->cmd.flags = CAM_ATAIO_48BIT; 1414 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1415 ataio->cmd.sector_count = 1; 1416 ataio->cmd.sector_count_exp = 0; 1417 ataio->cmd.lba_low = 0x10; 1418 ataio->cmd.lba_mid = 0; 1419 ataio->cmd.lba_mid_exp = 0; 1420 } else { 1421 /* REQUEST SENSE */ 1422 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 1423 ccb->ccb_h.recovery_slot = i; 1424 ccb->ccb_h.func_code = XPT_SCSI_IO; 1425 ccb->ccb_h.flags = CAM_DIR_IN; 1426 ccb->ccb_h.status = 0; 1427 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1428 csio = &ccb->csio; 1429 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 1430 csio->dxfer_len = ch->hold[i]->csio.sense_len; 1431 csio->cdb_len = 6; 1432 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 1433 csio->cdb_io.cdb_bytes[0] = 0x03; 1434 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 1435 } 1436 /* Freeze SIM while doing recovery. */ 1437 ch->recoverycmd = 1; 1438 xpt_freeze_simq(ch->sim, 1); 1439 fsl_sata_begin_transaction(ch, ccb); 1440 } 1441 1442 static void 1443 fsl_sata_process_read_log(struct fsl_sata_channel *ch, union ccb *ccb) 1444 { 1445 uint8_t *data; 1446 struct ata_res *res; 1447 int i; 1448 1449 ch->recoverycmd = 0; 1450 1451 data = ccb->ataio.data_ptr; 1452 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1453 (data[0] & 0x80) == 0) { 1454 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1455 if (!ch->hold[i]) 1456 continue; 1457 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 1458 continue; 1459 if ((data[0] & 0x1F) == i) { 1460 res = &ch->hold[i]->ataio.res; 1461 res->status = data[2]; 1462 res->error = data[3]; 1463 res->lba_low = data[4]; 1464 res->lba_mid = data[5]; 1465 res->lba_high = data[6]; 1466 res->device = data[7]; 1467 res->lba_low_exp = data[8]; 1468 res->lba_mid_exp = data[9]; 1469 res->lba_high_exp = data[10]; 1470 res->sector_count = data[12]; 1471 res->sector_count_exp = data[13]; 1472 } else { 1473 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1474 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1475 } 1476 fsl_sata_done(ch, ch->hold[i]); 1477 ch->hold[i] = NULL; 1478 ch->numhslots--; 1479 } 1480 } else { 1481 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1482 device_printf(ch->dev, "Error while READ LOG EXT\n"); 1483 else if ((data[0] & 0x80) == 0) { 1484 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 1485 } 1486 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1487 if (!ch->hold[i]) 1488 continue; 1489 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 1490 continue; 1491 fsl_sata_done(ch, ch->hold[i]); 1492 ch->hold[i] = NULL; 1493 ch->numhslots--; 1494 } 1495 } 1496 free(ccb->ataio.data_ptr, M_FSL_SATA); 1497 xpt_free_ccb(ccb); 1498 xpt_release_simq(ch->sim, TRUE); 1499 } 1500 1501 static void 1502 fsl_sata_process_request_sense(struct fsl_sata_channel *ch, union ccb *ccb) 1503 { 1504 int i; 1505 1506 ch->recoverycmd = 0; 1507 1508 i = ccb->ccb_h.recovery_slot; 1509 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 1510 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 1511 } else { 1512 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1513 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 1514 } 1515 fsl_sata_done(ch, ch->hold[i]); 1516 ch->hold[i] = NULL; 1517 ch->numhslots--; 1518 xpt_free_ccb(ccb); 1519 xpt_release_simq(ch->sim, TRUE); 1520 } 1521 1522 static void 1523 fsl_sata_start(struct fsl_sata_channel *ch) 1524 { 1525 u_int32_t cmd; 1526 1527 /* Clear SATA error register */ 1528 ATA_OUTL(ch->r_mem, FSL_SATA_P_SERR, 0xFFFFFFFF); 1529 /* Clear any interrupts pending on this channel */ 1530 ATA_OUTL(ch->r_mem, FSL_SATA_P_HSTS, 0x3F); 1531 ATA_OUTL(ch->r_mem, FSL_SATA_P_CER, 0xFFFF); 1532 ATA_OUTL(ch->r_mem, FSL_SATA_P_DER, 0xFFFF); 1533 /* Start operations on this channel */ 1534 cmd = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 1535 cmd |= FSL_SATA_P_HCTRL_HC_ON | FSL_SATA_P_HCTRL_SNOOP; 1536 cmd &= ~FSL_SATA_P_HCTRL_HC_FORCE_OFF; 1537 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, cmd | 1538 (ch->pm_present ? FSL_SATA_P_HCTRL_PM : 0)); 1539 fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 1540 FSL_SATA_P_HSTS_PR, FSL_SATA_P_HSTS_PR, 500); 1541 ATA_OUTL(ch->r_mem, FSL_SATA_P_HSTS, 1542 ATA_INL(ch->r_mem, FSL_SATA_P_HSTS) & FSL_SATA_P_HSTS_PR); 1543 } 1544 1545 static void 1546 fsl_sata_stop(struct fsl_sata_channel *ch) 1547 { 1548 uint32_t cmd; 1549 int i; 1550 1551 /* Kill all activity on this channel */ 1552 cmd = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL); 1553 cmd &= ~FSL_SATA_P_HCTRL_HC_ON; 1554 1555 for (i = 0; i < 2; i++) { 1556 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, cmd); 1557 if (fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 1558 FSL_SATA_P_HSTS_HS_ON, 0, 500)) { 1559 if (i != 0) 1560 device_printf(ch->dev, 1561 "stopping FSL SATA engine failed\n"); 1562 cmd |= FSL_SATA_P_HCTRL_HC_FORCE_OFF; 1563 } else 1564 break; 1565 } 1566 ch->eslots = 0; 1567 } 1568 1569 static void 1570 fsl_sata_reset(struct fsl_sata_channel *ch) 1571 { 1572 uint32_t ctrl; 1573 int i; 1574 1575 xpt_freeze_simq(ch->sim, 1); 1576 if (bootverbose) 1577 device_printf(ch->dev, "FSL SATA reset...\n"); 1578 1579 /* Requeue freezed command. */ 1580 if (ch->frozen) { 1581 union ccb *fccb = ch->frozen; 1582 ch->frozen = NULL; 1583 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1584 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1585 xpt_freeze_devq(fccb->ccb_h.path, 1); 1586 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1587 } 1588 fsl_sata_done(ch, fccb); 1589 } 1590 /* Kill the engine and requeue all running commands. */ 1591 fsl_sata_stop(ch); 1592 DELAY(1000); /* sleep for 1ms */ 1593 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1594 /* Do we have a running request on slot? */ 1595 if (ch->slot[i].state < FSL_SATA_SLOT_RUNNING) 1596 continue; 1597 /* XXX; Commands in loading state. */ 1598 fsl_sata_end_transaction(&ch->slot[i], FSL_SATA_ERR_INNOCENT); 1599 } 1600 for (i = 0; i < FSL_SATA_MAX_SLOTS; i++) { 1601 if (!ch->hold[i]) 1602 continue; 1603 fsl_sata_done(ch, ch->hold[i]); 1604 ch->hold[i] = NULL; 1605 ch->numhslots--; 1606 } 1607 if (ch->toslots != 0) 1608 xpt_release_simq(ch->sim, TRUE); 1609 ch->eslots = 0; 1610 ch->toslots = 0; 1611 ch->fatalerr = 0; 1612 /* Tell the XPT about the event */ 1613 xpt_async(AC_BUS_RESET, ch->path, NULL); 1614 /* Disable port interrupts */ 1615 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, 1616 ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f); 1617 /* Reset and reconnect PHY, */ 1618 fsl_sata_start(ch); 1619 if (fsl_sata_wait_register(ch, FSL_SATA_P_HSTS, 0x08, 0x08, 500)) { 1620 if (bootverbose) 1621 device_printf(ch->dev, 1622 "FSL SATA reset: device not found\n"); 1623 ch->devices = 0; 1624 /* Enable wanted port interrupts */ 1625 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, 1626 ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) | FSL_SATA_P_HCTRL_PHYRDY); 1627 xpt_release_simq(ch->sim, TRUE); 1628 return; 1629 } 1630 if (bootverbose) 1631 device_printf(ch->dev, "FSL SATA reset: device found\n"); 1632 ch->devices = 1; 1633 /* Enable wanted port interrupts */ 1634 ctrl = ATA_INL(ch->r_mem, FSL_SATA_P_HCTRL) & ~0x3f; 1635 ATA_OUTL(ch->r_mem, FSL_SATA_P_HCTRL, 1636 ctrl | FSL_SATA_P_HCTRL_FATAL | FSL_SATA_P_HCTRL_PHYRDY | 1637 FSL_SATA_P_HCTRL_SIG | FSL_SATA_P_HCTRL_SNTFY | 1638 FSL_SATA_P_HCTRL_DE | FSL_SATA_P_HCTRL_CC); 1639 xpt_release_simq(ch->sim, TRUE); 1640 } 1641 1642 static int 1643 fsl_sata_setup_fis(struct fsl_sata_channel *ch, struct fsl_sata_cmd_tab *ctp, union ccb *ccb, int tag) 1644 { 1645 uint8_t *fis = &ctp->cfis[0]; 1646 1647 bzero(fis, 32); 1648 fis[0] = 0x27; /* host to device */ 1649 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1650 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1651 fis[1] |= 0x80; 1652 fis[2] = ATA_PACKET_CMD; 1653 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1654 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 1655 fis[3] = ATA_F_DMA; 1656 else { 1657 fis[5] = ccb->csio.dxfer_len; 1658 fis[6] = ccb->csio.dxfer_len >> 8; 1659 } 1660 fis[7] = ATA_D_LBA; 1661 fis[15] = ATA_A_4BIT; 1662 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1663 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1664 ctp->acmd, ccb->csio.cdb_len); 1665 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 1666 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1667 fis[1] |= 0x80; 1668 fis[2] = ccb->ataio.cmd.command; 1669 fis[3] = ccb->ataio.cmd.features; 1670 fis[4] = ccb->ataio.cmd.lba_low; 1671 fis[5] = ccb->ataio.cmd.lba_mid; 1672 fis[6] = ccb->ataio.cmd.lba_high; 1673 fis[7] = ccb->ataio.cmd.device; 1674 fis[8] = ccb->ataio.cmd.lba_low_exp; 1675 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1676 fis[10] = ccb->ataio.cmd.lba_high_exp; 1677 fis[11] = ccb->ataio.cmd.features_exp; 1678 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1679 fis[12] = tag << 3; 1680 fis[13] = 0; 1681 } else { 1682 fis[12] = ccb->ataio.cmd.sector_count; 1683 fis[13] = ccb->ataio.cmd.sector_count_exp; 1684 } 1685 fis[15] = ATA_A_4BIT; 1686 } else { 1687 fis[15] = ccb->ataio.cmd.control; 1688 } 1689 return (20); 1690 } 1691 1692 static int 1693 fsl_sata_check_ids(struct fsl_sata_channel *ch, union ccb *ccb) 1694 { 1695 1696 if (ccb->ccb_h.target_id > 15) { 1697 ccb->ccb_h.status = CAM_TID_INVALID; 1698 fsl_sata_done(ch, ccb); 1699 return (-1); 1700 } 1701 if (ccb->ccb_h.target_lun != 0) { 1702 ccb->ccb_h.status = CAM_LUN_INVALID; 1703 fsl_sata_done(ch, ccb); 1704 return (-1); 1705 } 1706 return (0); 1707 } 1708 1709 static void 1710 fsl_sataaction(struct cam_sim *sim, union ccb *ccb) 1711 { 1712 struct fsl_sata_channel *ch; 1713 1714 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 1715 ("fsl_sataaction func_code=0x%x\n", ccb->ccb_h.func_code)); 1716 1717 ch = (struct fsl_sata_channel *)cam_sim_softc(sim); 1718 switch (ccb->ccb_h.func_code) { 1719 /* Common cases first */ 1720 case XPT_ATA_IO: /* Execute the requested I/O operation */ 1721 case XPT_SCSI_IO: 1722 if (fsl_sata_check_ids(ch, ccb)) 1723 return; 1724 if (ch->devices == 0 || 1725 (ch->pm_present == 0 && 1726 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 1727 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1728 break; 1729 } 1730 ccb->ccb_h.recovery_type = RECOVERY_NONE; 1731 /* Check for command collision. */ 1732 if (fsl_sata_check_collision(ch, ccb)) { 1733 /* Freeze command. */ 1734 ch->frozen = ccb; 1735 /* We have only one frozen slot, so freeze simq also. */ 1736 xpt_freeze_simq(ch->sim, 1); 1737 return; 1738 } 1739 fsl_sata_begin_transaction(ch, ccb); 1740 return; 1741 case XPT_ABORT: /* Abort the specified CCB */ 1742 /* XXX Implement */ 1743 ccb->ccb_h.status = CAM_REQ_INVALID; 1744 break; 1745 case XPT_SET_TRAN_SETTINGS: 1746 { 1747 struct ccb_trans_settings *cts = &ccb->cts; 1748 struct fsl_sata_device *d; 1749 1750 if (fsl_sata_check_ids(ch, ccb)) 1751 return; 1752 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1753 d = &ch->curr[ccb->ccb_h.target_id]; 1754 else 1755 d = &ch->user[ccb->ccb_h.target_id]; 1756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 1757 d->revision = cts->xport_specific.sata.revision; 1758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 1759 d->mode = cts->xport_specific.sata.mode; 1760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 1761 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 1762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 1763 d->tags = min(FSL_SATA_MAX_SLOTS, cts->xport_specific.sata.tags); 1764 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 1765 ch->pm_present = cts->xport_specific.sata.pm_present; 1766 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 1767 d->atapi = cts->xport_specific.sata.atapi; 1768 ccb->ccb_h.status = CAM_REQ_CMP; 1769 break; 1770 } 1771 case XPT_GET_TRAN_SETTINGS: 1772 /* Get default/user set transfer settings for the target */ 1773 { 1774 struct ccb_trans_settings *cts = &ccb->cts; 1775 struct fsl_sata_device *d; 1776 uint32_t status; 1777 1778 if (fsl_sata_check_ids(ch, ccb)) 1779 return; 1780 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1781 d = &ch->curr[ccb->ccb_h.target_id]; 1782 else 1783 d = &ch->user[ccb->ccb_h.target_id]; 1784 cts->protocol = PROTO_UNSPECIFIED; 1785 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 1786 cts->transport = XPORT_SATA; 1787 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 1788 cts->proto_specific.valid = 0; 1789 cts->xport_specific.sata.valid = 0; 1790 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 1791 (ccb->ccb_h.target_id == 15 || 1792 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 1793 status = ATA_INL(ch->r_mem, FSL_SATA_P_SSTS) & ATA_SS_SPD_MASK; 1794 if (status & 0x0f0) { 1795 cts->xport_specific.sata.revision = 1796 (status & 0x0f0) >> 4; 1797 cts->xport_specific.sata.valid |= 1798 CTS_SATA_VALID_REVISION; 1799 } 1800 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 1801 if (ch->pm_level) { 1802 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 1803 } 1804 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 1805 cts->xport_specific.sata.caps &= 1806 ch->user[ccb->ccb_h.target_id].caps; 1807 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1808 } else { 1809 cts->xport_specific.sata.revision = d->revision; 1810 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 1811 cts->xport_specific.sata.caps = d->caps; 1812 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 1813 } 1814 cts->xport_specific.sata.mode = d->mode; 1815 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 1816 cts->xport_specific.sata.bytecount = d->bytecount; 1817 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 1818 cts->xport_specific.sata.pm_present = ch->pm_present; 1819 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 1820 cts->xport_specific.sata.tags = d->tags; 1821 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 1822 cts->xport_specific.sata.atapi = d->atapi; 1823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 1824 ccb->ccb_h.status = CAM_REQ_CMP; 1825 break; 1826 } 1827 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1828 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1829 fsl_sata_reset(ch); 1830 ccb->ccb_h.status = CAM_REQ_CMP; 1831 break; 1832 case XPT_TERM_IO: /* Terminate the I/O process */ 1833 /* XXX Implement */ 1834 ccb->ccb_h.status = CAM_REQ_INVALID; 1835 break; 1836 case XPT_PATH_INQ: /* Path routing inquiry */ 1837 { 1838 struct ccb_pathinq *cpi = &ccb->cpi; 1839 1840 cpi->version_num = 1; /* XXX??? */ 1841 cpi->hba_inquiry = PI_SDTR_ABLE; 1842 cpi->hba_inquiry |= PI_TAG_ABLE; 1843 #if 0 1844 /* 1845 * XXX: CAM tries to reset port 15 if it sees port multiplier 1846 * support. Disable it for now. 1847 */ 1848 cpi->hba_inquiry |= PI_SATAPM; 1849 #endif 1850 cpi->target_sprt = 0; 1851 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 1852 cpi->hba_eng_cnt = 0; 1853 /* 1854 * XXX: This should be 15, since hardware *does* support a port 1855 * multiplier. See above. 1856 */ 1857 cpi->max_target = 0; 1858 cpi->max_lun = 0; 1859 cpi->initiator_id = 0; 1860 cpi->bus_id = cam_sim_bus(sim); 1861 cpi->base_transfer_speed = 150000; 1862 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1863 strncpy(cpi->hba_vid, "FSL SATA", HBA_IDLEN); 1864 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1865 cpi->unit_number = cam_sim_unit(sim); 1866 cpi->transport = XPORT_SATA; 1867 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 1868 cpi->protocol = PROTO_ATA; 1869 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 1870 cpi->maxio = (FSL_SATA_SG_ENTRIES - 1) * PAGE_SIZE; 1871 cpi->ccb_h.status = CAM_REQ_CMP; 1872 break; 1873 } 1874 default: 1875 ccb->ccb_h.status = CAM_REQ_INVALID; 1876 break; 1877 } 1878 fsl_sata_done(ch, ccb); 1879 } 1880 1881 static void 1882 fsl_satapoll(struct cam_sim *sim) 1883 { 1884 struct fsl_sata_channel *ch = (struct fsl_sata_channel *)cam_sim_softc(sim); 1885 uint32_t istatus; 1886 1887 /* Read interrupt statuses and process if any. */ 1888 istatus = ATA_INL(ch->r_mem, FSL_SATA_P_HSTS); 1889 if (istatus != 0) 1890 fsl_sata_intr_main(ch, istatus); 1891 } 1892 MODULE_VERSION(fsl_sata, 1); 1893 MODULE_DEPEND(fsl_sata, cam, 1, 1, 1); 1894