1 /*- 2 * Copyright (c) 2016 Justin Hibbits 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/malloc.h> 37 #include <sys/rman.h> 38 #include <sys/timeet.h> 39 #include <sys/timetc.h> 40 #include <sys/watchdog.h> 41 #include <sys/fbio.h> 42 #include <sys/consio.h> 43 #include <sys/eventhandler.h> 44 #include <sys/gpio.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <dev/videomode/videomode.h> 55 #include <dev/videomode/edidvar.h> 56 57 #include <dev/vt/vt.h> 58 #include <dev/vt/colors/vt_termcolors.h> 59 60 #include <powerpc/mpc85xx/mpc85xx.h> 61 62 #include "gpio_if.h" 63 64 #include <machine/bus.h> 65 #include <machine/cpu.h> 66 67 #include "fb_if.h" 68 69 #define DIU_DESC_1 0x000 /* Plane1 Area Descriptor Pointer Register */ 70 #define DIU_DESC_2 0x004 /* Plane2 Area Descriptor Pointer Register */ 71 #define DIU_DESC_3 0x008 /* Plane3 Area Descriptor Pointer Register */ 72 #define DIU_GAMMA 0x00C /* Gamma Register */ 73 #define DIU_PALETTE 0x010 /* Palette Register */ 74 #define DIU_CURSOR 0x014 /* Cursor Register */ 75 #define DIU_CURS_POS 0x018 /* Cursor Position Register */ 76 #define CURSOR_Y_SHIFT 16 77 #define CURSOR_X_SHIFT 0 78 #define DIU_DIU_MODE 0x01C /* DIU4 Mode */ 79 #define DIU_MODE_M 0x7 80 #define DIU_MODE_S 0 81 #define DIU_MODE_NORMAL 0x1 82 #define DIU_MODE_2 0x2 83 #define DIU_MODE_3 0x3 84 #define DIU_MODE_COLBAR 0x4 85 #define DIU_BGND 0x020 /* Background */ 86 #define DIU_BGND_WB 0x024 /* Background Color in write back Mode Register */ 87 #define DIU_DISP_SIZE 0x028 /* Display Size */ 88 #define DELTA_Y_S 16 89 #define DELTA_X_S 0 90 #define DIU_WB_SIZE 0x02C /* Write back Plane Size Register */ 91 #define DELTA_Y_WB_S 16 92 #define DELTA_X_WB_S 0 93 #define DIU_WB_MEM_ADDR 0x030 /* Address to Store the write back Plane Register */ 94 #define DIU_HSYN_PARA 0x034 /* Horizontal Sync Parameter */ 95 #define BP_H_SHIFT 22 96 #define PW_H_SHIFT 11 97 #define FP_H_SHIFT 0 98 #define DIU_VSYN_PARA 0x038 /* Vertical Sync Parameter */ 99 #define BP_V_SHIFT 22 100 #define PW_V_SHIFT 11 101 #define FP_V_SHIFT 0 102 #define DIU_SYNPOL 0x03C /* Synchronize Polarity */ 103 #define BP_VS (1 << 4) 104 #define BP_HS (1 << 3) 105 #define INV_CS (1 << 2) 106 #define INV_VS (1 << 1) 107 #define INV_HS (1 << 0) 108 #define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ 109 #define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ 110 #define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ 111 #define DIU_THRESHOLD 0x040 /* Threshold */ 112 #define LS_BF_VS_SHIFT 16 113 #define OUT_BUF_LOW_SHIFT 0 114 #define DIU_INT_STATUS 0x044 /* Interrupt Status */ 115 #define DIU_INT_MASK 0x048 /* Interrupt Mask */ 116 #define DIU_COLBAR_1 0x04C /* COLBAR_1 */ 117 #define DIU_COLORBARn_R(x) ((x & 0xff) << 16) 118 #define DIU_COLORBARn_G(x) ((x & 0xff) << 8) 119 #define DIU_COLORBARn_B(x) ((x & 0xff) << 0) 120 #define DIU_COLBAR_2 0x050 /* COLBAR_2 */ 121 #define DIU_COLBAR_3 0x054 /* COLBAR_3 */ 122 #define DIU_COLBAR_4 0x058 /* COLBAR_4 */ 123 #define DIU_COLBAR_5 0x05c /* COLBAR_5 */ 124 #define DIU_COLBAR_6 0x060 /* COLBAR_6 */ 125 #define DIU_COLBAR_7 0x064 /* COLBAR_7 */ 126 #define DIU_COLBAR_8 0x068 /* COLBAR_8 */ 127 #define DIU_FILLING 0x06C /* Filling Register */ 128 #define DIU_PLUT 0x070 /* Priority Look Up Table Register */ 129 130 /* Control Descriptor */ 131 #define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 132 #define DIU_CTRLDESCLn_1(n) DIU_CTRLDESCL(n, 1) 133 #define DIU_CTRLDESCLn_2(n) DIU_CTRLDESCL(n, 2) 134 #define DIU_CTRLDESCLn_3(n) DIU_CTRLDESCL(n, 3) 135 #define TRANS_SHIFT 20 136 #define DIU_CTRLDESCLn_4(n) DIU_CTRLDESCL(n, 4) 137 #define BPP_MASK 0xf /* Bit per pixel Mask */ 138 #define BPP_SHIFT 16 /* Bit per pixel Shift */ 139 #define BPP24 0x5 140 #define EN_LAYER (1 << 31) /* Enable the layer */ 141 #define DIU_CTRLDESCLn_5(n) DIU_CTRLDESCL(n, 5) 142 #define DIU_CTRLDESCLn_6(n) DIU_CTRLDESCL(n, 6) 143 #define DIU_CTRLDESCLn_7(n) DIU_CTRLDESCL(n, 7) 144 #define DIU_CTRLDESCLn_8(n) DIU_CTRLDESCL(n, 8) 145 #define DIU_CTRLDESCLn_9(n) DIU_CTRLDESCL(n, 9) 146 147 #define NUM_LAYERS 1 148 149 struct panel_info { 150 uint32_t panel_width; 151 uint32_t panel_height; 152 uint32_t panel_hbp; 153 uint32_t panel_hpw; 154 uint32_t panel_hfp; 155 uint32_t panel_vbp; 156 uint32_t panel_vpw; 157 uint32_t panel_vfp; 158 uint32_t panel_freq; 159 uint32_t clk_div; 160 }; 161 162 struct diu_area_descriptor { 163 uint32_t pixel_format; 164 uint32_t bitmap_address; 165 uint32_t source_size; 166 uint32_t aoi_size; 167 uint32_t aoi_offset; 168 uint32_t display_offset; 169 uint32_t chroma_key_max; 170 uint32_t chroma_key_min; 171 uint32_t next_ad_addr; 172 } __aligned(32); 173 174 struct diu_softc { 175 struct resource *res[2]; 176 void *ih; 177 device_t sc_dev; 178 device_t sc_fbd; /* fbd child */ 179 struct fb_info sc_info; 180 struct panel_info sc_panel; 181 struct diu_area_descriptor *sc_planes[3]; 182 uint8_t *sc_gamma; 183 uint8_t *sc_cursor; 184 }; 185 186 static struct resource_spec diu_spec[] = { 187 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 188 { SYS_RES_IRQ, 0, RF_ACTIVE }, 189 { -1, 0 } 190 }; 191 192 static int 193 diu_probe(device_t dev) 194 { 195 196 if (!ofw_bus_status_okay(dev)) 197 return (ENXIO); 198 199 if (!ofw_bus_is_compatible(dev, "fsl,diu")) 200 return (ENXIO); 201 202 device_set_desc(dev, "Freescale Display Interface Unit"); 203 return (BUS_PROBE_DEFAULT); 204 } 205 206 static void 207 diu_intr(void *arg) 208 { 209 struct diu_softc *sc; 210 int reg; 211 212 sc = arg; 213 214 /* Ack interrupts */ 215 reg = bus_read_4(sc->res[0], DIU_INT_STATUS); 216 bus_write_4(sc->res[0], DIU_INT_STATUS, reg); 217 218 /* TODO interrupt handler */ 219 } 220 221 static int 222 diu_set_pxclk(device_t dev, unsigned int freq) 223 { 224 phandle_t node; 225 unsigned long bus_freq; 226 uint32_t pxclk_set; 227 uint32_t clkdvd; 228 229 node = ofw_bus_get_node(device_get_parent(dev)); 230 if ((bus_freq = mpc85xx_get_platform_clock()) <= 0) { 231 device_printf(dev, "Unable to get bus frequency\n"); 232 return (ENXIO); 233 } 234 235 /* freq is in kHz */ 236 freq *= 1000; 237 /* adding freq/2 to round-to-closest */ 238 pxclk_set = min(max((bus_freq + freq/2) / freq, 2), 255) << 16; 239 pxclk_set |= OCP85XX_CLKDVDR_PXCKEN; 240 clkdvd = ccsr_read4(OCP85XX_CLKDVDR); 241 clkdvd &= ~(OCP85XX_CLKDVDR_PXCKEN | OCP85XX_CLKDVDR_PXCKINV | 242 OCP85XX_CLKDVDR_PXCLK_MASK); 243 ccsr_write4(OCP85XX_CLKDVDR, clkdvd); 244 ccsr_write4(OCP85XX_CLKDVDR, clkdvd | pxclk_set); 245 246 return (0); 247 } 248 249 static int 250 diu_init(struct diu_softc *sc) 251 { 252 struct panel_info *panel; 253 int reg; 254 255 panel = &sc->sc_panel; 256 257 /* Temporarily disable the DIU while configuring */ 258 reg = bus_read_4(sc->res[0], DIU_DIU_MODE); 259 reg &= ~(DIU_MODE_M << DIU_MODE_S); 260 bus_write_4(sc->res[0], DIU_DIU_MODE, reg); 261 262 if (diu_set_pxclk(sc->sc_dev, panel->panel_freq) < 0) { 263 return (ENXIO); 264 } 265 266 /* Configure DIU */ 267 /* Need to set these somehow later... */ 268 bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma)); 269 bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor)); 270 bus_write_4(sc->res[0], DIU_CURS_POS, 0); 271 272 reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 273 reg |= sc->sc_info.fb_width; 274 bus_write_4(sc->res[0], DIU_DISP_SIZE, reg); 275 276 reg = (panel->panel_hbp << BP_H_SHIFT); 277 reg |= (panel->panel_hpw << PW_H_SHIFT); 278 reg |= (panel->panel_hfp << FP_H_SHIFT); 279 bus_write_4(sc->res[0], DIU_HSYN_PARA, reg); 280 281 reg = (panel->panel_vbp << BP_V_SHIFT); 282 reg |= (panel->panel_vpw << PW_V_SHIFT); 283 reg |= (panel->panel_vfp << FP_V_SHIFT); 284 bus_write_4(sc->res[0], DIU_VSYN_PARA, reg); 285 286 bus_write_4(sc->res[0], DIU_BGND, 0); 287 288 /* Mask all the interrupts */ 289 bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f); 290 291 /* Reset all layers */ 292 sc->sc_planes[0] = contigmalloc(sizeof(struct diu_area_descriptor), 293 M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, 32, 0); 294 bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0])); 295 bus_write_4(sc->res[0], DIU_DESC_2, 0); 296 bus_write_4(sc->res[0], DIU_DESC_3, 0); 297 298 /* Setup first plane */ 299 /* Area descriptor fields are little endian, so byte swap. */ 300 /* Word 0: Pixel format */ 301 /* Set to 8:8:8:8 ARGB, 4 bytes per pixel, no flip. */ 302 #define MAKE_PXLFMT(as,rs,gs,bs,a,r,g,b,f,s) \ 303 htole32((as << (4 * a)) | (rs << 4 * r) | \ 304 (gs << 4 * g) | (bs << 4 * b) | \ 305 (f << 28) | (s << 16) | \ 306 (a << 25) | (r << 19) | \ 307 (g << 21) | (b << 24)) 308 reg = MAKE_PXLFMT(8, 8, 8, 8, 3, 2, 1, 0, 1, 3); 309 sc->sc_planes[0]->pixel_format = reg; 310 /* Word 1: Bitmap address */ 311 sc->sc_planes[0]->bitmap_address = htole32(sc->sc_info.fb_pbase); 312 /* Word 2: Source size/global alpha */ 313 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12)); 314 sc->sc_planes[0]->source_size = htole32(reg); 315 /* Word 3: AOI Size */ 316 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 317 sc->sc_planes[0]->aoi_size = htole32(reg); 318 /* Word 4: AOI Offset */ 319 sc->sc_planes[0]->aoi_offset = 0; 320 /* Word 5: Display offset */ 321 sc->sc_planes[0]->display_offset = 0; 322 /* Word 6: Chroma key max */ 323 sc->sc_planes[0]->chroma_key_max = 0; 324 /* Word 7: Chroma key min */ 325 reg = 255 << 16 | 255 << 8 | 255; 326 sc->sc_planes[0]->chroma_key_min = htole32(reg); 327 /* Word 8: Next AD */ 328 sc->sc_planes[0]->next_ad_addr = 0; 329 330 /* TODO: derive this from the panel size */ 331 bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666); 332 333 /* Enable DIU in normal mode */ 334 reg = bus_read_4(sc->res[0], DIU_DIU_MODE); 335 reg &= ~(DIU_MODE_M << DIU_MODE_S); 336 reg |= (DIU_MODE_NORMAL << DIU_MODE_S); 337 bus_write_4(sc->res[0], DIU_DIU_MODE, reg); 338 339 return (0); 340 } 341 342 static int 343 diu_attach(device_t dev) 344 { 345 struct edid_info edid; 346 struct diu_softc *sc; 347 const struct videomode *videomode; 348 void *edid_cells; 349 const char *vm_name; 350 phandle_t node; 351 int h, r, w; 352 int err, i; 353 354 sc = device_get_softc(dev); 355 sc->sc_dev = dev; 356 357 if (bus_alloc_resources(dev, diu_spec, sc->res)) { 358 device_printf(dev, "could not allocate resources\n"); 359 return (ENXIO); 360 } 361 362 node = ofw_bus_get_node(dev); 363 /* Setup interrupt handler */ 364 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 365 NULL, diu_intr, sc, &sc->ih); 366 if (err) { 367 device_printf(dev, "Unable to alloc interrupt resource.\n"); 368 return (ENXIO); 369 } 370 371 /* TODO: Eventually, allow EDID to be dynamically provided. */ 372 if (OF_getprop_alloc(node, "edid", 1, &edid_cells) <= 0) { 373 /* 374 * u-boot uses the environment variable name 'video-mode', so 375 * just use the same name here. Should allow another variable 376 * that better fits our design model, but this is fine. 377 */ 378 if ((vm_name = kern_getenv("video-mode")) == NULL) { 379 device_printf(dev, 380 "No EDID data and no video-mode env set\n"); 381 return (ENXIO); 382 } 383 } 384 if (edid_cells != NULL) { 385 if (edid_parse(edid_cells, &edid) != 0) { 386 device_printf(dev, "Error parsing EDID\n"); 387 OF_prop_free(edid_cells); 388 return (ENXIO); 389 } 390 videomode = edid.edid_preferred_mode; 391 } else { 392 /* Parse video-mode kenv variable. */ 393 if ((err = sscanf(vm_name, "fslfb:%dx%d@%d", &w, &h, &r)) != 3) { 394 device_printf(dev, 395 "Cannot parse video mode: %s\n", vm_name); 396 return (ENXIO); 397 } 398 videomode = pick_mode_by_ref(w, h, r); 399 if (videomode == NULL) { 400 device_printf(dev, 401 "Cannot find mode for %dx%d@%d", w, h, r); 402 return (ENXIO); 403 } 404 } 405 406 sc->sc_panel.panel_width = videomode->hdisplay; 407 sc->sc_panel.panel_height = videomode->vdisplay; 408 sc->sc_panel.panel_hbp = videomode->hsync_start - videomode->hdisplay; 409 sc->sc_panel.panel_hfp = videomode->htotal - videomode->hsync_end; 410 sc->sc_panel.panel_hpw = videomode->hsync_end - videomode->hsync_start; 411 sc->sc_panel.panel_vbp = videomode->vsync_start - videomode->vdisplay; 412 sc->sc_panel.panel_vfp = videomode->vtotal - videomode->vsync_end; 413 sc->sc_panel.panel_vpw = videomode->vsync_end - videomode->vsync_start; 414 sc->sc_panel.panel_freq = videomode->dot_clock; 415 416 sc->sc_info.fb_width = sc->sc_panel.panel_width; 417 sc->sc_info.fb_height = sc->sc_panel.panel_height; 418 sc->sc_info.fb_stride = sc->sc_info.fb_width * 4; 419 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 32; 420 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 421 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 422 M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); 423 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 424 425 /* Gamma table is 3 consecutive segments of 256 bytes. */ 426 sc->sc_gamma = contigmalloc(3 * 256, M_DEVBUF, 0, 0, 427 BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); 428 /* Initialize gamma to default */ 429 for (i = 0; i < 3 * 256; i++) 430 sc->sc_gamma[i] = (i % 256); 431 432 /* Cursor format is 32x32x16bpp */ 433 sc->sc_cursor = contigmalloc(32 * 32 * 2, M_DEVBUF, M_ZERO, 0, 434 BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); 435 436 diu_init(sc); 437 438 sc->sc_info.fb_name = device_get_nameunit(dev); 439 440 /* Ask newbus to attach framebuffer device to me. */ 441 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 442 if (sc->sc_fbd == NULL) 443 device_printf(dev, "Can't attach fbd device\n"); 444 445 if ((err = device_probe_and_attach(sc->sc_fbd)) != 0) { 446 device_printf(dev, "Failed to attach fbd device: %d\n", err); 447 } 448 449 return (0); 450 } 451 452 static struct fb_info * 453 diu_fb_getinfo(device_t dev) 454 { 455 struct diu_softc *sc = device_get_softc(dev); 456 457 return (&sc->sc_info); 458 } 459 460 static device_method_t diu_methods[] = { 461 DEVMETHOD(device_probe, diu_probe), 462 DEVMETHOD(device_attach, diu_attach), 463 464 /* Framebuffer service methods */ 465 DEVMETHOD(fb_getinfo, diu_fb_getinfo), 466 { 0, 0 } 467 }; 468 469 static driver_t diu_driver = { 470 "fb", 471 diu_methods, 472 sizeof(struct diu_softc), 473 }; 474 475 static devclass_t diu_devclass; 476 477 DRIVER_MODULE(fb, simplebus, diu_driver, diu_devclass, 0, 0); 478