1 /*- 2 * Copyright (c) 2016 Justin Hibbits 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/endian.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/malloc.h> 35 #include <sys/rman.h> 36 #include <sys/fbio.h> 37 #include <sys/consio.h> 38 39 #include <vm/vm.h> 40 #include <vm/pmap.h> 41 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/videomode/videomode.h> 48 #include <dev/videomode/edidvar.h> 49 50 #include <dev/vt/vt.h> 51 #include <dev/vt/colors/vt_termcolors.h> 52 53 #include <powerpc/mpc85xx/mpc85xx.h> 54 55 #include <machine/bus.h> 56 #include <machine/cpu.h> 57 58 #include "fb_if.h" 59 60 #define DIU_DESC_1 0x000 /* Plane1 Area Descriptor Pointer Register */ 61 #define DIU_DESC_2 0x004 /* Plane2 Area Descriptor Pointer Register */ 62 #define DIU_DESC_3 0x008 /* Plane3 Area Descriptor Pointer Register */ 63 #define DIU_GAMMA 0x00C /* Gamma Register */ 64 #define DIU_PALETTE 0x010 /* Palette Register */ 65 #define DIU_CURSOR 0x014 /* Cursor Register */ 66 #define DIU_CURS_POS 0x018 /* Cursor Position Register */ 67 #define CURSOR_Y_SHIFT 16 68 #define CURSOR_X_SHIFT 0 69 #define DIU_DIU_MODE 0x01C /* DIU4 Mode */ 70 #define DIU_MODE_M 0x7 71 #define DIU_MODE_S 0 72 #define DIU_MODE_NORMAL 0x1 73 #define DIU_MODE_2 0x2 74 #define DIU_MODE_3 0x3 75 #define DIU_MODE_COLBAR 0x4 76 #define DIU_BGND 0x020 /* Background */ 77 #define DIU_BGND_WB 0x024 /* Background Color in write back Mode Register */ 78 #define DIU_DISP_SIZE 0x028 /* Display Size */ 79 #define DELTA_Y_S 16 80 #define DELTA_X_S 0 81 #define DIU_WB_SIZE 0x02C /* Write back Plane Size Register */ 82 #define DELTA_Y_WB_S 16 83 #define DELTA_X_WB_S 0 84 #define DIU_WB_MEM_ADDR 0x030 /* Address to Store the write back Plane Register */ 85 #define DIU_HSYN_PARA 0x034 /* Horizontal Sync Parameter */ 86 #define BP_H_SHIFT 22 87 #define PW_H_SHIFT 11 88 #define FP_H_SHIFT 0 89 #define DIU_VSYN_PARA 0x038 /* Vertical Sync Parameter */ 90 #define BP_V_SHIFT 22 91 #define PW_V_SHIFT 11 92 #define FP_V_SHIFT 0 93 #define DIU_SYNPOL 0x03C /* Synchronize Polarity */ 94 #define BP_VS (1 << 4) 95 #define BP_HS (1 << 3) 96 #define INV_CS (1 << 2) 97 #define INV_VS (1 << 1) 98 #define INV_HS (1 << 0) 99 #define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ 100 #define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ 101 #define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ 102 #define DIU_THRESHOLD 0x040 /* Threshold */ 103 #define LS_BF_VS_SHIFT 16 104 #define OUT_BUF_LOW_SHIFT 0 105 #define DIU_INT_STATUS 0x044 /* Interrupt Status */ 106 #define DIU_INT_MASK 0x048 /* Interrupt Mask */ 107 #define DIU_COLBAR_1 0x04C /* COLBAR_1 */ 108 #define DIU_COLORBARn_R(x) ((x & 0xff) << 16) 109 #define DIU_COLORBARn_G(x) ((x & 0xff) << 8) 110 #define DIU_COLORBARn_B(x) ((x & 0xff) << 0) 111 #define DIU_COLBAR_2 0x050 /* COLBAR_2 */ 112 #define DIU_COLBAR_3 0x054 /* COLBAR_3 */ 113 #define DIU_COLBAR_4 0x058 /* COLBAR_4 */ 114 #define DIU_COLBAR_5 0x05c /* COLBAR_5 */ 115 #define DIU_COLBAR_6 0x060 /* COLBAR_6 */ 116 #define DIU_COLBAR_7 0x064 /* COLBAR_7 */ 117 #define DIU_COLBAR_8 0x068 /* COLBAR_8 */ 118 #define DIU_FILLING 0x06C /* Filling Register */ 119 #define DIU_PLUT 0x070 /* Priority Look Up Table Register */ 120 121 /* Control Descriptor */ 122 #define DIU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 123 #define DIU_CTRLDESCLn_1(n) DIU_CTRLDESCL(n, 1) 124 #define DIU_CTRLDESCLn_2(n) DIU_CTRLDESCL(n, 2) 125 #define DIU_CTRLDESCLn_3(n) DIU_CTRLDESCL(n, 3) 126 #define TRANS_SHIFT 20 127 #define DIU_CTRLDESCLn_4(n) DIU_CTRLDESCL(n, 4) 128 #define BPP_MASK 0xf /* Bit per pixel Mask */ 129 #define BPP_SHIFT 16 /* Bit per pixel Shift */ 130 #define BPP24 0x5 131 #define EN_LAYER (1 << 31) /* Enable the layer */ 132 #define DIU_CTRLDESCLn_5(n) DIU_CTRLDESCL(n, 5) 133 #define DIU_CTRLDESCLn_6(n) DIU_CTRLDESCL(n, 6) 134 #define DIU_CTRLDESCLn_7(n) DIU_CTRLDESCL(n, 7) 135 #define DIU_CTRLDESCLn_8(n) DIU_CTRLDESCL(n, 8) 136 #define DIU_CTRLDESCLn_9(n) DIU_CTRLDESCL(n, 9) 137 138 #define NUM_LAYERS 1 139 140 struct panel_info { 141 uint32_t panel_width; 142 uint32_t panel_height; 143 uint32_t panel_hbp; 144 uint32_t panel_hpw; 145 uint32_t panel_hfp; 146 uint32_t panel_vbp; 147 uint32_t panel_vpw; 148 uint32_t panel_vfp; 149 uint32_t panel_freq; 150 uint32_t clk_div; 151 }; 152 153 struct diu_area_descriptor { 154 uint32_t pixel_format; 155 uint32_t bitmap_address; 156 uint32_t source_size; 157 uint32_t aoi_size; 158 uint32_t aoi_offset; 159 uint32_t display_offset; 160 uint32_t chroma_key_max; 161 uint32_t chroma_key_min; 162 uint32_t next_ad_addr; 163 } __aligned(32); 164 165 struct diu_softc { 166 struct resource *res[2]; 167 void *ih; 168 device_t sc_dev; 169 device_t sc_fbd; /* fbd child */ 170 struct fb_info sc_info; 171 struct panel_info sc_panel; 172 struct diu_area_descriptor *sc_planes[3]; 173 uint8_t *sc_gamma; 174 uint8_t *sc_cursor; 175 }; 176 177 static struct resource_spec diu_spec[] = { 178 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 179 { SYS_RES_IRQ, 0, RF_ACTIVE }, 180 { -1, 0 } 181 }; 182 183 static int 184 diu_probe(device_t dev) 185 { 186 187 if (!ofw_bus_status_okay(dev)) 188 return (ENXIO); 189 190 if (!ofw_bus_is_compatible(dev, "fsl,diu")) 191 return (ENXIO); 192 193 device_set_desc(dev, "Freescale Display Interface Unit"); 194 return (BUS_PROBE_DEFAULT); 195 } 196 197 static void 198 diu_intr(void *arg) 199 { 200 struct diu_softc *sc; 201 int reg; 202 203 sc = arg; 204 205 /* Ack interrupts */ 206 reg = bus_read_4(sc->res[0], DIU_INT_STATUS); 207 bus_write_4(sc->res[0], DIU_INT_STATUS, reg); 208 209 /* TODO interrupt handler */ 210 } 211 212 static int 213 diu_set_pxclk(device_t dev, unsigned int freq) 214 { 215 unsigned long bus_freq; 216 uint32_t pxclk_set; 217 uint32_t clkdvd; 218 219 if ((bus_freq = mpc85xx_get_platform_clock()) <= 0) { 220 device_printf(dev, "Unable to get bus frequency\n"); 221 return (ENXIO); 222 } 223 224 /* freq is in kHz */ 225 freq *= 1000; 226 /* adding freq/2 to round-to-closest */ 227 pxclk_set = min(max((bus_freq + freq/2) / freq, 2), 255) << 16; 228 pxclk_set |= OCP85XX_CLKDVDR_PXCKEN; 229 clkdvd = ccsr_read4(OCP85XX_CLKDVDR); 230 clkdvd &= ~(OCP85XX_CLKDVDR_PXCKEN | OCP85XX_CLKDVDR_PXCKINV | 231 OCP85XX_CLKDVDR_PXCLK_MASK); 232 ccsr_write4(OCP85XX_CLKDVDR, clkdvd); 233 ccsr_write4(OCP85XX_CLKDVDR, clkdvd | pxclk_set); 234 235 return (0); 236 } 237 238 static int 239 diu_init(struct diu_softc *sc) 240 { 241 struct panel_info *panel; 242 int reg; 243 244 panel = &sc->sc_panel; 245 246 /* Temporarily disable the DIU while configuring */ 247 reg = bus_read_4(sc->res[0], DIU_DIU_MODE); 248 reg &= ~(DIU_MODE_M << DIU_MODE_S); 249 bus_write_4(sc->res[0], DIU_DIU_MODE, reg); 250 251 if (diu_set_pxclk(sc->sc_dev, panel->panel_freq) < 0) { 252 return (ENXIO); 253 } 254 255 /* Configure DIU */ 256 /* Need to set these somehow later... */ 257 bus_write_4(sc->res[0], DIU_GAMMA, vtophys(sc->sc_gamma)); 258 bus_write_4(sc->res[0], DIU_CURSOR, vtophys(sc->sc_cursor)); 259 bus_write_4(sc->res[0], DIU_CURS_POS, 0); 260 261 reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 262 reg |= sc->sc_info.fb_width; 263 bus_write_4(sc->res[0], DIU_DISP_SIZE, reg); 264 265 reg = (panel->panel_hbp << BP_H_SHIFT); 266 reg |= (panel->panel_hpw << PW_H_SHIFT); 267 reg |= (panel->panel_hfp << FP_H_SHIFT); 268 bus_write_4(sc->res[0], DIU_HSYN_PARA, reg); 269 270 reg = (panel->panel_vbp << BP_V_SHIFT); 271 reg |= (panel->panel_vpw << PW_V_SHIFT); 272 reg |= (panel->panel_vfp << FP_V_SHIFT); 273 bus_write_4(sc->res[0], DIU_VSYN_PARA, reg); 274 275 bus_write_4(sc->res[0], DIU_BGND, 0); 276 277 /* Mask all the interrupts */ 278 bus_write_4(sc->res[0], DIU_INT_MASK, 0x3f); 279 280 /* Reset all layers */ 281 sc->sc_planes[0] = contigmalloc(sizeof(struct diu_area_descriptor), 282 M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, 32, 0); 283 bus_write_4(sc->res[0], DIU_DESC_1, vtophys(sc->sc_planes[0])); 284 bus_write_4(sc->res[0], DIU_DESC_2, 0); 285 bus_write_4(sc->res[0], DIU_DESC_3, 0); 286 287 /* Setup first plane */ 288 /* Area descriptor fields are little endian, so byte swap. */ 289 /* Word 0: Pixel format */ 290 /* Set to 8:8:8:8 ARGB, 4 bytes per pixel, no flip. */ 291 #define MAKE_PXLFMT(as,rs,gs,bs,a,r,g,b,f,s) \ 292 htole32((as << (4 * a)) | (rs << 4 * r) | \ 293 (gs << 4 * g) | (bs << 4 * b) | \ 294 (f << 28) | (s << 16) | \ 295 (a << 25) | (r << 19) | \ 296 (g << 21) | (b << 24)) 297 reg = MAKE_PXLFMT(8, 8, 8, 8, 3, 2, 1, 0, 1, 3); 298 sc->sc_planes[0]->pixel_format = reg; 299 /* Word 1: Bitmap address */ 300 sc->sc_planes[0]->bitmap_address = htole32(sc->sc_info.fb_pbase); 301 /* Word 2: Source size/global alpha */ 302 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 12)); 303 sc->sc_planes[0]->source_size = htole32(reg); 304 /* Word 3: AOI Size */ 305 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 306 sc->sc_planes[0]->aoi_size = htole32(reg); 307 /* Word 4: AOI Offset */ 308 sc->sc_planes[0]->aoi_offset = 0; 309 /* Word 5: Display offset */ 310 sc->sc_planes[0]->display_offset = 0; 311 /* Word 6: Chroma key max */ 312 sc->sc_planes[0]->chroma_key_max = 0; 313 /* Word 7: Chroma key min */ 314 reg = 255 << 16 | 255 << 8 | 255; 315 sc->sc_planes[0]->chroma_key_min = htole32(reg); 316 /* Word 8: Next AD */ 317 sc->sc_planes[0]->next_ad_addr = 0; 318 319 /* TODO: derive this from the panel size */ 320 bus_write_4(sc->res[0], DIU_PLUT, 0x1f5f666); 321 322 /* Enable DIU in normal mode */ 323 reg = bus_read_4(sc->res[0], DIU_DIU_MODE); 324 reg &= ~(DIU_MODE_M << DIU_MODE_S); 325 reg |= (DIU_MODE_NORMAL << DIU_MODE_S); 326 bus_write_4(sc->res[0], DIU_DIU_MODE, reg); 327 328 return (0); 329 } 330 331 static int 332 diu_attach(device_t dev) 333 { 334 struct edid_info edid; 335 struct diu_softc *sc; 336 const struct videomode *videomode; 337 void *edid_cells; 338 const char *vm_name; 339 phandle_t node; 340 int h, r, w; 341 int err, i; 342 343 sc = device_get_softc(dev); 344 sc->sc_dev = dev; 345 346 if (bus_alloc_resources(dev, diu_spec, sc->res)) { 347 device_printf(dev, "could not allocate resources\n"); 348 return (ENXIO); 349 } 350 351 node = ofw_bus_get_node(dev); 352 /* Setup interrupt handler */ 353 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 354 NULL, diu_intr, sc, &sc->ih); 355 if (err) { 356 device_printf(dev, "Unable to alloc interrupt resource.\n"); 357 return (ENXIO); 358 } 359 360 /* TODO: Eventually, allow EDID to be dynamically provided. */ 361 if (OF_getprop_alloc(node, "edid", &edid_cells) <= 0) { 362 /* Get a resource hint: hint.fb.N.mode */ 363 if (resource_string_value(device_get_name(dev), 364 device_get_unit(dev), "mode", &vm_name) != 0) { 365 device_printf(dev, 366 "No EDID data and no video-mode env set\n"); 367 return (ENXIO); 368 } 369 } 370 if (edid_cells != NULL) { 371 if (edid_parse(edid_cells, &edid) != 0) { 372 device_printf(dev, "Error parsing EDID\n"); 373 OF_prop_free(edid_cells); 374 return (ENXIO); 375 } 376 videomode = edid.edid_preferred_mode; 377 } else { 378 /* Parse video-mode kenv variable. */ 379 if ((err = sscanf(vm_name, "%dx%d@%d", &w, &h, &r)) != 3) { 380 device_printf(dev, 381 "Cannot parse video mode: %s\n", vm_name); 382 return (ENXIO); 383 } 384 videomode = pick_mode_by_ref(w, h, r); 385 if (videomode == NULL) { 386 device_printf(dev, 387 "Cannot find mode for %dx%d@%d", w, h, r); 388 return (ENXIO); 389 } 390 } 391 392 sc->sc_panel.panel_width = videomode->hdisplay; 393 sc->sc_panel.panel_height = videomode->vdisplay; 394 sc->sc_panel.panel_hbp = videomode->hsync_start - videomode->hdisplay; 395 sc->sc_panel.panel_hfp = videomode->htotal - videomode->hsync_end; 396 sc->sc_panel.panel_hpw = videomode->hsync_end - videomode->hsync_start; 397 sc->sc_panel.panel_vbp = videomode->vsync_start - videomode->vdisplay; 398 sc->sc_panel.panel_vfp = videomode->vtotal - videomode->vsync_end; 399 sc->sc_panel.panel_vpw = videomode->vsync_end - videomode->vsync_start; 400 sc->sc_panel.panel_freq = videomode->dot_clock; 401 402 sc->sc_info.fb_width = sc->sc_panel.panel_width; 403 sc->sc_info.fb_height = sc->sc_panel.panel_height; 404 sc->sc_info.fb_stride = sc->sc_info.fb_width * 4; 405 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 32; 406 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 407 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 408 M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); 409 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 410 sc->sc_info.fb_flags = FB_FLAG_MEMATTR; 411 sc->sc_info.fb_memattr = VM_MEMATTR_DEFAULT; 412 413 /* Gamma table is 3 consecutive segments of 256 bytes. */ 414 sc->sc_gamma = contigmalloc(3 * 256, M_DEVBUF, 0, 0, 415 BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); 416 /* Initialize gamma to default */ 417 for (i = 0; i < 3 * 256; i++) 418 sc->sc_gamma[i] = (i % 256); 419 420 /* Cursor format is 32x32x16bpp */ 421 sc->sc_cursor = contigmalloc(32 * 32 * 2, M_DEVBUF, M_ZERO, 0, 422 BUS_SPACE_MAXADDR_32BIT, PAGE_SIZE, 0); 423 424 diu_init(sc); 425 426 sc->sc_info.fb_name = device_get_nameunit(dev); 427 428 /* Ask newbus to attach framebuffer device to me. */ 429 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 430 if (sc->sc_fbd == NULL) 431 device_printf(dev, "Can't attach fbd device\n"); 432 433 if ((err = device_probe_and_attach(sc->sc_fbd)) != 0) { 434 device_printf(dev, "Failed to attach fbd device: %d\n", err); 435 } 436 437 return (0); 438 } 439 440 static struct fb_info * 441 diu_fb_getinfo(device_t dev) 442 { 443 struct diu_softc *sc = device_get_softc(dev); 444 445 return (&sc->sc_info); 446 } 447 448 static device_method_t diu_methods[] = { 449 DEVMETHOD(device_probe, diu_probe), 450 DEVMETHOD(device_attach, diu_attach), 451 452 /* Framebuffer service methods */ 453 DEVMETHOD(fb_getinfo, diu_fb_getinfo), 454 { 0, 0 } 455 }; 456 457 static driver_t diu_driver = { 458 "fb", 459 diu_methods, 460 sizeof(struct diu_softc), 461 }; 462 463 DRIVER_MODULE(fb, simplebus, diu_driver, 0, 0); 464