xref: /freebsd/sys/powerpc/mpc85xx/atpic.c (revision 7aa383846770374466b1dcb2cefd71bde9acf463)
1 /*-
2  * Copyright (c) 2009 Marcel Moolenaar
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/bus.h>
34 #include <sys/rman.h>
35 #include <sys/bus.h>
36 
37 #include <machine/bus.h>
38 #include <machine/intr_machdep.h>
39 #include <machine/ocpbus.h>
40 #include <machine/pio.h>
41 
42 #include <powerpc/mpc85xx/mpc85xx.h>
43 
44 #include <dev/ic/i8259.h>
45 
46 #include <isa/isareg.h>
47 #include <isa/isavar.h>
48 
49 #include "pic_if.h"
50 
51 #define	ATPIC_MASTER	0
52 #define	ATPIC_SLAVE	1
53 
54 struct atpic_softc {
55 	device_t	sc_dev;
56 
57 	/* I/O port resources for master & slave. */
58 	struct resource	*sc_res[2];
59 	int		sc_rid[2];
60 
61 	/* Our "routing" interrupt */
62 	struct resource *sc_ires;
63 	void		*sc_icookie;
64 	int		sc_irid;
65 
66 	int		sc_vector[16];
67 	uint8_t		sc_mask[2];
68 };
69 
70 static int	atpic_isa_attach(device_t);
71 static void	atpic_isa_identify(driver_t *, device_t);
72 static int	atpic_isa_probe(device_t);
73 
74 static void atpic_config(device_t, u_int, enum intr_trigger,
75     enum intr_polarity);
76 static void atpic_dispatch(device_t, struct trapframe *);
77 static void atpic_enable(device_t, u_int, u_int);
78 static void atpic_eoi(device_t, u_int);
79 static void atpic_ipi(device_t, u_int);
80 static void atpic_mask(device_t, u_int);
81 static void atpic_unmask(device_t, u_int);
82 static uint32_t atpic_id (device_t dev);
83 
84 static device_method_t atpic_isa_methods[] = {
85 	/* Device interface */
86 	DEVMETHOD(device_identify, 	atpic_isa_identify),
87 	DEVMETHOD(device_probe,		atpic_isa_probe),
88 	DEVMETHOD(device_attach,	atpic_isa_attach),
89 
90 	/* PIC interface */
91 	DEVMETHOD(pic_config,		atpic_config),
92 	DEVMETHOD(pic_dispatch,		atpic_dispatch),
93 	DEVMETHOD(pic_enable,		atpic_enable),
94 	DEVMETHOD(pic_eoi,		atpic_eoi),
95 	DEVMETHOD(pic_ipi,		atpic_ipi),
96 	DEVMETHOD(pic_mask,		atpic_mask),
97 	DEVMETHOD(pic_unmask,		atpic_unmask),
98 	DEVMETHOD(pic_id,		atpic_id),
99 
100 	{ 0, 0 },
101 };
102 
103 static driver_t atpic_isa_driver = {
104 	"atpic",
105 	atpic_isa_methods,
106 	sizeof(struct atpic_softc)
107 };
108 
109 static devclass_t atpic_devclass;
110 
111 DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0);
112 
113 static struct isa_pnp_id atpic_ids[] = {
114 	{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
115 	{ 0 }
116 };
117 
118 static __inline uint8_t
119 atpic_read(struct atpic_softc *sc, int icu, int ofs)
120 {
121 	uint8_t val;
122 
123 	val = bus_read_1(sc->sc_res[icu], ofs);
124 	return (val);
125 }
126 
127 static __inline void
128 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val)
129 {
130 
131 	bus_write_1(sc->sc_res[icu], ofs, val);
132 	bus_barrier(sc->sc_res[icu], ofs, 2 - ofs,
133 	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
134 }
135 
136 static void
137 atpic_intr(void *arg)
138 {
139 
140 	atpic_dispatch(arg, NULL);
141 }
142 
143 static void
144 atpic_isa_identify(driver_t *drv, device_t parent)
145 {
146 	device_t child;
147 
148 	child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1);
149 	device_set_driver(child, drv);
150 	isa_set_logicalid(child, atpic_ids[0].ip_id);
151 	isa_set_vendorid(child, atpic_ids[0].ip_id);
152 
153 	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2);
154 	bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2);
155 
156 	/* ISA interrupts are routed through external interrupt 0. */
157 	bus_set_resource(child, SYS_RES_IRQ, 0, PIC_IRQ_EXT(0), 1);
158 }
159 
160 static int
161 atpic_isa_probe(device_t dev)
162 {
163 	int res;
164 
165 	res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
166 	if (res > 0)
167 		return (res);
168 
169 	device_set_desc(dev, "PC/AT compatible PIC");
170 	return (res);
171 }
172 
173 static void
174 atpic_init(struct atpic_softc *sc, int icu)
175 {
176 
177 	sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0);
178 
179 	atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4);
180 	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0);
181 	atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4);
182 	atpic_write(sc, icu, 1, ICW4_8086);
183 	atpic_write(sc, icu, 1, sc->sc_mask[icu]);
184 	atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR);
185 }
186 
187 static int
188 atpic_isa_attach(device_t dev)
189 {
190 	struct atpic_softc *sc;
191 	int error;
192 
193 	sc = device_get_softc(dev);
194 	sc->sc_dev = dev;
195 
196 	error = ENXIO;
197 
198 	sc->sc_rid[ATPIC_MASTER] = 0;
199 	sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
200 	    &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE);
201 	if (sc->sc_res[ATPIC_MASTER] == NULL)
202 		goto fail;
203 
204 	sc->sc_rid[ATPIC_SLAVE] = 1;
205 	sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
206 	    &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE);
207 	if (sc->sc_res[ATPIC_SLAVE] == NULL)
208 		goto fail;
209 
210 	sc->sc_irid = 0;
211 	sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
212 	    RF_ACTIVE);
213 	if (sc->sc_ires == NULL)
214 		goto fail;
215 
216 	error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE,
217 	    NULL, atpic_intr, dev, &sc->sc_icookie);
218 	if (error)
219 		goto fail;
220 
221 	atpic_init(sc, ATPIC_SLAVE);
222 	atpic_init(sc, ATPIC_MASTER);
223 
224 	powerpc_register_pic(dev, 0x10);
225 	return (0);
226 
227  fail:
228 	if (sc->sc_ires != NULL)
229 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
230 		    sc->sc_ires);
231 	if (sc->sc_res[ATPIC_SLAVE] != NULL)
232 		bus_release_resource(dev, SYS_RES_IOPORT,
233 		    sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]);
234 	if (sc->sc_res[ATPIC_MASTER] != NULL)
235 		bus_release_resource(dev, SYS_RES_IOPORT,
236 		    sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]);
237 	return (error);
238 }
239 
240 
241 /*
242  * PIC interface.
243  */
244 
245 static void
246 atpic_config(device_t dev, u_int irq, enum intr_trigger trig,
247     enum intr_polarity pol)
248 {
249 }
250 
251 static void
252 atpic_dispatch(device_t dev, struct trapframe *tf)
253 {
254 	struct atpic_softc *sc;
255 	uint8_t irq;
256 
257 	sc = device_get_softc(dev);
258 	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P);
259 	irq = atpic_read(sc, ATPIC_MASTER, 0);
260 	atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR);
261 	if ((irq & 0x80) == 0)
262 		return;
263 
264 	if (irq == 0x82) {
265 		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P);
266 		irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8;
267 		atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR);
268 		if ((irq & 0x80) == 0)
269 			return;
270 	}
271 
272 	powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf);
273 }
274 
275 static void
276 atpic_enable(device_t dev, u_int irq, u_int vector)
277 {
278 	struct atpic_softc *sc;
279 
280 	sc = device_get_softc(dev);
281 	sc->sc_vector[irq] = vector;
282 	atpic_unmask(dev, irq);
283 }
284 
285 static void
286 atpic_eoi(device_t dev, u_int irq)
287 {
288 	struct atpic_softc *sc;
289 
290 	sc = device_get_softc(dev);
291 	if (irq > 7)
292 		atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI);
293 	atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI);
294 }
295 
296 static void
297 atpic_ipi(device_t dev, u_int cpu)
298 {
299 	/* No SMP support. */
300 }
301 
302 static void
303 atpic_mask(device_t dev, u_int irq)
304 {
305 	struct atpic_softc *sc;
306 
307 	sc = device_get_softc(dev);
308 	if (irq > 7) {
309 		sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8);
310 		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
311 	} else {
312 		sc->sc_mask[ATPIC_MASTER] |= 1 << irq;
313 		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
314 	}
315 }
316 
317 static void
318 atpic_unmask(device_t dev, u_int irq)
319 {
320 	struct atpic_softc *sc;
321 
322 	sc = device_get_softc(dev);
323 	if (irq > 7) {
324 		sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8));
325 		atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]);
326 	} else {
327 		sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq);
328 		atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]);
329 	}
330 }
331 
332 static uint32_t
333 atpic_id (device_t dev)
334 {
335 
336 	return (ATPIC_ID);
337 }
338 
339