1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009 Marcel Moolenaar 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/cpuset.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/rman.h> 36 37 #include <machine/bus.h> 38 #include <machine/intr_machdep.h> 39 #include <machine/pio.h> 40 41 #include <powerpc/mpc85xx/mpc85xx.h> 42 43 #include <dev/ic/i8259.h> 44 45 #include <isa/isareg.h> 46 #include <isa/isavar.h> 47 48 #include "pic_if.h" 49 50 #define ATPIC_MASTER 0 51 #define ATPIC_SLAVE 1 52 53 struct atpic_softc { 54 device_t sc_dev; 55 56 /* I/O port resources for master & slave. */ 57 struct resource *sc_res[2]; 58 int sc_rid[2]; 59 60 /* Our "routing" interrupt */ 61 struct resource *sc_ires; 62 void *sc_icookie; 63 int sc_irid; 64 65 int sc_vector[16]; 66 uint8_t sc_mask[2]; 67 }; 68 69 static int atpic_isa_attach(device_t); 70 static void atpic_isa_identify(driver_t *, device_t); 71 static int atpic_isa_probe(device_t); 72 73 static void atpic_config(device_t, u_int, enum intr_trigger, 74 enum intr_polarity); 75 static void atpic_dispatch(device_t, struct trapframe *); 76 static void atpic_enable(device_t, u_int, u_int); 77 static void atpic_eoi(device_t, u_int); 78 static void atpic_ipi(device_t, u_int); 79 static void atpic_mask(device_t, u_int); 80 static void atpic_unmask(device_t, u_int); 81 82 static void atpic_ofw_translate_code(device_t, u_int irq, int code, 83 enum intr_trigger *trig, enum intr_polarity *pol); 84 85 static device_method_t atpic_isa_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_identify, atpic_isa_identify), 88 DEVMETHOD(device_probe, atpic_isa_probe), 89 DEVMETHOD(device_attach, atpic_isa_attach), 90 91 /* PIC interface */ 92 DEVMETHOD(pic_config, atpic_config), 93 DEVMETHOD(pic_dispatch, atpic_dispatch), 94 DEVMETHOD(pic_enable, atpic_enable), 95 DEVMETHOD(pic_eoi, atpic_eoi), 96 DEVMETHOD(pic_ipi, atpic_ipi), 97 DEVMETHOD(pic_mask, atpic_mask), 98 DEVMETHOD(pic_unmask, atpic_unmask), 99 100 DEVMETHOD(pic_translate_code, atpic_ofw_translate_code), 101 102 { 0, 0 }, 103 }; 104 105 static driver_t atpic_isa_driver = { 106 "atpic", 107 atpic_isa_methods, 108 sizeof(struct atpic_softc) 109 }; 110 111 static struct isa_pnp_id atpic_ids[] = { 112 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, 113 { 0 } 114 }; 115 116 DRIVER_MODULE(atpic, isa, atpic_isa_driver, 0, 0); 117 ISA_PNP_INFO(atpic_ids); 118 119 static __inline uint8_t 120 atpic_read(struct atpic_softc *sc, int icu, int ofs) 121 { 122 uint8_t val; 123 124 val = bus_read_1(sc->sc_res[icu], ofs); 125 return (val); 126 } 127 128 static __inline void 129 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val) 130 { 131 132 bus_write_1(sc->sc_res[icu], ofs, val); 133 bus_barrier(sc->sc_res[icu], ofs, 2 - ofs, 134 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 135 } 136 137 static void 138 atpic_intr(void *arg) 139 { 140 141 atpic_dispatch(arg, NULL); 142 } 143 144 static void 145 atpic_isa_identify(driver_t *drv, device_t parent) 146 { 147 device_t child; 148 149 child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1); 150 device_set_driver(child, drv); 151 isa_set_logicalid(child, atpic_ids[0].ip_id); 152 isa_set_vendorid(child, atpic_ids[0].ip_id); 153 154 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2); 155 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2); 156 157 /* ISA interrupts are routed through external interrupt 0. */ 158 bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1); 159 } 160 161 static int 162 atpic_isa_probe(device_t dev) 163 { 164 int res; 165 166 res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids); 167 if (res > 0) 168 return (res); 169 170 device_set_desc(dev, "PC/AT compatible PIC"); 171 return (res); 172 } 173 174 static void 175 atpic_init(struct atpic_softc *sc, int icu) 176 { 177 178 sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0); 179 180 atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4); 181 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0); 182 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4); 183 atpic_write(sc, icu, 1, ICW4_8086); 184 atpic_write(sc, icu, 1, sc->sc_mask[icu]); 185 atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR); 186 } 187 188 static int 189 atpic_isa_attach(device_t dev) 190 { 191 struct atpic_softc *sc; 192 int error; 193 194 sc = device_get_softc(dev); 195 sc->sc_dev = dev; 196 197 error = ENXIO; 198 199 sc->sc_rid[ATPIC_MASTER] = 0; 200 sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 201 &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE); 202 if (sc->sc_res[ATPIC_MASTER] == NULL) 203 goto fail; 204 205 sc->sc_rid[ATPIC_SLAVE] = 1; 206 sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 207 &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE); 208 if (sc->sc_res[ATPIC_SLAVE] == NULL) 209 goto fail; 210 211 sc->sc_irid = 0; 212 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, 213 RF_ACTIVE); 214 if (sc->sc_ires == NULL) 215 goto fail; 216 217 error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE, 218 NULL, atpic_intr, dev, &sc->sc_icookie); 219 if (error) 220 goto fail; 221 222 atpic_init(sc, ATPIC_SLAVE); 223 atpic_init(sc, ATPIC_MASTER); 224 225 powerpc_register_pic(dev, 0, 16, 0, TRUE); 226 return (0); 227 228 fail: 229 if (sc->sc_ires != NULL) 230 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 231 sc->sc_ires); 232 if (sc->sc_res[ATPIC_SLAVE] != NULL) 233 bus_release_resource(dev, SYS_RES_IOPORT, 234 sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]); 235 if (sc->sc_res[ATPIC_MASTER] != NULL) 236 bus_release_resource(dev, SYS_RES_IOPORT, 237 sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]); 238 return (error); 239 } 240 241 /* 242 * PIC interface. 243 */ 244 245 static void 246 atpic_config(device_t dev, u_int irq, enum intr_trigger trig, 247 enum intr_polarity pol) 248 { 249 } 250 251 static void 252 atpic_dispatch(device_t dev, struct trapframe *tf) 253 { 254 struct atpic_softc *sc; 255 uint8_t irq; 256 257 sc = device_get_softc(dev); 258 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P); 259 irq = atpic_read(sc, ATPIC_MASTER, 0); 260 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR); 261 if ((irq & 0x80) == 0) 262 return; 263 264 if (irq == 0x82) { 265 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P); 266 irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8; 267 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR); 268 if ((irq & 0x80) == 0) 269 return; 270 } 271 272 powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf); 273 } 274 275 static void 276 atpic_enable(device_t dev, u_int irq, u_int vector) 277 { 278 struct atpic_softc *sc; 279 280 sc = device_get_softc(dev); 281 sc->sc_vector[irq] = vector; 282 atpic_unmask(dev, irq); 283 } 284 285 static void 286 atpic_eoi(device_t dev, u_int irq) 287 { 288 struct atpic_softc *sc; 289 290 sc = device_get_softc(dev); 291 if (irq > 7) 292 atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI); 293 atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI); 294 } 295 296 static void 297 atpic_ipi(device_t dev, u_int cpu) 298 { 299 /* No SMP support. */ 300 } 301 302 static void 303 atpic_mask(device_t dev, u_int irq) 304 { 305 struct atpic_softc *sc; 306 307 sc = device_get_softc(dev); 308 if (irq > 7) { 309 sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8); 310 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]); 311 } else { 312 sc->sc_mask[ATPIC_MASTER] |= 1 << irq; 313 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); 314 } 315 } 316 317 static void 318 atpic_unmask(device_t dev, u_int irq) 319 { 320 struct atpic_softc *sc; 321 322 sc = device_get_softc(dev); 323 if (irq > 7) { 324 sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8)); 325 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]); 326 } else { 327 sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq); 328 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); 329 } 330 } 331 332 static void 333 atpic_ofw_translate_code(device_t dev, u_int irq, int code, 334 enum intr_trigger *trig, enum intr_polarity *pol) 335 { 336 switch (code) { 337 case 0: 338 /* Active L level */ 339 *trig = INTR_TRIGGER_LEVEL; 340 *pol = INTR_POLARITY_LOW; 341 break; 342 case 1: 343 /* Active H level */ 344 *trig = INTR_TRIGGER_LEVEL; 345 *pol = INTR_POLARITY_HIGH; 346 break; 347 case 2: 348 /* H to L edge */ 349 *trig = INTR_TRIGGER_EDGE; 350 *pol = INTR_POLARITY_LOW; 351 break; 352 case 3: 353 /* L to H edge */ 354 *trig = INTR_TRIGGER_EDGE; 355 *pol = INTR_POLARITY_HIGH; 356 break; 357 default: 358 *trig = INTR_TRIGGER_CONFORM; 359 *pol = INTR_POLARITY_CONFORM; 360 } 361 } 362