1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Marcel Moolenaar 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/cpuset.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr_machdep.h> 41 #include <machine/pio.h> 42 43 #include <powerpc/mpc85xx/mpc85xx.h> 44 45 #include <dev/ic/i8259.h> 46 47 #include <isa/isareg.h> 48 #include <isa/isavar.h> 49 50 #include "pic_if.h" 51 52 #define ATPIC_MASTER 0 53 #define ATPIC_SLAVE 1 54 55 struct atpic_softc { 56 device_t sc_dev; 57 58 /* I/O port resources for master & slave. */ 59 struct resource *sc_res[2]; 60 int sc_rid[2]; 61 62 /* Our "routing" interrupt */ 63 struct resource *sc_ires; 64 void *sc_icookie; 65 int sc_irid; 66 67 int sc_vector[16]; 68 uint8_t sc_mask[2]; 69 }; 70 71 static int atpic_isa_attach(device_t); 72 static void atpic_isa_identify(driver_t *, device_t); 73 static int atpic_isa_probe(device_t); 74 75 static void atpic_config(device_t, u_int, enum intr_trigger, 76 enum intr_polarity); 77 static void atpic_dispatch(device_t, struct trapframe *); 78 static void atpic_enable(device_t, u_int, u_int); 79 static void atpic_eoi(device_t, u_int); 80 static void atpic_ipi(device_t, u_int); 81 static void atpic_mask(device_t, u_int); 82 static void atpic_unmask(device_t, u_int); 83 84 static void atpic_ofw_translate_code(device_t, u_int irq, int code, 85 enum intr_trigger *trig, enum intr_polarity *pol); 86 87 static device_method_t atpic_isa_methods[] = { 88 /* Device interface */ 89 DEVMETHOD(device_identify, atpic_isa_identify), 90 DEVMETHOD(device_probe, atpic_isa_probe), 91 DEVMETHOD(device_attach, atpic_isa_attach), 92 93 /* PIC interface */ 94 DEVMETHOD(pic_config, atpic_config), 95 DEVMETHOD(pic_dispatch, atpic_dispatch), 96 DEVMETHOD(pic_enable, atpic_enable), 97 DEVMETHOD(pic_eoi, atpic_eoi), 98 DEVMETHOD(pic_ipi, atpic_ipi), 99 DEVMETHOD(pic_mask, atpic_mask), 100 DEVMETHOD(pic_unmask, atpic_unmask), 101 102 DEVMETHOD(pic_translate_code, atpic_ofw_translate_code), 103 104 { 0, 0 }, 105 }; 106 107 static driver_t atpic_isa_driver = { 108 "atpic", 109 atpic_isa_methods, 110 sizeof(struct atpic_softc) 111 }; 112 113 static devclass_t atpic_devclass; 114 115 static struct isa_pnp_id atpic_ids[] = { 116 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, 117 { 0 } 118 }; 119 120 DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0); 121 ISA_PNP_INFO(atpic_ids); 122 123 static __inline uint8_t 124 atpic_read(struct atpic_softc *sc, int icu, int ofs) 125 { 126 uint8_t val; 127 128 val = bus_read_1(sc->sc_res[icu], ofs); 129 return (val); 130 } 131 132 static __inline void 133 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val) 134 { 135 136 bus_write_1(sc->sc_res[icu], ofs, val); 137 bus_barrier(sc->sc_res[icu], ofs, 2 - ofs, 138 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 139 } 140 141 static void 142 atpic_intr(void *arg) 143 { 144 145 atpic_dispatch(arg, NULL); 146 } 147 148 static void 149 atpic_isa_identify(driver_t *drv, device_t parent) 150 { 151 device_t child; 152 153 child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1); 154 device_set_driver(child, drv); 155 isa_set_logicalid(child, atpic_ids[0].ip_id); 156 isa_set_vendorid(child, atpic_ids[0].ip_id); 157 158 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2); 159 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2); 160 161 /* ISA interrupts are routed through external interrupt 0. */ 162 bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1); 163 } 164 165 static int 166 atpic_isa_probe(device_t dev) 167 { 168 int res; 169 170 res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids); 171 if (res > 0) 172 return (res); 173 174 device_set_desc(dev, "PC/AT compatible PIC"); 175 return (res); 176 } 177 178 static void 179 atpic_init(struct atpic_softc *sc, int icu) 180 { 181 182 sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0); 183 184 atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4); 185 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0); 186 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4); 187 atpic_write(sc, icu, 1, ICW4_8086); 188 atpic_write(sc, icu, 1, sc->sc_mask[icu]); 189 atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR); 190 } 191 192 static int 193 atpic_isa_attach(device_t dev) 194 { 195 struct atpic_softc *sc; 196 int error; 197 198 sc = device_get_softc(dev); 199 sc->sc_dev = dev; 200 201 error = ENXIO; 202 203 sc->sc_rid[ATPIC_MASTER] = 0; 204 sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 205 &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE); 206 if (sc->sc_res[ATPIC_MASTER] == NULL) 207 goto fail; 208 209 sc->sc_rid[ATPIC_SLAVE] = 1; 210 sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 211 &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE); 212 if (sc->sc_res[ATPIC_SLAVE] == NULL) 213 goto fail; 214 215 sc->sc_irid = 0; 216 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, 217 RF_ACTIVE); 218 if (sc->sc_ires == NULL) 219 goto fail; 220 221 error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE, 222 NULL, atpic_intr, dev, &sc->sc_icookie); 223 if (error) 224 goto fail; 225 226 atpic_init(sc, ATPIC_SLAVE); 227 atpic_init(sc, ATPIC_MASTER); 228 229 powerpc_register_pic(dev, 0, 16, 0, TRUE); 230 return (0); 231 232 fail: 233 if (sc->sc_ires != NULL) 234 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 235 sc->sc_ires); 236 if (sc->sc_res[ATPIC_SLAVE] != NULL) 237 bus_release_resource(dev, SYS_RES_IOPORT, 238 sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]); 239 if (sc->sc_res[ATPIC_MASTER] != NULL) 240 bus_release_resource(dev, SYS_RES_IOPORT, 241 sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]); 242 return (error); 243 } 244 245 246 /* 247 * PIC interface. 248 */ 249 250 static void 251 atpic_config(device_t dev, u_int irq, enum intr_trigger trig, 252 enum intr_polarity pol) 253 { 254 } 255 256 static void 257 atpic_dispatch(device_t dev, struct trapframe *tf) 258 { 259 struct atpic_softc *sc; 260 uint8_t irq; 261 262 sc = device_get_softc(dev); 263 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P); 264 irq = atpic_read(sc, ATPIC_MASTER, 0); 265 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR); 266 if ((irq & 0x80) == 0) 267 return; 268 269 if (irq == 0x82) { 270 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P); 271 irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8; 272 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR); 273 if ((irq & 0x80) == 0) 274 return; 275 } 276 277 powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf); 278 } 279 280 static void 281 atpic_enable(device_t dev, u_int irq, u_int vector) 282 { 283 struct atpic_softc *sc; 284 285 sc = device_get_softc(dev); 286 sc->sc_vector[irq] = vector; 287 atpic_unmask(dev, irq); 288 } 289 290 static void 291 atpic_eoi(device_t dev, u_int irq) 292 { 293 struct atpic_softc *sc; 294 295 sc = device_get_softc(dev); 296 if (irq > 7) 297 atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI); 298 atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI); 299 } 300 301 static void 302 atpic_ipi(device_t dev, u_int cpu) 303 { 304 /* No SMP support. */ 305 } 306 307 static void 308 atpic_mask(device_t dev, u_int irq) 309 { 310 struct atpic_softc *sc; 311 312 sc = device_get_softc(dev); 313 if (irq > 7) { 314 sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8); 315 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]); 316 } else { 317 sc->sc_mask[ATPIC_MASTER] |= 1 << irq; 318 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); 319 } 320 } 321 322 static void 323 atpic_unmask(device_t dev, u_int irq) 324 { 325 struct atpic_softc *sc; 326 327 sc = device_get_softc(dev); 328 if (irq > 7) { 329 sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8)); 330 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]); 331 } else { 332 sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq); 333 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); 334 } 335 } 336 337 static void 338 atpic_ofw_translate_code(device_t dev, u_int irq, int code, 339 enum intr_trigger *trig, enum intr_polarity *pol) 340 { 341 switch (code) { 342 case 0: 343 /* Active L level */ 344 *trig = INTR_TRIGGER_LEVEL; 345 *pol = INTR_POLARITY_LOW; 346 break; 347 case 1: 348 /* Active H level */ 349 *trig = INTR_TRIGGER_LEVEL; 350 *pol = INTR_POLARITY_HIGH; 351 break; 352 case 2: 353 /* H to L edge */ 354 *trig = INTR_TRIGGER_EDGE; 355 *pol = INTR_POLARITY_LOW; 356 break; 357 case 3: 358 /* L to H edge */ 359 *trig = INTR_TRIGGER_EDGE; 360 *pol = INTR_POLARITY_HIGH; 361 break; 362 default: 363 *trig = INTR_TRIGGER_CONFORM; 364 *pol = INTR_POLARITY_CONFORM; 365 } 366 } 367