1 /*- 2 * Copyright (c) 2009 Marcel Moolenaar 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/cpuset.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/rman.h> 36 37 #include <machine/bus.h> 38 #include <machine/intr_machdep.h> 39 #include <machine/pio.h> 40 41 #include <powerpc/mpc85xx/mpc85xx.h> 42 43 #include <dev/ic/i8259.h> 44 45 #include <isa/isareg.h> 46 #include <isa/isavar.h> 47 48 #include "pic_if.h" 49 50 #define ATPIC_MASTER 0 51 #define ATPIC_SLAVE 1 52 53 struct atpic_softc { 54 device_t sc_dev; 55 56 /* I/O port resources for master & slave. */ 57 struct resource *sc_res[2]; 58 int sc_rid[2]; 59 60 /* Our "routing" interrupt */ 61 struct resource *sc_ires; 62 void *sc_icookie; 63 int sc_irid; 64 65 int sc_vector[16]; 66 uint8_t sc_mask[2]; 67 }; 68 69 static int atpic_isa_attach(device_t); 70 static void atpic_isa_identify(driver_t *, device_t); 71 static int atpic_isa_probe(device_t); 72 73 static void atpic_config(device_t, u_int, enum intr_trigger, 74 enum intr_polarity); 75 static void atpic_dispatch(device_t, struct trapframe *); 76 static void atpic_enable(device_t, u_int, u_int); 77 static void atpic_eoi(device_t, u_int); 78 static void atpic_ipi(device_t, u_int); 79 static void atpic_mask(device_t, u_int); 80 static void atpic_unmask(device_t, u_int); 81 82 static device_method_t atpic_isa_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_identify, atpic_isa_identify), 85 DEVMETHOD(device_probe, atpic_isa_probe), 86 DEVMETHOD(device_attach, atpic_isa_attach), 87 88 /* PIC interface */ 89 DEVMETHOD(pic_config, atpic_config), 90 DEVMETHOD(pic_dispatch, atpic_dispatch), 91 DEVMETHOD(pic_enable, atpic_enable), 92 DEVMETHOD(pic_eoi, atpic_eoi), 93 DEVMETHOD(pic_ipi, atpic_ipi), 94 DEVMETHOD(pic_mask, atpic_mask), 95 DEVMETHOD(pic_unmask, atpic_unmask), 96 97 { 0, 0 }, 98 }; 99 100 static driver_t atpic_isa_driver = { 101 "atpic", 102 atpic_isa_methods, 103 sizeof(struct atpic_softc) 104 }; 105 106 static devclass_t atpic_devclass; 107 108 DRIVER_MODULE(atpic, isa, atpic_isa_driver, atpic_devclass, 0, 0); 109 110 static struct isa_pnp_id atpic_ids[] = { 111 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, 112 { 0 } 113 }; 114 115 static __inline uint8_t 116 atpic_read(struct atpic_softc *sc, int icu, int ofs) 117 { 118 uint8_t val; 119 120 val = bus_read_1(sc->sc_res[icu], ofs); 121 return (val); 122 } 123 124 static __inline void 125 atpic_write(struct atpic_softc *sc, int icu, int ofs, uint8_t val) 126 { 127 128 bus_write_1(sc->sc_res[icu], ofs, val); 129 bus_barrier(sc->sc_res[icu], ofs, 2 - ofs, 130 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 131 } 132 133 static void 134 atpic_intr(void *arg) 135 { 136 137 atpic_dispatch(arg, NULL); 138 } 139 140 static void 141 atpic_isa_identify(driver_t *drv, device_t parent) 142 { 143 device_t child; 144 145 child = BUS_ADD_CHILD(parent, ISA_ORDER_SENSITIVE, drv->name, -1); 146 device_set_driver(child, drv); 147 isa_set_logicalid(child, atpic_ids[0].ip_id); 148 isa_set_vendorid(child, atpic_ids[0].ip_id); 149 150 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_MASTER, IO_ICU1, 2); 151 bus_set_resource(child, SYS_RES_IOPORT, ATPIC_SLAVE, IO_ICU2, 2); 152 153 /* ISA interrupts are routed through external interrupt 0. */ 154 bus_set_resource(child, SYS_RES_IRQ, 0, 16, 1); 155 } 156 157 static int 158 atpic_isa_probe(device_t dev) 159 { 160 int res; 161 162 res = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids); 163 if (res > 0) 164 return (res); 165 166 device_set_desc(dev, "PC/AT compatible PIC"); 167 return (res); 168 } 169 170 static void 171 atpic_init(struct atpic_softc *sc, int icu) 172 { 173 174 sc->sc_mask[icu] = 0xff - ((icu == ATPIC_MASTER) ? 4 : 0); 175 176 atpic_write(sc, icu, 0, ICW1_RESET | ICW1_IC4); 177 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 8 : 0); 178 atpic_write(sc, icu, 1, (icu == ATPIC_SLAVE) ? 2 : 4); 179 atpic_write(sc, icu, 1, ICW4_8086); 180 atpic_write(sc, icu, 1, sc->sc_mask[icu]); 181 atpic_write(sc, icu, 0, OCW3_SEL | OCW3_RR); 182 } 183 184 static int 185 atpic_isa_attach(device_t dev) 186 { 187 struct atpic_softc *sc; 188 int error; 189 190 sc = device_get_softc(dev); 191 sc->sc_dev = dev; 192 193 error = ENXIO; 194 195 sc->sc_rid[ATPIC_MASTER] = 0; 196 sc->sc_res[ATPIC_MASTER] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 197 &sc->sc_rid[ATPIC_MASTER], RF_ACTIVE); 198 if (sc->sc_res[ATPIC_MASTER] == NULL) 199 goto fail; 200 201 sc->sc_rid[ATPIC_SLAVE] = 1; 202 sc->sc_res[ATPIC_SLAVE] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 203 &sc->sc_rid[ATPIC_SLAVE], RF_ACTIVE); 204 if (sc->sc_res[ATPIC_SLAVE] == NULL) 205 goto fail; 206 207 sc->sc_irid = 0; 208 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, 209 RF_ACTIVE); 210 if (sc->sc_ires == NULL) 211 goto fail; 212 213 error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_MISC | INTR_MPSAFE, 214 NULL, atpic_intr, dev, &sc->sc_icookie); 215 if (error) 216 goto fail; 217 218 atpic_init(sc, ATPIC_SLAVE); 219 atpic_init(sc, ATPIC_MASTER); 220 221 powerpc_register_pic(dev, 0, 16, 0, TRUE); 222 return (0); 223 224 fail: 225 if (sc->sc_ires != NULL) 226 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 227 sc->sc_ires); 228 if (sc->sc_res[ATPIC_SLAVE] != NULL) 229 bus_release_resource(dev, SYS_RES_IOPORT, 230 sc->sc_rid[ATPIC_SLAVE], sc->sc_res[ATPIC_SLAVE]); 231 if (sc->sc_res[ATPIC_MASTER] != NULL) 232 bus_release_resource(dev, SYS_RES_IOPORT, 233 sc->sc_rid[ATPIC_MASTER], sc->sc_res[ATPIC_MASTER]); 234 return (error); 235 } 236 237 238 /* 239 * PIC interface. 240 */ 241 242 static void 243 atpic_config(device_t dev, u_int irq, enum intr_trigger trig, 244 enum intr_polarity pol) 245 { 246 } 247 248 static void 249 atpic_dispatch(device_t dev, struct trapframe *tf) 250 { 251 struct atpic_softc *sc; 252 uint8_t irq; 253 254 sc = device_get_softc(dev); 255 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_P); 256 irq = atpic_read(sc, ATPIC_MASTER, 0); 257 atpic_write(sc, ATPIC_MASTER, 0, OCW3_SEL | OCW3_RR); 258 if ((irq & 0x80) == 0) 259 return; 260 261 if (irq == 0x82) { 262 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_P); 263 irq = atpic_read(sc, ATPIC_SLAVE, 0) + 8; 264 atpic_write(sc, ATPIC_SLAVE, 0, OCW3_SEL | OCW3_RR); 265 if ((irq & 0x80) == 0) 266 return; 267 } 268 269 powerpc_dispatch_intr(sc->sc_vector[irq & 0x0f], tf); 270 } 271 272 static void 273 atpic_enable(device_t dev, u_int irq, u_int vector) 274 { 275 struct atpic_softc *sc; 276 277 sc = device_get_softc(dev); 278 sc->sc_vector[irq] = vector; 279 atpic_unmask(dev, irq); 280 } 281 282 static void 283 atpic_eoi(device_t dev, u_int irq) 284 { 285 struct atpic_softc *sc; 286 287 sc = device_get_softc(dev); 288 if (irq > 7) 289 atpic_write(sc, ATPIC_SLAVE, 0, OCW2_EOI); 290 atpic_write(sc, ATPIC_MASTER, 0, OCW2_EOI); 291 } 292 293 static void 294 atpic_ipi(device_t dev, u_int cpu) 295 { 296 /* No SMP support. */ 297 } 298 299 static void 300 atpic_mask(device_t dev, u_int irq) 301 { 302 struct atpic_softc *sc; 303 304 sc = device_get_softc(dev); 305 if (irq > 7) { 306 sc->sc_mask[ATPIC_SLAVE] |= 1 << (irq - 8); 307 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]); 308 } else { 309 sc->sc_mask[ATPIC_MASTER] |= 1 << irq; 310 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); 311 } 312 } 313 314 static void 315 atpic_unmask(device_t dev, u_int irq) 316 { 317 struct atpic_softc *sc; 318 319 sc = device_get_softc(dev); 320 if (irq > 7) { 321 sc->sc_mask[ATPIC_SLAVE] &= ~(1 << (irq - 8)); 322 atpic_write(sc, ATPIC_SLAVE, 1, sc->sc_mask[ATPIC_SLAVE]); 323 } else { 324 sc->sc_mask[ATPIC_MASTER] &= ~(1 << irq); 325 atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); 326 } 327 } 328