160727d8bSWarner Losh /*- 2*51369649SPedro F. Giffuni * SPDX-License-Identifier: BSD-4-Clause 3*51369649SPedro F. Giffuni * 4fb75554eSBenno Rice * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5fb75554eSBenno Rice * Copyright (C) 1995, 1996 TooLs GmbH. 6fb75554eSBenno Rice * All rights reserved. 7fb75554eSBenno Rice * 8fb75554eSBenno Rice * Redistribution and use in source and binary forms, with or without 9fb75554eSBenno Rice * modification, are permitted provided that the following conditions 10fb75554eSBenno Rice * are met: 11fb75554eSBenno Rice * 1. Redistributions of source code must retain the above copyright 12fb75554eSBenno Rice * notice, this list of conditions and the following disclaimer. 13fb75554eSBenno Rice * 2. Redistributions in binary form must reproduce the above copyright 14fb75554eSBenno Rice * notice, this list of conditions and the following disclaimer in the 15fb75554eSBenno Rice * documentation and/or other materials provided with the distribution. 16fb75554eSBenno Rice * 3. All advertising materials mentioning features or use of this software 17fb75554eSBenno Rice * must display the following acknowledgement: 18fb75554eSBenno Rice * This product includes software developed by TooLs GmbH. 19fb75554eSBenno Rice * 4. The name of TooLs GmbH may not be used to endorse or promote products 20fb75554eSBenno Rice * derived from this software without specific prior written permission. 21fb75554eSBenno Rice * 22fb75554eSBenno Rice * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23fb75554eSBenno Rice * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24fb75554eSBenno Rice * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25fb75554eSBenno Rice * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26fb75554eSBenno Rice * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27fb75554eSBenno Rice * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28fb75554eSBenno Rice * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29fb75554eSBenno Rice * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30fb75554eSBenno Rice * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31fb75554eSBenno Rice * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32dfeade78SDavid E. O'Brien * 33dfeade78SDavid E. O'Brien * $NetBSD: signal.h,v 1.4 1998/09/14 02:48:34 thorpej Exp $ 34dfeade78SDavid E. O'Brien * $FreeBSD$ 35fb75554eSBenno Rice */ 36dfeade78SDavid E. O'Brien 37fb75554eSBenno Rice #ifndef _MACHINE_UCONTEXT_H_ 38fb75554eSBenno Rice #define _MACHINE_UCONTEXT_H_ 39fb75554eSBenno Rice 40fb75554eSBenno Rice typedef struct __mcontext { 41919cb336SPeter Grehan int mc_vers; 42919cb336SPeter Grehan int mc_flags; 43919cb336SPeter Grehan #define _MC_FP_VALID 0x01 44919cb336SPeter Grehan #define _MC_AV_VALID 0x02 45fb75554eSBenno Rice int mc_onstack; /* saved onstack flag */ 46919cb336SPeter Grehan int mc_len; /* sizeof(__mcontext) */ 4790edf67eSKonstantin Belousov __uint64_t mc_avec[32*2]; /* vector register file */ 4890edf67eSKonstantin Belousov __uint32_t mc_av[2]; 4990edf67eSKonstantin Belousov __register_t mc_frame[42]; 5090edf67eSKonstantin Belousov __uint64_t mc_fpreg[33]; 5190edf67eSKonstantin Belousov __uint64_t mc_vsxfpreg[32]; /* low-order half of VSR0-31 */ 52919cb336SPeter Grehan } mcontext_t __aligned(16); 53919cb336SPeter Grehan 54c3e289e1SNathan Whitehorn #if defined(_KERNEL) && defined(__powerpc64__) 55c3e289e1SNathan Whitehorn typedef struct __mcontext32 { 56c3e289e1SNathan Whitehorn int mc_vers; 57c3e289e1SNathan Whitehorn int mc_flags; 58c3e289e1SNathan Whitehorn #define _MC_FP_VALID 0x01 59c3e289e1SNathan Whitehorn #define _MC_AV_VALID 0x02 60c3e289e1SNathan Whitehorn int mc_onstack; /* saved onstack flag */ 61c3e289e1SNathan Whitehorn int mc_len; /* sizeof(__mcontext) */ 62c3e289e1SNathan Whitehorn uint64_t mc_avec[32*2]; /* vector register file */ 63c3e289e1SNathan Whitehorn uint32_t mc_av[2]; 64c3e289e1SNathan Whitehorn uint32_t mc_frame[42]; 65c3e289e1SNathan Whitehorn uint64_t mc_fpreg[33]; 660aff8b5cSNathan Whitehorn uint64_t mc_vsxfpreg[32]; /* low-order half of VSR0-31 */ 67c3e289e1SNathan Whitehorn } mcontext32_t __aligned(16); 68c3e289e1SNathan Whitehorn #endif 69c3e289e1SNathan Whitehorn 70919cb336SPeter Grehan /* GPRs and supervisor-level regs */ 71919cb336SPeter Grehan #define mc_gpr mc_frame 72919cb336SPeter Grehan #define mc_lr mc_frame[32] 73919cb336SPeter Grehan #define mc_cr mc_frame[33] 74919cb336SPeter Grehan #define mc_xer mc_frame[34] 75919cb336SPeter Grehan #define mc_ctr mc_frame[35] 76919cb336SPeter Grehan #define mc_srr0 mc_frame[36] 77919cb336SPeter Grehan #define mc_srr1 mc_frame[37] 78fbd21ea6SNathan Whitehorn #define mc_exc mc_frame[38] 79fbd21ea6SNathan Whitehorn #define mc_dar mc_frame[39] 80fbd21ea6SNathan Whitehorn #define mc_dsisr mc_frame[40] 81919cb336SPeter Grehan 82919cb336SPeter Grehan /* floating-point state */ 83919cb336SPeter Grehan #define mc_fpscr mc_fpreg[32] 84919cb336SPeter Grehan 85919cb336SPeter Grehan /* altivec state */ 86919cb336SPeter Grehan #define mc_vscr mc_av[0] 87919cb336SPeter Grehan #define mc_vrsave mc_av[1] 88919cb336SPeter Grehan 89919cb336SPeter Grehan #define _MC_VERSION 0x1 903327cde2SPeter Grehan #define _MC_VERSION_KSE 0xee /* partial ucontext for libpthread */ 91fb75554eSBenno Rice 92fb75554eSBenno Rice #endif /* !_MACHINE_UCONTEXT_H_ */ 93