xref: /freebsd/sys/powerpc/include/trap.h (revision e40139ff33b48b56a24c808b166b04b8ee6f5b21)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5  * Copyright (C) 1995, 1996 TooLs GmbH.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by TooLs GmbH.
19  * 4. The name of TooLs GmbH may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $
34  * $FreeBSD$
35  */
36 
37 #ifndef	_POWERPC_TRAP_H_
38 #define	_POWERPC_TRAP_H_
39 
40 #define	EXC_RSVD	0x0000		/* Reserved */
41 #define	EXC_RST		0x0100		/* Reset; all but IBM4xx */
42 #define	EXC_MCHK	0x0200		/* Machine Check */
43 #define	EXC_DSI		0x0300		/* Data Storage Interrupt */
44 #define	EXC_DSE		0x0380		/* Data Segment Interrupt */
45 #define	EXC_ISI		0x0400		/* Instruction Storage Interrupt */
46 #define	EXC_ISE		0x0480		/* Instruction Segment Interrupt */
47 #define	EXC_EXI		0x0500		/* External Interrupt */
48 #define	EXC_ALI		0x0600		/* Alignment Interrupt */
49 #define	EXC_PGM		0x0700		/* Program Interrupt */
50 #define	EXC_FPU		0x0800		/* Floating-point Unavailable */
51 #define	EXC_DECR	0x0900		/* Decrementer Interrupt */
52 #define	EXC_SC		0x0c00		/* System Call */
53 #define	EXC_TRC		0x0d00		/* Trace */
54 #define	EXC_FPA		0x0e00		/* Floating-point Assist */
55 
56 /* The following is only available on the 601: */
57 #define	EXC_RUNMODETRC	0x2000		/* Run Mode/Trace Exception */
58 
59 /* The following are only available on 970(G5): */
60 #define	EXC_VECAST_G5	0x1700		/* AltiVec Assist */
61 
62 /* The following are only available on 7400(G4): */
63 #define	EXC_VEC		0x0f20		/* AltiVec Unavailable */
64 #define	EXC_VECAST_G4	0x1600		/* AltiVec Assist */
65 
66 /* The following are only available on 604/750/7400: */
67 #define	EXC_PERF	0x0f00		/* Performance Monitoring */
68 #define	EXC_BPT		0x1300		/* Instruction Breakpoint */
69 #define	EXC_SMI		0x1400		/* System Managment Interrupt */
70 
71 /* The following are only available on 750/7400: */
72 #define	EXC_THRM	0x1700		/* Thermal Management Interrupt */
73 
74 /* And these are only on the 603: */
75 #define	EXC_IMISS	0x1000		/* Instruction translation miss */
76 #define	EXC_DLMISS	0x1100		/* Data load translation miss */
77 #define	EXC_DSMISS	0x1200		/* Data store translation miss */
78 
79 /* Power ISA 2.06+: */
80 #define	EXC_HDSI	0x0e00		/* Hypervisor Data Storage */
81 #define	EXC_HISI	0x0e20		/* Hypervisor Instruction Storage */
82 #define	EXC_HEA		0x0e40		/* Hypervisor Emulation Assistance */
83 #define	EXC_HMI		0x0e60		/* Hypervisor Maintenance */
84 #define	EXC_VSX		0x0f40		/* VSX Unavailable */
85 
86 /* Power ISA 2.07+: */
87 #define	EXC_FAC		0x0f60		/* Facility Unavailable */
88 #define	EXC_HFAC	0x0f80		/* Hypervisor Facility Unavailable */
89 
90 /* Power ISA 3.0+: */
91 #define	EXC_HVI		0x0ea0		/* Hypervisor Virtualization */
92 
93 /* The following are available on 4xx and 85xx */
94 #define	EXC_CRIT	0x0100		/* Critical Input Interrupt */
95 #define	EXC_PIT		0x1000		/* Programmable Interval Timer */
96 #define	EXC_FIT		0x1010		/* Fixed Interval Timer */
97 #define	EXC_WDOG	0x1020		/* Watchdog Timer */
98 #define	EXC_DTMISS	0x1100		/* Data TLB Miss */
99 #define	EXC_ITMISS	0x1200		/* Instruction TLB Miss */
100 #define	EXC_APU		0x1300		/* Auxiliary Processing Unit */
101 #define	EXC_DEBUG	0x2f10		/* Debug trap */
102 #define	EXC_VECAST_E	0x2f20		/* Altivec Assist (Book-E) */
103 #define	EXC_SPFPD	0x2f30		/* SPE Floating-point Data */
104 #define	EXC_SPFPR	0x2f40		/* SPE Floating-point Round */
105 
106 /* POWER8 */
107 #define EXC_SOFT_PATCH	0x1500		/* POWER8 Soft Patch Exception */
108 
109 #define	EXC_LAST	0x2f00		/* Last possible exception vector */
110 
111 #define	EXC_AST		0x3000		/* Fake AST vector */
112 
113 /* Trap was in user mode */
114 #define	EXC_USER	0x10000
115 
116 
117 /*
118  * EXC_ALI sets bits in the DSISR and DAR to provide enough
119  * information to recover from the unaligned access without needing to
120  * parse the offending instruction. This includes certain bits of the
121  * opcode, and information about what registers are used. The opcode
122  * indicator values below come from Appendix F of Book III of "The
123  * PowerPC Architecture".
124  */
125 
126 #define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
127 #define EXC_ALI_LFD	0x09
128 #define EXC_ALI_STFD	0x0b
129 
130 /* Macros to extract register information */
131 #define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f)   /* source or target */
132 #define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
133 #define	EXC_ALI_INST_RST(instr)	((instr >> 21) & 0x1f)
134 
135 /*
136  * SRR1 bits for program exception traps. These identify what caused
137  * the program exception. See section 6.5.9 of the Power ISA Version
138  * 2.05.
139  */
140 
141 #define	EXC_PGM_FPENABLED	(1UL << 20)
142 #define	EXC_PGM_ILLEGAL		(1UL << 19)
143 #define	EXC_PGM_PRIV		(1UL << 18)
144 #define	EXC_PGM_TRAP		(1UL << 17)
145 
146 /* DTrace trap opcode. */
147 #define EXC_DTRACE	0x7ffff808
148 
149 /* Magic pointer to store TOC base and other info for trap handlers on ppc64 */
150 #define	TRAP_ENTRY	0x1e8
151 #define	TRAP_GENTRAP	0x1f0
152 #define	TRAP_TOCBASE	0x1f8
153 
154 #ifndef LOCORE
155 struct	trapframe;
156 struct	thread;
157 extern int	(*hmi_handler)(struct trapframe *);
158 void    trap(struct trapframe *);
159 int	ppc_instr_emulate(struct trapframe *, struct thread *);
160 #endif
161 
162 #endif	/* _POWERPC_TRAP_H_ */
163