1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $ 34 * $FreeBSD$ 35 */ 36 37 #ifndef _POWERPC_TRAP_H_ 38 #define _POWERPC_TRAP_H_ 39 40 #define EXC_RSVD 0x0000 /* Reserved */ 41 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */ 42 #define EXC_MCHK 0x0200 /* Machine Check */ 43 #define EXC_DSI 0x0300 /* Data Storage Interrupt */ 44 #define EXC_DSE 0x0380 /* Data Segment Interrupt */ 45 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */ 46 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */ 47 #define EXC_EXI 0x0500 /* External Interrupt */ 48 #define EXC_ALI 0x0600 /* Alignment Interrupt */ 49 #define EXC_PGM 0x0700 /* Program Interrupt */ 50 #define EXC_FPU 0x0800 /* Floating-point Unavailable */ 51 #define EXC_DECR 0x0900 /* Decrementer Interrupt */ 52 #define EXC_SC 0x0c00 /* System Call */ 53 #define EXC_TRC 0x0d00 /* Trace */ 54 #define EXC_FPA 0x0e00 /* Floating-point Assist */ 55 56 /* The following is only available on the 601: */ 57 #define EXC_RUNMODETRC 0x2000 /* Run Mode/Trace Exception */ 58 59 /* The following are only available on 970(G5): */ 60 #define EXC_VECAST_G5 0x1700 /* AltiVec Assist */ 61 62 /* The following are only available on 7400(G4): */ 63 #define EXC_VEC 0x0f20 /* AltiVec Unavailable */ 64 #define EXC_VECAST_G4 0x1600 /* AltiVec Assist */ 65 66 /* The following are only available on 604/750/7400: */ 67 #define EXC_PERF 0x0f00 /* Performance Monitoring */ 68 #define EXC_BPT 0x1300 /* Instruction Breakpoint */ 69 #define EXC_SMI 0x1400 /* System Managment Interrupt */ 70 71 /* The following are only available on 750/7400: */ 72 #define EXC_THRM 0x1700 /* Thermal Management Interrupt */ 73 74 /* And these are only on the 603: */ 75 #define EXC_IMISS 0x1000 /* Instruction translation miss */ 76 #define EXC_DLMISS 0x1100 /* Data load translation miss */ 77 #define EXC_DSMISS 0x1200 /* Data store translation miss */ 78 79 /* Power ISA 2.06+: */ 80 #define EXC_HEA 0x0e40 /* Hypervisor Emulation Assistance */ 81 #define EXC_VSX 0x0f40 /* VSX Unavailable */ 82 83 /* The following are available on 4xx and 85xx */ 84 #define EXC_CRIT 0x0100 /* Critical Input Interrupt */ 85 #define EXC_PIT 0x1000 /* Programmable Interval Timer */ 86 #define EXC_FIT 0x1010 /* Fixed Interval Timer */ 87 #define EXC_WDOG 0x1020 /* Watchdog Timer */ 88 #define EXC_DTMISS 0x1100 /* Data TLB Miss */ 89 #define EXC_ITMISS 0x1200 /* Instruction TLB Miss */ 90 #define EXC_APU 0x1300 /* Auxiliary Processing Unit */ 91 #define EXC_DEBUG 0x2f10 /* Debug trap */ 92 #define EXC_VECAST_E 0x2f20 /* Altivec Assist (Book-E) */ 93 94 #define EXC_LAST 0x2f00 /* Last possible exception vector */ 95 96 #define EXC_AST 0x3000 /* Fake AST vector */ 97 98 /* Trap was in user mode */ 99 #define EXC_USER 0x10000 100 101 102 /* 103 * EXC_ALI sets bits in the DSISR and DAR to provide enough 104 * information to recover from the unaligned access without needing to 105 * parse the offending instruction. This includes certain bits of the 106 * opcode, and information about what registers are used. The opcode 107 * indicator values below come from Appendix F of Book III of "The 108 * PowerPC Architecture". 109 */ 110 111 #define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f) 112 #define EXC_ALI_LFD 0x09 113 #define EXC_ALI_STFD 0x0b 114 115 /* Macros to extract register information */ 116 #define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */ 117 #define EXC_ALI_RA(dsisr) (dsisr & 0x1f) 118 #define EXC_ALI_SPE_REG(instr) ((instr >> 21) & 0x1f) 119 120 /* 121 * SRR1 bits for program exception traps. These identify what caused 122 * the program exception. See section 6.5.9 of the Power ISA Version 123 * 2.05. 124 */ 125 126 #define EXC_PGM_FPENABLED (1UL << 20) 127 #define EXC_PGM_ILLEGAL (1UL << 19) 128 #define EXC_PGM_PRIV (1UL << 18) 129 #define EXC_PGM_TRAP (1UL << 17) 130 131 /* DTrace trap opcode. */ 132 #define EXC_DTRACE 0x7ffff808 133 134 /* Magic pointer to store TOC base and other info for trap handlers on ppc64 */ 135 #define TRAP_GENTRAP 0x1f0 136 #define TRAP_TOCBASE 0x1f8 137 138 #ifndef LOCORE 139 struct trapframe; 140 struct pcb; 141 void trap(struct trapframe *); 142 int ppc_instr_emulate(struct trapframe *, struct pcb *); 143 #endif 144 145 #endif /* _POWERPC_TRAP_H_ */ 146