1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_PTE_H_ 38 #define _MACHINE_PTE_H_ 39 40 #if defined(AIM) 41 42 /* 43 * Page Table Entries 44 */ 45 #ifndef LOCORE 46 47 /* 32-bit PTE */ 48 struct pte { 49 u_int32_t pte_hi; 50 u_int32_t pte_lo; 51 }; 52 53 struct pteg { 54 struct pte pt[8]; 55 }; 56 57 /* 64-bit (long) PTE */ 58 struct lpte { 59 u_int64_t pte_hi; 60 u_int64_t pte_lo; 61 }; 62 63 struct lpteg { 64 struct lpte pt[8]; 65 }; 66 67 /* Partition table entry */ 68 struct pate { 69 u_int64_t pagetab; 70 u_int64_t proctab; 71 }; 72 73 #endif /* LOCORE */ 74 75 /* 32-bit PTE definitions */ 76 77 /* High word: */ 78 #define PTE_VALID 0x80000000 79 #define PTE_VSID_SHFT 7 80 #define PTE_HID 0x00000040 81 #define PTE_API 0x0000003f 82 /* Low word: */ 83 #define PTE_RPGN 0xfffff000 84 #define PTE_REF 0x00000100 85 #define PTE_CHG 0x00000080 86 #define PTE_WIMG 0x00000078 87 #define PTE_W 0x00000040 88 #define PTE_I 0x00000020 89 #define PTE_M 0x00000010 90 #define PTE_G 0x00000008 91 #define PTE_PP 0x00000003 92 #define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ 93 #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ 94 #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ 95 #define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ 96 #define PTE_RW PTE_BW 97 #define PTE_RO PTE_BR 98 99 #define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ 100 101 /* 64-bit PTE definitions */ 102 103 /* High quadword: */ 104 #define LPTE_VSID_SHIFT 12 105 #define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL 106 #define LPTE_API 0x0000000000000F80ULL 107 #define LPTE_SWBITS 0x0000000000000078ULL 108 #define LPTE_WIRED 0x0000000000000010ULL 109 #define LPTE_LOCKED 0x0000000000000008ULL 110 #define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ 111 #define LPTE_HID 0x0000000000000002ULL 112 #define LPTE_VALID 0x0000000000000001ULL 113 114 /* Low quadword: */ 115 #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ 116 #define LPTE_RPGN 0xfffffffffffff000ULL 117 #define LPTE_REF EXTEND_PTE( PTE_REF ) 118 #define LPTE_CHG EXTEND_PTE( PTE_CHG ) 119 #define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) 120 #define LPTE_W EXTEND_PTE( PTE_W ) 121 #define LPTE_I EXTEND_PTE( PTE_I ) 122 #define LPTE_M EXTEND_PTE( PTE_M ) 123 #define LPTE_G EXTEND_PTE( PTE_G ) 124 #define LPTE_NOEXEC 0x0000000000000004ULL 125 #define LPTE_PP EXTEND_PTE( PTE_PP ) 126 127 #define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ 128 #define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ 129 #define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ 130 #define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ 131 #define LPTE_RW LPTE_BW 132 #define LPTE_RO LPTE_BR 133 134 /* POWER ISA 3.0 Radix Table Definitions */ 135 #define RPTE_VALID 0x8000000000000000ULL 136 #define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */ 137 #define RPTE_SW0 0x2000000000000000ULL 138 #define RPTE_RPN_MASK 0x00FFFFFFFFFFF000ULL 139 #define RPTE_RPN_SHIFT 12 140 #define RPTE_SW1 0x0000000000000800ULL 141 #define RPTE_SW2 0x0000000000000400ULL 142 #define RPTE_SW3 0x0000000000000200ULL 143 #define RPTE_R 0x0000000000000100ULL 144 #define RPTE_C 0x0000000000000080ULL 145 146 #define RPTE_ATTR_MASK 0x0000000000000030ULL 147 #define RPTE_ATTR_MEM 0x0000000000000000ULL /* PTE M */ 148 #define RPTE_ATTR_SAO 0x0000000000000010ULL /* PTE WIM */ 149 #define RPTE_ATTR_GUARDEDIO 0x0000000000000020ULL /* PTE IMG */ 150 #define RPTE_ATTR_UNGUARDEDIO 0x0000000000000030ULL /* PTE IM */ 151 152 #define RPTE_EAA_MASK 0x000000000000000FULL 153 #define RPTE_EAA_P 0x0000000000000008ULL /* Supervisor only */ 154 #define RPTE_EAA_R 0x0000000000000004ULL /* Read allowed */ 155 #define RPTE_EAA_W 0x0000000000000002ULL /* Write (+read) */ 156 #define RPTE_EAA_X 0x0000000000000001ULL /* Execute allowed */ 157 158 #define RPDE_VALID RPTE_VALID 159 #define RPDE_LEAF RPTE_LEAF /* is a PTE: always 0 */ 160 #define RPDE_NLB_MASK 0x0FFFFFFFFFFFFF00ULL 161 #define RPDE_NLB_SHIFT 8 162 #define RPDE_NLS_MASK 0x000000000000001FULL 163 164 165 #ifndef LOCORE 166 typedef struct pte pte_t; 167 typedef struct lpte lpte_t; 168 #endif /* LOCORE */ 169 170 /* 171 * Extract bits from address 172 */ 173 #define ADDR_SR_SHFT 28 174 #define ADDR_PIDX 0x0ffff000UL 175 #define ADDR_PIDX_SHFT 12 176 #define ADDR_API_SHFT 22 177 #define ADDR_API_SHFT64 16 178 #define ADDR_POFF 0x00000fffUL 179 180 /* 181 * Bits in DSISR: 182 */ 183 #define DSISR_DIRECT 0x80000000 184 #define DSISR_NOTFOUND 0x40000000 185 #define DSISR_PROTECT 0x08000000 186 #define DSISR_INVRX 0x04000000 187 #define DSISR_STORE 0x02000000 188 #define DSISR_DABR 0x00400000 189 #define DSISR_SEGMENT 0x00200000 190 #define DSISR_EAR 0x00100000 191 192 /* 193 * Bits in SRR1 on ISI: 194 */ 195 #define ISSRR1_NOTFOUND 0x40000000 196 #define ISSRR1_DIRECT 0x10000000 197 #define ISSRR1_PROTECT 0x08000000 198 #define ISSRR1_SEGMENT 0x00200000 199 200 #else /* BOOKE */ 201 202 #include <machine/tlb.h> 203 204 #ifdef __powerpc64__ 205 206 #include <machine/tlb.h> 207 208 /* 209 * The virtual address is: 210 * 211 * 4K page size 212 * +-----+-----+-----+-------+-------------+-------------+----------------+ 213 * | - |p2d#h| - | p2d#l | dir# | pte# | off in 4K page | 214 * +-----+-----+-----+-------+-------------+-------------+----------------+ 215 * 63 62 61 60 59 40 39 30 29 ^ 21 20 ^ 12 11 0 216 * | | 217 * index in 1 page of pointers 218 * 219 * 1st level - pointers to page table directory (pp2d) 220 * 221 * pp2d consists of PP2D_NENTRIES entries, each being a pointer to 222 * second level entity, i.e. the page table directory (pdir). 223 */ 224 #define HARDWARE_WALKER 225 #define PP2D_H_H 61 226 #define PP2D_H_L 60 227 #define PP2D_L_H 39 228 #define PP2D_L_L 30 /* >30 would work with no page table pool */ 229 #ifndef LOCORE 230 #define PP2D_SIZE (1UL << PP2D_L_L) /* va range mapped by pp2d */ 231 #else 232 #define PP2D_SIZE (1 << PP2D_L_L) /* va range mapped by pp2d */ 233 #endif 234 #define PP2D_L_SHIFT PP2D_L_L 235 #define PP2D_L_NUM (PP2D_L_H-PP2D_L_L+1) 236 #define PP2D_L_MASK ((1<<PP2D_L_NUM)-1) 237 #define PP2D_H_SHIFT (PP2D_H_L-PP2D_L_NUM) 238 #define PP2D_H_NUM (PP2D_H_H-PP2D_H_L+1) 239 #define PP2D_H_MASK (((1<<PP2D_H_NUM)-1)<<PP2D_L_NUM) 240 #define PP2D_IDX(va) (((va >> PP2D_H_SHIFT) & PP2D_H_MASK) | ((va >> PP2D_L_SHIFT) & PP2D_L_MASK)) 241 #define PP2D_NENTRIES (1<<(PP2D_L_NUM+PP2D_H_NUM)) 242 #define PP2D_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */ 243 244 /* 245 * 2nd level - page table directory (pdir) 246 * 247 * pdir consists of PDIR_NENTRIES entries, each being a pointer to 248 * second level entity, i.e. the actual page table (ptbl). 249 */ 250 #define PDIR_H (PP2D_L_L-1) 251 #define PDIR_L 21 252 #define PDIR_NUM (PDIR_H-PDIR_L+1) 253 #define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */ 254 #define PDIR_MASK ((1<<PDIR_NUM)-1) 255 #define PDIR_SHIFT PDIR_L 256 #define PDIR_NENTRIES (1<<PDIR_NUM) 257 #define PDIR_IDX(va) (((va) >> PDIR_SHIFT) & PDIR_MASK) 258 #define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ 259 #define PDIR_PAGES ((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE) 260 261 /* 262 * 3rd level - page table (ptbl) 263 * 264 * Page table covers PTBL_NENTRIES page table entries. Page 265 * table entry (pte) is 64 bit wide and defines mapping 266 * for a single page. 267 */ 268 #define PTBL_H (PDIR_L-1) 269 #define PTBL_L PAGE_SHIFT 270 #define PTBL_NUM (PTBL_H-PTBL_L+1) 271 #define PTBL_MASK ((1<<PTBL_NUM)-1) 272 #define PTBL_SHIFT PTBL_L 273 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 274 #define PTBL_NENTRIES (1<<PTBL_NUM) 275 #define PTBL_IDX(va) ((va >> PTBL_SHIFT) & PTBL_MASK) 276 #define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */ 277 #define PTBL_PAGES ((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE) 278 279 #define KERNEL_LINEAR_MAX 0xc000000040000000 280 #else 281 /* 282 * 1st level - page table directory (pdir) 283 * 284 * pdir consists of 1024 entries, each being a pointer to 285 * second level entity, i.e. the actual page table (ptbl). 286 */ 287 #define PDIR_SHIFT 22 288 #define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */ 289 #define PDIR_MASK (~(PDIR_SIZE - 1)) 290 #define PDIR_NENTRIES 1024 /* number of page tables in pdir */ 291 292 /* Returns pdir entry number for given va */ 293 #define PDIR_IDX(va) ((va) >> PDIR_SHIFT) 294 295 #define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ 296 297 /* 298 * 2nd level - page table (ptbl) 299 * 300 * Page table covers 1024 page table entries. Page 301 * table entry (pte) is 32 bit wide and defines mapping 302 * for a single page. 303 */ 304 #define PTBL_SHIFT PAGE_SHIFT 305 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 306 #define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) 307 #define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ 308 309 /* Returns ptbl entry number for given va */ 310 #define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) 311 312 /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ 313 #define PTBL_PAGES 2 314 #define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ 315 316 #endif 317 318 /* 319 * Flags for pte_remove() routine. 320 */ 321 #define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ 322 #define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ 323 324 #define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) 325 326 /* 327 * Page Table Entry definitions and macros. 328 * 329 * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest 330 * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. 331 */ 332 #ifndef LOCORE 333 typedef uint64_t pte_t; 334 #endif 335 336 /* RPN mask, TLB0 4K pages */ 337 #define PTE_PA_MASK PAGE_MASK 338 339 #if defined(BOOKE_E500) 340 341 /* PTE bits assigned to MAS2, MAS3 flags */ 342 #define PTE_MAS2_SHIFT 19 343 #define PTE_W (MAS2_W << PTE_MAS2_SHIFT) 344 #define PTE_I (MAS2_I << PTE_MAS2_SHIFT) 345 #define PTE_M (MAS2_M << PTE_MAS2_SHIFT) 346 #define PTE_G (MAS2_G << PTE_MAS2_SHIFT) 347 #define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) 348 349 #define PTE_MAS3_SHIFT 2 350 #define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) 351 #define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) 352 #define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) 353 #define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) 354 #define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) 355 #define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) 356 #define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ 357 | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) 358 359 #define PTE_PS_SHIFT 8 360 #define PTE_PS_4KB (2 << PTE_PS_SHIFT) 361 362 #elif defined(BOOKE_PPC4XX) 363 364 #define PTE_WL1 TLB_WL1 365 #define PTE_IL2I TLB_IL2I 366 #define PTE_IL2D TLB_IL2D 367 368 #define PTE_W TLB_W 369 #define PTE_I TLB_I 370 #define PTE_M TLB_M 371 #define PTE_G TLB_G 372 373 #define PTE_UX TLB_UX 374 #define PTE_SX TLB_SX 375 #define PTE_UW TLB_UW 376 #define PTE_SW TLB_SW 377 #define PTE_UR TLB_UR 378 #define PTE_SR TLB_SR 379 380 #endif 381 382 /* Other PTE flags */ 383 #define PTE_VALID 0x00000001 /* Valid */ 384 #define PTE_MODIFIED 0x00001000 /* Modified */ 385 #define PTE_WIRED 0x00002000 /* Wired */ 386 #define PTE_MANAGED 0x00000002 /* Managed */ 387 #define PTE_REFERENCED 0x00040000 /* Referenced */ 388 389 /* 390 * Page Table Entry definitions and macros. 391 * 392 * We use the hardware page table entry format: 393 * 394 * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0 395 * --------------------------------------------------------------- 396 * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V 397 * --------------------------------------------------------------- 398 */ 399 400 /* PTE fields. */ 401 #define PTE_TSIZE_SHIFT (63-54) 402 #define PTE_TSIZE_MASK 0x7 403 #define PTE_TSIZE_SHIFT_DIRECT (63-55) 404 #define PTE_TSIZE_MASK_DIRECT 0xf 405 #define PTE_PS_DIRECT(ps) (ps<<PTE_TSIZE_SHIFT_DIRECT) /* Direct Entry Page Size */ 406 #define PTE_PS(ps) (ps<<PTE_TSIZE_SHIFT) /* Page Size */ 407 408 /* Macro argument must of pte_t type. */ 409 #define PTE_TSIZE(pte) (int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) 410 #define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) 411 412 /* Macro argument must of pte_t type. */ 413 #define PTE_ARPN_SHIFT 12 414 #define PTE_FLAGS_MASK 0x00ffffff 415 #define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) 416 #define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) 417 #define PTE_ISVALID(pte) ((*pte) & PTE_VALID) 418 #define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) 419 #define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) 420 #define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) 421 #define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) 422 423 #endif /* BOOKE */ 424 #endif /* _MACHINE_PTE_H_ */ 425