xref: /freebsd/sys/powerpc/include/pte.h (revision d93a896ef95946b0bf1219866fcb324b78543444)
1 /*-
2  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3  * Copyright (C) 1995, 1996 TooLs GmbH.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by TooLs GmbH.
17  * 4. The name of TooLs GmbH may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  *
31  *	$NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $
32  * $FreeBSD$
33  */
34 
35 #ifndef	_MACHINE_PTE_H_
36 #define	_MACHINE_PTE_H_
37 
38 #if defined(AIM)
39 
40 /*
41  * Page Table Entries
42  */
43 #ifndef	LOCORE
44 
45 /* 32-bit PTE */
46 struct pte {
47 	u_int32_t pte_hi;
48 	u_int32_t pte_lo;
49 };
50 
51 struct pteg {
52 	struct	pte pt[8];
53 };
54 
55 /* 64-bit (long) PTE */
56 struct lpte {
57 	u_int64_t pte_hi;
58 	u_int64_t pte_lo;
59 };
60 
61 struct lpteg {
62 	struct lpte pt[8];
63 };
64 
65 #endif	/* LOCORE */
66 
67 /* 32-bit PTE definitions */
68 
69 /* High word: */
70 #define	PTE_VALID	0x80000000
71 #define	PTE_VSID_SHFT	7
72 #define	PTE_HID		0x00000040
73 #define	PTE_API		0x0000003f
74 /* Low word: */
75 #define	PTE_RPGN	0xfffff000
76 #define	PTE_REF		0x00000100
77 #define	PTE_CHG		0x00000080
78 #define	PTE_WIMG	0x00000078
79 #define	PTE_W		0x00000040
80 #define	PTE_I		0x00000020
81 #define	PTE_M		0x00000010
82 #define	PTE_G		0x00000008
83 #define	PTE_PP		0x00000003
84 #define	PTE_SO		0x00000000	/* Super. Only       (U: XX, S: RW) */
85 #define PTE_SW		0x00000001	/* Super. Write-Only (U: RO, S: RW) */
86 #define	PTE_BW		0x00000002	/* Supervisor        (U: RW, S: RW) */
87 #define	PTE_BR		0x00000003	/* Both Read Only    (U: RO, S: RO) */
88 #define	PTE_RW		PTE_BW
89 #define	PTE_RO		PTE_BR
90 
91 #define	PTE_EXEC	0x00000200	/* pseudo bit in attrs; page is exec */
92 
93 /* 64-bit PTE definitions */
94 
95 /* High quadword: */
96 #define LPTE_VSID_SHIFT		12
97 #define LPTE_AVPN_MASK		0xFFFFFFFFFFFFFF80ULL
98 #define LPTE_API		0x0000000000000F80ULL
99 #define LPTE_SWBITS		0x0000000000000078ULL
100 #define LPTE_WIRED		0x0000000000000010ULL
101 #define LPTE_LOCKED		0x0000000000000008ULL
102 #define LPTE_BIG		0x0000000000000004ULL	/* 4kb/16Mb page */
103 #define LPTE_HID		0x0000000000000002ULL
104 #define LPTE_VALID		0x0000000000000001ULL
105 
106 /* Low quadword: */
107 #define EXTEND_PTE(x)	UINT64_C(x)	/* make constants 64-bit */
108 #define	LPTE_RPGN	0xfffffffffffff000ULL
109 #define	LPTE_REF	EXTEND_PTE( PTE_REF )
110 #define	LPTE_CHG	EXTEND_PTE( PTE_CHG )
111 #define	LPTE_WIMG	EXTEND_PTE( PTE_WIMG )
112 #define	LPTE_W		EXTEND_PTE( PTE_W )
113 #define	LPTE_I		EXTEND_PTE( PTE_I )
114 #define	LPTE_M		EXTEND_PTE( PTE_M )
115 #define	LPTE_G		EXTEND_PTE( PTE_G )
116 #define	LPTE_NOEXEC	0x0000000000000004ULL
117 #define	LPTE_PP		EXTEND_PTE( PTE_PP )
118 
119 #define	LPTE_SO		EXTEND_PTE( PTE_SO )	/* Super. Only */
120 #define	LPTE_SW		EXTEND_PTE( PTE_SW )	/* Super. Write-Only */
121 #define	LPTE_BW		EXTEND_PTE( PTE_BW )	/* Supervisor */
122 #define	LPTE_BR		EXTEND_PTE( PTE_BR )	/* Both Read Only */
123 #define	LPTE_RW		LPTE_BW
124 #define	LPTE_RO		LPTE_BR
125 
126 #ifndef	LOCORE
127 typedef	struct pte pte_t;
128 typedef	struct lpte lpte_t;
129 #endif	/* LOCORE */
130 
131 /*
132  * Extract bits from address
133  */
134 #define	ADDR_SR_SHFT	28
135 #define	ADDR_PIDX	0x0ffff000UL
136 #define	ADDR_PIDX_SHFT	12
137 #define	ADDR_API_SHFT	22
138 #define	ADDR_API_SHFT64	16
139 #define	ADDR_POFF	0x00000fffUL
140 
141 /*
142  * Bits in DSISR:
143  */
144 #define	DSISR_DIRECT	0x80000000
145 #define	DSISR_NOTFOUND	0x40000000
146 #define	DSISR_PROTECT	0x08000000
147 #define	DSISR_INVRX	0x04000000
148 #define	DSISR_STORE	0x02000000
149 #define	DSISR_DABR	0x00400000
150 #define	DSISR_SEGMENT	0x00200000
151 #define	DSISR_EAR	0x00100000
152 
153 /*
154  * Bits in SRR1 on ISI:
155  */
156 #define	ISSRR1_NOTFOUND	0x40000000
157 #define	ISSRR1_DIRECT	0x10000000
158 #define	ISSRR1_PROTECT	0x08000000
159 #define	ISSRR1_SEGMENT	0x00200000
160 
161 #else /* BOOKE */
162 
163 #include <machine/tlb.h>
164 
165 #ifdef __powerpc64__
166 
167 #include <machine/tlb.h>
168 
169 /*
170  * The virtual address is:
171  *
172  * 4K page size
173  *   +-----+-----+-----+-------+-------------+-------------+----------------+
174  *   |  -  |p2d#h|  -  | p2d#l |     dir#    |     pte#    | off in 4K page |
175  *   +-----+-----+-----+-------+-------------+-------------+----------------+
176  *    63 62 61 60 59 40 39   30 29    ^    21 20    ^    12 11             0
177  *                                    |             |
178  *                                index in 1 page of pointers
179  *
180  * 1st level - pointers to page table directory (pp2d)
181  *
182  * pp2d consists of PP2D_NENTRIES entries, each being a pointer to
183  * second level entity, i.e. the page table directory (pdir).
184  */
185 #define HARDWARE_WALKER
186 #define PP2D_H_H		61
187 #define PP2D_H_L		60
188 #define PP2D_L_H		39
189 #define PP2D_L_L		30	/* >30 would work with no page table pool */
190 #ifndef LOCORE
191 #define PP2D_SIZE		(1UL << PP2D_L_L)	/* va range mapped by pp2d */
192 #else
193 #define PP2D_SIZE		(1 << PP2D_L_L)	/* va range mapped by pp2d */
194 #endif
195 #define PP2D_L_SHIFT		PP2D_L_L
196 #define PP2D_L_NUM		(PP2D_L_H-PP2D_L_L+1)
197 #define PP2D_L_MASK		((1<<PP2D_L_NUM)-1)
198 #define PP2D_H_SHIFT		(PP2D_H_L-PP2D_L_NUM)
199 #define PP2D_H_NUM		(PP2D_H_H-PP2D_H_L+1)
200 #define PP2D_H_MASK		(((1<<PP2D_H_NUM)-1)<<PP2D_L_NUM)
201 #define PP2D_IDX(va)		(((va >> PP2D_H_SHIFT) & PP2D_H_MASK) | ((va >> PP2D_L_SHIFT) & PP2D_L_MASK))
202 #define PP2D_NENTRIES		(1<<(PP2D_L_NUM+PP2D_H_NUM))
203 #define PP2D_ENTRY_SHIFT	3	/* log2 (sizeof(struct pte_entry **)) */
204 
205 /*
206  * 2nd level - page table directory (pdir)
207  *
208  * pdir consists of PDIR_NENTRIES entries, each being a pointer to
209  * second level entity, i.e. the actual page table (ptbl).
210  */
211 #define PDIR_H			(PP2D_L_L-1)
212 #define PDIR_L			21
213 #define PDIR_NUM		(PDIR_H-PDIR_L+1)
214 #define PDIR_SIZE		(1 << PDIR_L)	/* va range mapped by pdir */
215 #define PDIR_MASK		((1<<PDIR_NUM)-1)
216 #define PDIR_SHIFT		PDIR_L
217 #define PDIR_NENTRIES		(1<<PDIR_NUM)
218 #define PDIR_IDX(va)		(((va) >> PDIR_SHIFT) & PDIR_MASK)
219 #define PDIR_ENTRY_SHIFT	3	/* log2 (sizeof(struct pte_entry *)) */
220 #define PDIR_PAGES		((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE)
221 
222 /*
223  * 3rd level - page table (ptbl)
224  *
225  * Page table covers PTBL_NENTRIES page table entries. Page
226  * table entry (pte) is 64 bit wide and defines mapping
227  * for a single page.
228  */
229 #define PTBL_H			(PDIR_L-1)
230 #define PTBL_L			PAGE_SHIFT
231 #define PTBL_NUM		(PTBL_H-PTBL_L+1)
232 #define PTBL_MASK		((1<<PTBL_NUM)-1)
233 #define PTBL_SHIFT		PTBL_L
234 #define PTBL_SIZE		PAGE_SIZE	/* va range mapped by ptbl entry */
235 #define PTBL_NENTRIES		(1<<PTBL_NUM)
236 #define PTBL_IDX(va)		((va >> PTBL_SHIFT) & PTBL_MASK)
237 #define PTBL_ENTRY_SHIFT	 3	/* log2 (sizeof (struct pte_entry)) */
238 #define PTBL_PAGES		((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE)
239 
240 #define KERNEL_LINEAR_MAX	0xc000000040000000
241 #else
242 /*
243  * 1st level - page table directory (pdir)
244  *
245  * pdir consists of 1024 entries, each being a pointer to
246  * second level entity, i.e. the actual page table (ptbl).
247  */
248 #define PDIR_SHIFT	22
249 #define PDIR_SIZE	(1 << PDIR_SHIFT)	/* va range mapped by pdir */
250 #define PDIR_MASK	(~(PDIR_SIZE - 1))
251 #define PDIR_NENTRIES	1024			/* number of page tables in pdir */
252 
253 /* Returns pdir entry number for given va */
254 #define PDIR_IDX(va)	((va) >> PDIR_SHIFT)
255 
256 #define PDIR_ENTRY_SHIFT 2	/* entry size is 2^2 = 4 bytes */
257 
258 /*
259  * 2nd level - page table (ptbl)
260  *
261  * Page table covers 1024 page table entries. Page
262  * table entry (pte) is 32 bit wide and defines mapping
263  * for a single page.
264  */
265 #define PTBL_SHIFT	PAGE_SHIFT
266 #define PTBL_SIZE	PAGE_SIZE		/* va range mapped by ptbl entry */
267 #define PTBL_MASK	((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1))
268 #define PTBL_NENTRIES	1024			/* number of pages mapped by ptbl */
269 
270 /* Returns ptbl entry number for given va */
271 #define PTBL_IDX(va)	(((va) & PTBL_MASK) >> PTBL_SHIFT)
272 
273 /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */
274 #define PTBL_PAGES	2
275 #define PTBL_ENTRY_SHIFT 3	/* entry size is 2^3 = 8 bytes */
276 
277 #endif
278 
279 /*
280  * Flags for pte_remove() routine.
281  */
282 #define PTBL_HOLD	0x00000001	/* do not unhold ptbl pages */
283 #define PTBL_UNHOLD	0x00000002	/* unhold and attempt to free ptbl pages */
284 
285 #define PTBL_HOLD_FLAG(pmap)	(((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD)
286 
287 /*
288  * Page Table Entry definitions and macros.
289  *
290  * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest
291  * page size is 4k (12-bit mask), so RPN can really fit into 24 bits.
292  */
293 #ifndef	LOCORE
294 typedef uint64_t pte_t;
295 #endif
296 
297 /* RPN mask, TLB0 4K pages */
298 #define PTE_PA_MASK	PAGE_MASK
299 
300 #if defined(BOOKE_E500)
301 
302 /* PTE bits assigned to MAS2, MAS3 flags */
303 #define	PTE_MAS2_SHIFT	19
304 #define PTE_W		(MAS2_W << PTE_MAS2_SHIFT)
305 #define PTE_I		(MAS2_I << PTE_MAS2_SHIFT)
306 #define PTE_M		(MAS2_M << PTE_MAS2_SHIFT)
307 #define PTE_G		(MAS2_G << PTE_MAS2_SHIFT)
308 #define PTE_MAS2_MASK	(MAS2_G | MAS2_M | MAS2_I | MAS2_W)
309 
310 #define PTE_MAS3_SHIFT	2
311 #define PTE_UX		(MAS3_UX << PTE_MAS3_SHIFT)
312 #define PTE_SX		(MAS3_SX << PTE_MAS3_SHIFT)
313 #define PTE_UW		(MAS3_UW << PTE_MAS3_SHIFT)
314 #define PTE_SW		(MAS3_SW << PTE_MAS3_SHIFT)
315 #define PTE_UR		(MAS3_UR << PTE_MAS3_SHIFT)
316 #define PTE_SR		(MAS3_SR << PTE_MAS3_SHIFT)
317 #define PTE_MAS3_MASK	((MAS3_UX | MAS3_SX | MAS3_UW	\
318 			| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
319 
320 #define	PTE_PS_SHIFT	8
321 #define	PTE_PS_4KB	(2 << PTE_PS_SHIFT)
322 
323 #elif defined(BOOKE_PPC4XX)
324 
325 #define PTE_WL1		TLB_WL1
326 #define PTE_IL2I	TLB_IL2I
327 #define PTE_IL2D	TLB_IL2D
328 
329 #define PTE_W		TLB_W
330 #define PTE_I		TLB_I
331 #define PTE_M		TLB_M
332 #define PTE_G		TLB_G
333 
334 #define PTE_UX		TLB_UX
335 #define PTE_SX		TLB_SX
336 #define PTE_UW		TLB_UW
337 #define PTE_SW		TLB_SW
338 #define PTE_UR		TLB_UR
339 #define PTE_SR		TLB_SR
340 
341 #endif
342 
343 /* Other PTE flags */
344 #define PTE_VALID	0x00000001	/* Valid */
345 #define PTE_MODIFIED	0x00001000	/* Modified */
346 #define PTE_WIRED	0x00002000	/* Wired */
347 #define PTE_MANAGED	0x00000002	/* Managed */
348 #define PTE_REFERENCED	0x00040000	/* Referenced */
349 
350 /*
351  * Page Table Entry definitions and macros.
352  *
353  * We use the hardware page table entry format:
354  *
355  * 63       24 23 19 18 17 14  13 12 11  8  7  6  5  4  3  2  1  0
356  * ---------------------------------------------------------------
357  * ARPN(12:51) WIMGE  R U0:U3 SW0 C  PSIZE UX SX UW SW UR SR SW1 V
358  * ---------------------------------------------------------------
359  */
360 
361 /* PTE fields. */
362 #define PTE_TSIZE_SHIFT		(63-54)
363 #define PTE_TSIZE_MASK		0x7
364 #define PTE_TSIZE_SHIFT_DIRECT	(63-55)
365 #define PTE_TSIZE_MASK_DIRECT	0xf
366 #define PTE_PS_DIRECT(ps)	(ps<<PTE_TSIZE_SHIFT_DIRECT)	/* Direct Entry Page Size */
367 #define PTE_PS(ps)		(ps<<PTE_TSIZE_SHIFT)	/* Page Size */
368 
369 /* Macro argument must of pte_t type. */
370 #define PTE_TSIZE(pte)		(int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK)
371 #define PTE_TSIZE_DIRECT(pte)	(int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT)
372 
373 /* Macro argument must of pte_t type. */
374 #define	PTE_ARPN_SHIFT		12
375 #define	PTE_FLAGS_MASK		0x00ffffff
376 #define PTE_RPN_FROM_PA(pa)	(((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT)
377 #define PTE_PA(pte)		((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK)
378 #define PTE_ISVALID(pte)	((*pte) & PTE_VALID)
379 #define PTE_ISWIRED(pte)	((*pte) & PTE_WIRED)
380 #define PTE_ISMANAGED(pte)	((*pte) & PTE_MANAGED)
381 #define PTE_ISMODIFIED(pte)	((*pte) & PTE_MODIFIED)
382 #define PTE_ISREFERENCED(pte)	((*pte) & PTE_REFERENCED)
383 
384 #endif /* BOOKE */
385 #endif /* _MACHINE_PTE_H_ */
386