1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_PTE_H_ 38 #define _MACHINE_PTE_H_ 39 40 #if defined(AIM) 41 42 /* 43 * Page Table Entries 44 */ 45 #ifndef LOCORE 46 47 /* 32-bit PTE */ 48 struct pte { 49 u_int32_t pte_hi; 50 u_int32_t pte_lo; 51 }; 52 53 struct pteg { 54 struct pte pt[8]; 55 }; 56 57 /* 64-bit (long) PTE */ 58 struct lpte { 59 u_int64_t pte_hi; 60 u_int64_t pte_lo; 61 }; 62 63 struct lpteg { 64 struct lpte pt[8]; 65 }; 66 67 #endif /* LOCORE */ 68 69 /* 32-bit PTE definitions */ 70 71 /* High word: */ 72 #define PTE_VALID 0x80000000 73 #define PTE_VSID_SHFT 7 74 #define PTE_HID 0x00000040 75 #define PTE_API 0x0000003f 76 /* Low word: */ 77 #define PTE_RPGN 0xfffff000 78 #define PTE_REF 0x00000100 79 #define PTE_CHG 0x00000080 80 #define PTE_WIMG 0x00000078 81 #define PTE_W 0x00000040 82 #define PTE_I 0x00000020 83 #define PTE_M 0x00000010 84 #define PTE_G 0x00000008 85 #define PTE_PP 0x00000003 86 #define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ 87 #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ 88 #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ 89 #define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ 90 #define PTE_RW PTE_BW 91 #define PTE_RO PTE_BR 92 93 #define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ 94 95 /* 64-bit PTE definitions */ 96 97 /* High quadword: */ 98 #define LPTE_VSID_SHIFT 12 99 #define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL 100 #define LPTE_API 0x0000000000000F80ULL 101 #define LPTE_SWBITS 0x0000000000000078ULL 102 #define LPTE_WIRED 0x0000000000000010ULL 103 #define LPTE_LOCKED 0x0000000000000008ULL 104 #define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ 105 #define LPTE_HID 0x0000000000000002ULL 106 #define LPTE_VALID 0x0000000000000001ULL 107 108 /* Low quadword: */ 109 #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ 110 #define LPTE_RPGN 0xfffffffffffff000ULL 111 #define LPTE_REF EXTEND_PTE( PTE_REF ) 112 #define LPTE_CHG EXTEND_PTE( PTE_CHG ) 113 #define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) 114 #define LPTE_W EXTEND_PTE( PTE_W ) 115 #define LPTE_I EXTEND_PTE( PTE_I ) 116 #define LPTE_M EXTEND_PTE( PTE_M ) 117 #define LPTE_G EXTEND_PTE( PTE_G ) 118 #define LPTE_NOEXEC 0x0000000000000004ULL 119 #define LPTE_PP EXTEND_PTE( PTE_PP ) 120 121 #define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ 122 #define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ 123 #define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ 124 #define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ 125 #define LPTE_RW LPTE_BW 126 #define LPTE_RO LPTE_BR 127 128 #ifndef LOCORE 129 typedef struct pte pte_t; 130 typedef struct lpte lpte_t; 131 #endif /* LOCORE */ 132 133 /* 134 * Extract bits from address 135 */ 136 #define ADDR_SR_SHFT 28 137 #define ADDR_PIDX 0x0ffff000UL 138 #define ADDR_PIDX_SHFT 12 139 #define ADDR_API_SHFT 22 140 #define ADDR_API_SHFT64 16 141 #define ADDR_POFF 0x00000fffUL 142 143 /* 144 * Bits in DSISR: 145 */ 146 #define DSISR_DIRECT 0x80000000 147 #define DSISR_NOTFOUND 0x40000000 148 #define DSISR_PROTECT 0x08000000 149 #define DSISR_INVRX 0x04000000 150 #define DSISR_STORE 0x02000000 151 #define DSISR_DABR 0x00400000 152 #define DSISR_SEGMENT 0x00200000 153 #define DSISR_EAR 0x00100000 154 155 /* 156 * Bits in SRR1 on ISI: 157 */ 158 #define ISSRR1_NOTFOUND 0x40000000 159 #define ISSRR1_DIRECT 0x10000000 160 #define ISSRR1_PROTECT 0x08000000 161 #define ISSRR1_SEGMENT 0x00200000 162 163 #else /* BOOKE */ 164 165 #include <machine/tlb.h> 166 167 #ifdef __powerpc64__ 168 169 #include <machine/tlb.h> 170 171 /* 172 * The virtual address is: 173 * 174 * 4K page size 175 * +-----+-----+-----+-------+-------------+-------------+----------------+ 176 * | - |p2d#h| - | p2d#l | dir# | pte# | off in 4K page | 177 * +-----+-----+-----+-------+-------------+-------------+----------------+ 178 * 63 62 61 60 59 40 39 30 29 ^ 21 20 ^ 12 11 0 179 * | | 180 * index in 1 page of pointers 181 * 182 * 1st level - pointers to page table directory (pp2d) 183 * 184 * pp2d consists of PP2D_NENTRIES entries, each being a pointer to 185 * second level entity, i.e. the page table directory (pdir). 186 */ 187 #define HARDWARE_WALKER 188 #define PP2D_H_H 61 189 #define PP2D_H_L 60 190 #define PP2D_L_H 39 191 #define PP2D_L_L 30 /* >30 would work with no page table pool */ 192 #ifndef LOCORE 193 #define PP2D_SIZE (1UL << PP2D_L_L) /* va range mapped by pp2d */ 194 #else 195 #define PP2D_SIZE (1 << PP2D_L_L) /* va range mapped by pp2d */ 196 #endif 197 #define PP2D_L_SHIFT PP2D_L_L 198 #define PP2D_L_NUM (PP2D_L_H-PP2D_L_L+1) 199 #define PP2D_L_MASK ((1<<PP2D_L_NUM)-1) 200 #define PP2D_H_SHIFT (PP2D_H_L-PP2D_L_NUM) 201 #define PP2D_H_NUM (PP2D_H_H-PP2D_H_L+1) 202 #define PP2D_H_MASK (((1<<PP2D_H_NUM)-1)<<PP2D_L_NUM) 203 #define PP2D_IDX(va) (((va >> PP2D_H_SHIFT) & PP2D_H_MASK) | ((va >> PP2D_L_SHIFT) & PP2D_L_MASK)) 204 #define PP2D_NENTRIES (1<<(PP2D_L_NUM+PP2D_H_NUM)) 205 #define PP2D_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */ 206 207 /* 208 * 2nd level - page table directory (pdir) 209 * 210 * pdir consists of PDIR_NENTRIES entries, each being a pointer to 211 * second level entity, i.e. the actual page table (ptbl). 212 */ 213 #define PDIR_H (PP2D_L_L-1) 214 #define PDIR_L 21 215 #define PDIR_NUM (PDIR_H-PDIR_L+1) 216 #define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */ 217 #define PDIR_MASK ((1<<PDIR_NUM)-1) 218 #define PDIR_SHIFT PDIR_L 219 #define PDIR_NENTRIES (1<<PDIR_NUM) 220 #define PDIR_IDX(va) (((va) >> PDIR_SHIFT) & PDIR_MASK) 221 #define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ 222 #define PDIR_PAGES ((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE) 223 224 /* 225 * 3rd level - page table (ptbl) 226 * 227 * Page table covers PTBL_NENTRIES page table entries. Page 228 * table entry (pte) is 64 bit wide and defines mapping 229 * for a single page. 230 */ 231 #define PTBL_H (PDIR_L-1) 232 #define PTBL_L PAGE_SHIFT 233 #define PTBL_NUM (PTBL_H-PTBL_L+1) 234 #define PTBL_MASK ((1<<PTBL_NUM)-1) 235 #define PTBL_SHIFT PTBL_L 236 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 237 #define PTBL_NENTRIES (1<<PTBL_NUM) 238 #define PTBL_IDX(va) ((va >> PTBL_SHIFT) & PTBL_MASK) 239 #define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */ 240 #define PTBL_PAGES ((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE) 241 242 #define KERNEL_LINEAR_MAX 0xc000000040000000 243 #else 244 /* 245 * 1st level - page table directory (pdir) 246 * 247 * pdir consists of 1024 entries, each being a pointer to 248 * second level entity, i.e. the actual page table (ptbl). 249 */ 250 #define PDIR_SHIFT 22 251 #define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */ 252 #define PDIR_MASK (~(PDIR_SIZE - 1)) 253 #define PDIR_NENTRIES 1024 /* number of page tables in pdir */ 254 255 /* Returns pdir entry number for given va */ 256 #define PDIR_IDX(va) ((va) >> PDIR_SHIFT) 257 258 #define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ 259 260 /* 261 * 2nd level - page table (ptbl) 262 * 263 * Page table covers 1024 page table entries. Page 264 * table entry (pte) is 32 bit wide and defines mapping 265 * for a single page. 266 */ 267 #define PTBL_SHIFT PAGE_SHIFT 268 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 269 #define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) 270 #define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ 271 272 /* Returns ptbl entry number for given va */ 273 #define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) 274 275 /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ 276 #define PTBL_PAGES 2 277 #define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ 278 279 #endif 280 281 /* 282 * Flags for pte_remove() routine. 283 */ 284 #define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ 285 #define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ 286 287 #define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) 288 289 /* 290 * Page Table Entry definitions and macros. 291 * 292 * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest 293 * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. 294 */ 295 #ifndef LOCORE 296 typedef uint64_t pte_t; 297 #endif 298 299 /* RPN mask, TLB0 4K pages */ 300 #define PTE_PA_MASK PAGE_MASK 301 302 #if defined(BOOKE_E500) 303 304 /* PTE bits assigned to MAS2, MAS3 flags */ 305 #define PTE_MAS2_SHIFT 19 306 #define PTE_W (MAS2_W << PTE_MAS2_SHIFT) 307 #define PTE_I (MAS2_I << PTE_MAS2_SHIFT) 308 #define PTE_M (MAS2_M << PTE_MAS2_SHIFT) 309 #define PTE_G (MAS2_G << PTE_MAS2_SHIFT) 310 #define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) 311 312 #define PTE_MAS3_SHIFT 2 313 #define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) 314 #define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) 315 #define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) 316 #define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) 317 #define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) 318 #define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) 319 #define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ 320 | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) 321 322 #define PTE_PS_SHIFT 8 323 #define PTE_PS_4KB (2 << PTE_PS_SHIFT) 324 325 #elif defined(BOOKE_PPC4XX) 326 327 #define PTE_WL1 TLB_WL1 328 #define PTE_IL2I TLB_IL2I 329 #define PTE_IL2D TLB_IL2D 330 331 #define PTE_W TLB_W 332 #define PTE_I TLB_I 333 #define PTE_M TLB_M 334 #define PTE_G TLB_G 335 336 #define PTE_UX TLB_UX 337 #define PTE_SX TLB_SX 338 #define PTE_UW TLB_UW 339 #define PTE_SW TLB_SW 340 #define PTE_UR TLB_UR 341 #define PTE_SR TLB_SR 342 343 #endif 344 345 /* Other PTE flags */ 346 #define PTE_VALID 0x00000001 /* Valid */ 347 #define PTE_MODIFIED 0x00001000 /* Modified */ 348 #define PTE_WIRED 0x00002000 /* Wired */ 349 #define PTE_MANAGED 0x00000002 /* Managed */ 350 #define PTE_REFERENCED 0x00040000 /* Referenced */ 351 352 /* 353 * Page Table Entry definitions and macros. 354 * 355 * We use the hardware page table entry format: 356 * 357 * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0 358 * --------------------------------------------------------------- 359 * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V 360 * --------------------------------------------------------------- 361 */ 362 363 /* PTE fields. */ 364 #define PTE_TSIZE_SHIFT (63-54) 365 #define PTE_TSIZE_MASK 0x7 366 #define PTE_TSIZE_SHIFT_DIRECT (63-55) 367 #define PTE_TSIZE_MASK_DIRECT 0xf 368 #define PTE_PS_DIRECT(ps) (ps<<PTE_TSIZE_SHIFT_DIRECT) /* Direct Entry Page Size */ 369 #define PTE_PS(ps) (ps<<PTE_TSIZE_SHIFT) /* Page Size */ 370 371 /* Macro argument must of pte_t type. */ 372 #define PTE_TSIZE(pte) (int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) 373 #define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) 374 375 /* Macro argument must of pte_t type. */ 376 #define PTE_ARPN_SHIFT 12 377 #define PTE_FLAGS_MASK 0x00ffffff 378 #define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) 379 #define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) 380 #define PTE_ISVALID(pte) ((*pte) & PTE_VALID) 381 #define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) 382 #define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) 383 #define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) 384 #define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) 385 386 #endif /* BOOKE */ 387 #endif /* _MACHINE_PTE_H_ */ 388