1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_PTE_H_ 38 #define _MACHINE_PTE_H_ 39 40 #if defined(AIM) 41 42 /* 43 * Page Table Entries 44 */ 45 #ifndef LOCORE 46 47 /* 32-bit PTE */ 48 struct pte { 49 u_int32_t pte_hi; 50 u_int32_t pte_lo; 51 }; 52 53 struct pteg { 54 struct pte pt[8]; 55 }; 56 57 /* 64-bit (long) PTE */ 58 struct lpte { 59 u_int64_t pte_hi; 60 u_int64_t pte_lo; 61 }; 62 63 struct lpteg { 64 struct lpte pt[8]; 65 }; 66 67 /* Partition table entry */ 68 struct pate { 69 u_int64_t pagetab; 70 u_int64_t proctab; 71 }; 72 73 /* Process table entry */ 74 struct prte { 75 u_int64_t proctab0; 76 u_int64_t proctab1; 77 }; 78 79 typedef struct pte pte_t; 80 typedef struct lpte lpte_t; 81 #endif /* LOCORE */ 82 83 /* 32-bit PTE definitions */ 84 85 /* High word: */ 86 #define PTE_VALID 0x80000000 87 #define PTE_VSID_SHFT 7 88 #define PTE_HID 0x00000040 89 #define PTE_API 0x0000003f 90 /* Low word: */ 91 #define PTE_RPGN 0xfffff000 92 #define PTE_REF 0x00000100 93 #define PTE_CHG 0x00000080 94 #define PTE_WIMG 0x00000078 95 #define PTE_W 0x00000040 96 #define PTE_I 0x00000020 97 #define PTE_M 0x00000010 98 #define PTE_G 0x00000008 99 #define PTE_PP 0x00000003 100 #define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ 101 #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ 102 #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ 103 #define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ 104 #define PTE_RW PTE_BW 105 #define PTE_RO PTE_BR 106 107 #define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ 108 109 /* 64-bit PTE definitions */ 110 111 /* High quadword: */ 112 #define LPTE_VSID_SHIFT 12 113 #define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL 114 #define LPTE_API 0x0000000000000F80ULL 115 #define LPTE_SWBITS 0x0000000000000078ULL 116 #define LPTE_WIRED 0x0000000000000010ULL 117 #define LPTE_LOCKED 0x0000000000000008ULL 118 #define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ 119 #define LPTE_HID 0x0000000000000002ULL 120 #define LPTE_VALID 0x0000000000000001ULL 121 122 /* Low quadword: */ 123 #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ 124 #define LPTE_RPGN 0xfffffffffffff000ULL 125 #define LPTE_REF EXTEND_PTE( PTE_REF ) 126 #define LPTE_CHG EXTEND_PTE( PTE_CHG ) 127 #define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) 128 #define LPTE_W EXTEND_PTE( PTE_W ) 129 #define LPTE_I EXTEND_PTE( PTE_I ) 130 #define LPTE_M EXTEND_PTE( PTE_M ) 131 #define LPTE_G EXTEND_PTE( PTE_G ) 132 #define LPTE_NOEXEC 0x0000000000000004ULL 133 #define LPTE_PP EXTEND_PTE( PTE_PP ) 134 135 #define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ 136 #define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ 137 #define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ 138 #define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ 139 #define LPTE_RW LPTE_BW 140 #define LPTE_RO LPTE_BR 141 142 /* POWER ISA 3.0 Radix Table Definitions */ 143 #define RPTE_VALID 0x8000000000000000ULL 144 #define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */ 145 #define RPTE_SW0 0x2000000000000000ULL 146 #define RPTE_RPN_MASK 0x00FFFFFFFFFFF000ULL 147 #define RPTE_RPN_SHIFT 12 148 #define RPTE_SW1 0x0000000000000800ULL 149 #define RPTE_SW2 0x0000000000000400ULL 150 #define RPTE_SW3 0x0000000000000200ULL 151 #define RPTE_R 0x0000000000000100ULL 152 #define RPTE_C 0x0000000000000080ULL 153 154 #define RPTE_MANAGED RPTE_SW1 155 #define RPTE_WIRED RPTE_SW2 156 #define RPTE_PROMOTED RPTE_SW3 157 158 #define RPTE_ATTR_MASK 0x0000000000000030ULL 159 #define RPTE_ATTR_MEM 0x0000000000000000ULL /* PTE M */ 160 #define RPTE_ATTR_SAO 0x0000000000000010ULL /* PTE WIM */ 161 #define RPTE_ATTR_GUARDEDIO 0x0000000000000020ULL /* PTE IMG */ 162 #define RPTE_ATTR_UNGUARDEDIO 0x0000000000000030ULL /* PTE IM */ 163 164 #define RPTE_EAA_MASK 0x000000000000000FULL 165 #define RPTE_EAA_P 0x0000000000000008ULL /* Supervisor only */ 166 #define RPTE_EAA_R 0x0000000000000004ULL /* Read allowed */ 167 #define RPTE_EAA_W 0x0000000000000002ULL /* Write (+read) */ 168 #define RPTE_EAA_X 0x0000000000000001ULL /* Execute allowed */ 169 170 #define RPDE_VALID RPTE_VALID 171 #define RPDE_LEAF RPTE_LEAF /* is a PTE: always 0 */ 172 #define RPDE_NLB_MASK 0x00FFFFFFFFFFFF00ULL 173 #define RPDE_NLB_SHIFT 8 174 #define RPDE_NLS_MASK 0x000000000000001FULL 175 176 #define PG_FRAME (0x000ffffffffff000ul) 177 #define PG_PS_FRAME (0x000fffffffe00000ul) 178 /* 179 * Extract bits from address 180 */ 181 #define ADDR_SR_SHFT 28 182 #define ADDR_PIDX 0x0ffff000UL 183 #define ADDR_PIDX_SHFT 12 184 #define ADDR_API_SHFT 22 185 #define ADDR_API_SHFT64 16 186 #define ADDR_POFF 0x00000fffUL 187 188 /* 189 * Bits in DSISR: 190 */ 191 #define DSISR_DIRECT 0x80000000 192 #define DSISR_NOTFOUND 0x40000000 193 #define DSISR_PROTECT 0x08000000 194 #define DSISR_INVRX 0x04000000 195 #define DSISR_STORE 0x02000000 196 #define DSISR_DABR 0x00400000 197 #define DSISR_SEGMENT 0x00200000 198 #define DSISR_EAR 0x00100000 199 200 /* 201 * Bits in SRR1 on ISI: 202 */ 203 #define ISSRR1_NOTFOUND 0x40000000 204 #define ISSRR1_DIRECT 0x10000000 205 #define ISSRR1_PROTECT 0x08000000 206 #define ISSRR1_SEGMENT 0x00200000 207 208 #else /* BOOKE */ 209 210 #include <machine/tlb.h> 211 212 /* 213 * Flags for pte_remove() routine. 214 */ 215 #define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ 216 #define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ 217 218 #define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) 219 220 /* 221 * Page Table Entry definitions and macros. 222 * 223 * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest 224 * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. 225 */ 226 #ifndef LOCORE 227 typedef uint64_t pte_t; 228 #endif 229 230 /* RPN mask, TLB0 4K pages */ 231 #define PTE_PA_MASK PAGE_MASK 232 233 #if defined(BOOKE_E500) 234 235 /* PTE bits assigned to MAS2, MAS3 flags */ 236 #define PTE_MAS2_SHIFT 19 237 #define PTE_W (MAS2_W << PTE_MAS2_SHIFT) 238 #define PTE_I (MAS2_I << PTE_MAS2_SHIFT) 239 #define PTE_M (MAS2_M << PTE_MAS2_SHIFT) 240 #define PTE_G (MAS2_G << PTE_MAS2_SHIFT) 241 #define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) 242 243 #define PTE_MAS3_SHIFT 2 244 #define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) 245 #define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) 246 #define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) 247 #define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) 248 #define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) 249 #define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) 250 #define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ 251 | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) 252 253 #define PTE_PS_SHIFT 8 254 #define PTE_PS_4KB (2 << PTE_PS_SHIFT) 255 256 #endif 257 258 /* Other PTE flags */ 259 #define PTE_VALID 0x00000001 /* Valid */ 260 #define PTE_MODIFIED 0x00001000 /* Modified */ 261 #define PTE_WIRED 0x00002000 /* Wired */ 262 #define PTE_MANAGED 0x00000002 /* Managed */ 263 #define PTE_REFERENCED 0x00040000 /* Referenced */ 264 265 /* 266 * Page Table Entry definitions and macros. 267 * 268 * We use the hardware page table entry format: 269 * 270 * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0 271 * --------------------------------------------------------------- 272 * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V 273 * --------------------------------------------------------------- 274 */ 275 276 /* PTE fields. */ 277 #define PTE_TSIZE_SHIFT (63-54) 278 #define PTE_TSIZE_MASK 0x7 279 #define PTE_TSIZE_SHIFT_DIRECT (63-55) 280 #define PTE_TSIZE_MASK_DIRECT 0xf 281 #define PTE_PS_DIRECT(ps) (ps<<PTE_TSIZE_SHIFT_DIRECT) /* Direct Entry Page Size */ 282 #define PTE_PS(ps) (ps<<PTE_TSIZE_SHIFT) /* Page Size */ 283 284 /* Macro argument must of pte_t type. */ 285 #define PTE_TSIZE(pte) (int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) 286 #define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) 287 288 /* Macro argument must of pte_t type. */ 289 #define PTE_ARPN_SHIFT 12 290 #define PTE_FLAGS_MASK 0x00ffffff 291 #define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) 292 #define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) 293 #define PTE_ISVALID(pte) ((*pte) & PTE_VALID) 294 #define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) 295 #define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) 296 #define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) 297 #define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) 298 299 #endif /* BOOKE */ 300 301 /* Book-E page table format, broken out for the generic pmap.h. */ 302 #ifdef __powerpc64__ 303 304 #include <machine/tlb.h> 305 306 /* 307 * The virtual address is: 308 * 309 * 4K page size 310 * +-----+-----------+-------+-------------+-------------+----------------+ 311 * | - | pg_root |pdir_l1| dir# | pte# | off in 4K page | 312 * +-----+-----------+-------+-------------+-------------+----------------+ 313 * 63 52 51 39 38 30 29 ^ 21 20 ^ 12 11 0 314 * | | 315 * index in 1 page of pointers 316 * 317 * 1st level - Root page table 318 * 319 * pp2d consists of PG_ROOT_NENTRIES entries, each being a pointer to 320 * second level entity, i.e. the page table directory (pdir). 321 */ 322 #define PG_ROOT_H 51 323 #define PG_ROOT_L 39 324 #define PG_ROOT_SIZE (1UL << PG_ROOT_L) /* va range mapped by pp2d */ 325 #define PG_ROOT_SHIFT PG_ROOT_L 326 #define PG_ROOT_NUM (PG_ROOT_H - PG_ROOT_L + 1) 327 #define PG_ROOT_MASK ((1 << PG_ROOT_NUM) - 1) 328 #define PG_ROOT_IDX(va) ((va >> PG_ROOT_SHIFT) & PG_ROOT_MASK) 329 #define PG_ROOT_NENTRIES (1 << PG_ROOT_NUM) 330 #define PG_ROOT_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */ 331 332 /* 333 * 2nd level - page directory directory (pdir l1) 334 * 335 * pdir consists of PDIR_NENTRIES entries, each being a pointer to 336 * second level entity, i.e. the actual page table (ptbl). 337 */ 338 #define PDIR_L1_H (PG_ROOT_L-1) 339 #define PDIR_L1_L 30 340 #define PDIR_L1_NUM (PDIR_L1_H-PDIR_L1_L+1) 341 #define PDIR_L1_SIZE (1 << PDIR_L1_L) /* va range mapped by pdir */ 342 #define PDIR_L1_MASK ((1<<PDIR_L1_NUM)-1) 343 #define PDIR_L1_SHIFT PDIR_L1_L 344 #define PDIR_L1_NENTRIES (1<<PDIR_L1_NUM) 345 #define PDIR_L1_IDX(va) (((va) >> PDIR_L1_SHIFT) & PDIR_L1_MASK) 346 #define PDIR_L1_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ 347 #define PDIR_L1_PAGES ((PDIR_L1_NENTRIES * (1<<PDIR_L1_ENTRY_SHIFT)) / PAGE_SIZE) 348 349 /* 350 * 3rd level - page table directory (pdir) 351 * 352 * pdir consists of PDIR_NENTRIES entries, each being a pointer to 353 * second level entity, i.e. the actual page table (ptbl). 354 */ 355 #define PDIR_H (PDIR_L1_L-1) 356 #define PDIR_L 21 357 #define PDIR_NUM (PDIR_H-PDIR_L+1) 358 #define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */ 359 #define PDIR_MASK ((1<<PDIR_NUM)-1) 360 #define PDIR_SHIFT PDIR_L 361 #define PDIR_NENTRIES (1<<PDIR_NUM) 362 #define PDIR_IDX(va) (((va) >> PDIR_SHIFT) & PDIR_MASK) 363 #define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ 364 #define PDIR_PAGES ((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE) 365 366 /* 367 * 4th level - page table (ptbl) 368 * 369 * Page table covers PTBL_NENTRIES page table entries. Page 370 * table entry (pte) is 64 bit wide and defines mapping 371 * for a single page. 372 */ 373 #define PTBL_H (PDIR_L-1) 374 #define PTBL_L PAGE_SHIFT 375 #define PTBL_NUM (PTBL_H-PTBL_L+1) 376 #define PTBL_MASK ((1<<PTBL_NUM)-1) 377 #define PTBL_SHIFT PTBL_L 378 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 379 #define PTBL_NENTRIES (1<<PTBL_NUM) 380 #define PTBL_IDX(va) ((va >> PTBL_SHIFT) & PTBL_MASK) 381 #define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */ 382 #define PTBL_PAGES ((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE) 383 384 #else 385 /* 386 * 1st level - page table directory (pdir) 387 * 388 * pdir consists of 1024 entries, each being a pointer to 389 * second level entity, i.e. the actual page table (ptbl). 390 */ 391 #define PDIR_SHIFT 22 392 #define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */ 393 #define PDIR_MASK (~(PDIR_SIZE - 1)) 394 #define PDIR_NENTRIES 1024 /* number of page tables in pdir */ 395 396 /* Returns pdir entry number for given va */ 397 #define PDIR_IDX(va) ((va) >> PDIR_SHIFT) 398 399 #define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ 400 401 /* 402 * 2nd level - page table (ptbl) 403 * 404 * Page table covers 1024 page table entries. Page 405 * table entry (pte) is 32 bit wide and defines mapping 406 * for a single page. 407 */ 408 #define PTBL_SHIFT PAGE_SHIFT 409 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 410 #define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) 411 #define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ 412 413 /* Returns ptbl entry number for given va */ 414 #define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) 415 416 /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ 417 #define PTBL_PAGES 2 418 #define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ 419 420 #endif 421 #endif /* _MACHINE_PTE_H_ */ 422