1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 5 * Copyright (C) 1995, 1996 TooLs GmbH. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by TooLs GmbH. 19 * 4. The name of TooLs GmbH may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_PTE_H_ 38 #define _MACHINE_PTE_H_ 39 40 #if defined(AIM) 41 42 /* 43 * Page Table Entries 44 */ 45 #ifndef LOCORE 46 47 /* 32-bit PTE */ 48 struct pte { 49 u_int32_t pte_hi; 50 u_int32_t pte_lo; 51 }; 52 53 struct pteg { 54 struct pte pt[8]; 55 }; 56 57 /* 64-bit (long) PTE */ 58 struct lpte { 59 u_int64_t pte_hi; 60 u_int64_t pte_lo; 61 }; 62 63 struct lpteg { 64 struct lpte pt[8]; 65 }; 66 67 #endif /* LOCORE */ 68 69 /* 32-bit PTE definitions */ 70 71 /* High word: */ 72 #define PTE_VALID 0x80000000 73 #define PTE_VSID_SHFT 7 74 #define PTE_HID 0x00000040 75 #define PTE_API 0x0000003f 76 /* Low word: */ 77 #define PTE_RPGN 0xfffff000 78 #define PTE_REF 0x00000100 79 #define PTE_CHG 0x00000080 80 #define PTE_WIMG 0x00000078 81 #define PTE_W 0x00000040 82 #define PTE_I 0x00000020 83 #define PTE_M 0x00000010 84 #define PTE_G 0x00000008 85 #define PTE_PP 0x00000003 86 #define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ 87 #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ 88 #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ 89 #define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ 90 #define PTE_RW PTE_BW 91 #define PTE_RO PTE_BR 92 93 #define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ 94 95 /* 64-bit PTE definitions */ 96 97 /* High quadword: */ 98 #define LPTE_VSID_SHIFT 12 99 #define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL 100 #define LPTE_API 0x0000000000000F80ULL 101 #define LPTE_SWBITS 0x0000000000000078ULL 102 #define LPTE_WIRED 0x0000000000000010ULL 103 #define LPTE_LOCKED 0x0000000000000008ULL 104 #define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ 105 #define LPTE_HID 0x0000000000000002ULL 106 #define LPTE_VALID 0x0000000000000001ULL 107 108 /* Low quadword: */ 109 #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ 110 #define LPTE_RPGN 0xfffffffffffff000ULL 111 #define LPTE_REF EXTEND_PTE( PTE_REF ) 112 #define LPTE_CHG EXTEND_PTE( PTE_CHG ) 113 #define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) 114 #define LPTE_W EXTEND_PTE( PTE_W ) 115 #define LPTE_I EXTEND_PTE( PTE_I ) 116 #define LPTE_M EXTEND_PTE( PTE_M ) 117 #define LPTE_G EXTEND_PTE( PTE_G ) 118 #define LPTE_NOEXEC 0x0000000000000004ULL 119 #define LPTE_PP EXTEND_PTE( PTE_PP ) 120 121 #define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ 122 #define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ 123 #define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ 124 #define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ 125 #define LPTE_RW LPTE_BW 126 #define LPTE_RO LPTE_BR 127 128 /* POWER ISA 3.0 Radix Table Definitions */ 129 #define RPTE_VALID 0x8000000000000000ULL 130 #define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */ 131 #define RPTE_SW0 0x2000000000000000ULL 132 #define RPTE_RPN_MASK 0x00FFFFFFFFFFF000ULL 133 #define RPTE_RPN_SHIFT 12 134 #define RPTE_SW1 0x0000000000000800ULL 135 #define RPTE_SW2 0x0000000000000400ULL 136 #define RPTE_SW3 0x0000000000000200ULL 137 #define RPTE_R 0x0000000000000100ULL 138 #define RPTE_C 0x0000000000000080ULL 139 140 #define RPTE_ATTR_MASK 0x0000000000000030ULL 141 #define RPTE_ATTR_MEM 0x0000000000000000ULL /* PTE M */ 142 #define RPTE_ATTR_SAO 0x0000000000000010ULL /* PTE WIM */ 143 #define RPTE_ATTR_GUARDEDIO 0x0000000000000020ULL /* PTE IMG */ 144 #define RPTE_ATTR_UNGUARDEDIO 0x0000000000000030ULL /* PTE IM */ 145 146 #define RPTE_EAA_MASK 0x000000000000000FULL 147 #define RPTE_EAA_P 0x0000000000000008ULL /* Supervisor only */ 148 #define RPTE_EAA_R 0x0000000000000004ULL /* Read allowed */ 149 #define RPTE_EAA_W 0x0000000000000002ULL /* Write (+read) */ 150 #define RPTE_EAA_X 0x0000000000000001ULL /* Execute allowed */ 151 152 #define RPDE_VALID RPTE_VALID 153 #define RPDE_LEAF RPTE_LEAF /* is a PTE: always 0 */ 154 #define RPDE_NLB_MASK 0x0FFFFFFFFFFFFF00ULL 155 #define RPDE_NLB_SHIFT 8 156 #define RPDE_NLS_MASK 0x000000000000001FULL 157 158 159 #ifndef LOCORE 160 typedef struct pte pte_t; 161 typedef struct lpte lpte_t; 162 #endif /* LOCORE */ 163 164 /* 165 * Extract bits from address 166 */ 167 #define ADDR_SR_SHFT 28 168 #define ADDR_PIDX 0x0ffff000UL 169 #define ADDR_PIDX_SHFT 12 170 #define ADDR_API_SHFT 22 171 #define ADDR_API_SHFT64 16 172 #define ADDR_POFF 0x00000fffUL 173 174 /* 175 * Bits in DSISR: 176 */ 177 #define DSISR_DIRECT 0x80000000 178 #define DSISR_NOTFOUND 0x40000000 179 #define DSISR_PROTECT 0x08000000 180 #define DSISR_INVRX 0x04000000 181 #define DSISR_STORE 0x02000000 182 #define DSISR_DABR 0x00400000 183 #define DSISR_SEGMENT 0x00200000 184 #define DSISR_EAR 0x00100000 185 186 /* 187 * Bits in SRR1 on ISI: 188 */ 189 #define ISSRR1_NOTFOUND 0x40000000 190 #define ISSRR1_DIRECT 0x10000000 191 #define ISSRR1_PROTECT 0x08000000 192 #define ISSRR1_SEGMENT 0x00200000 193 194 #else /* BOOKE */ 195 196 #include <machine/tlb.h> 197 198 #ifdef __powerpc64__ 199 200 #include <machine/tlb.h> 201 202 /* 203 * The virtual address is: 204 * 205 * 4K page size 206 * +-----+-----+-----+-------+-------------+-------------+----------------+ 207 * | - |p2d#h| - | p2d#l | dir# | pte# | off in 4K page | 208 * +-----+-----+-----+-------+-------------+-------------+----------------+ 209 * 63 62 61 60 59 40 39 30 29 ^ 21 20 ^ 12 11 0 210 * | | 211 * index in 1 page of pointers 212 * 213 * 1st level - pointers to page table directory (pp2d) 214 * 215 * pp2d consists of PP2D_NENTRIES entries, each being a pointer to 216 * second level entity, i.e. the page table directory (pdir). 217 */ 218 #define HARDWARE_WALKER 219 #define PP2D_H_H 61 220 #define PP2D_H_L 60 221 #define PP2D_L_H 39 222 #define PP2D_L_L 30 /* >30 would work with no page table pool */ 223 #ifndef LOCORE 224 #define PP2D_SIZE (1UL << PP2D_L_L) /* va range mapped by pp2d */ 225 #else 226 #define PP2D_SIZE (1 << PP2D_L_L) /* va range mapped by pp2d */ 227 #endif 228 #define PP2D_L_SHIFT PP2D_L_L 229 #define PP2D_L_NUM (PP2D_L_H-PP2D_L_L+1) 230 #define PP2D_L_MASK ((1<<PP2D_L_NUM)-1) 231 #define PP2D_H_SHIFT (PP2D_H_L-PP2D_L_NUM) 232 #define PP2D_H_NUM (PP2D_H_H-PP2D_H_L+1) 233 #define PP2D_H_MASK (((1<<PP2D_H_NUM)-1)<<PP2D_L_NUM) 234 #define PP2D_IDX(va) (((va >> PP2D_H_SHIFT) & PP2D_H_MASK) | ((va >> PP2D_L_SHIFT) & PP2D_L_MASK)) 235 #define PP2D_NENTRIES (1<<(PP2D_L_NUM+PP2D_H_NUM)) 236 #define PP2D_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */ 237 238 /* 239 * 2nd level - page table directory (pdir) 240 * 241 * pdir consists of PDIR_NENTRIES entries, each being a pointer to 242 * second level entity, i.e. the actual page table (ptbl). 243 */ 244 #define PDIR_H (PP2D_L_L-1) 245 #define PDIR_L 21 246 #define PDIR_NUM (PDIR_H-PDIR_L+1) 247 #define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */ 248 #define PDIR_MASK ((1<<PDIR_NUM)-1) 249 #define PDIR_SHIFT PDIR_L 250 #define PDIR_NENTRIES (1<<PDIR_NUM) 251 #define PDIR_IDX(va) (((va) >> PDIR_SHIFT) & PDIR_MASK) 252 #define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ 253 #define PDIR_PAGES ((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE) 254 255 /* 256 * 3rd level - page table (ptbl) 257 * 258 * Page table covers PTBL_NENTRIES page table entries. Page 259 * table entry (pte) is 64 bit wide and defines mapping 260 * for a single page. 261 */ 262 #define PTBL_H (PDIR_L-1) 263 #define PTBL_L PAGE_SHIFT 264 #define PTBL_NUM (PTBL_H-PTBL_L+1) 265 #define PTBL_MASK ((1<<PTBL_NUM)-1) 266 #define PTBL_SHIFT PTBL_L 267 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 268 #define PTBL_NENTRIES (1<<PTBL_NUM) 269 #define PTBL_IDX(va) ((va >> PTBL_SHIFT) & PTBL_MASK) 270 #define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */ 271 #define PTBL_PAGES ((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE) 272 273 #define KERNEL_LINEAR_MAX 0xc000000040000000 274 #else 275 /* 276 * 1st level - page table directory (pdir) 277 * 278 * pdir consists of 1024 entries, each being a pointer to 279 * second level entity, i.e. the actual page table (ptbl). 280 */ 281 #define PDIR_SHIFT 22 282 #define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */ 283 #define PDIR_MASK (~(PDIR_SIZE - 1)) 284 #define PDIR_NENTRIES 1024 /* number of page tables in pdir */ 285 286 /* Returns pdir entry number for given va */ 287 #define PDIR_IDX(va) ((va) >> PDIR_SHIFT) 288 289 #define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ 290 291 /* 292 * 2nd level - page table (ptbl) 293 * 294 * Page table covers 1024 page table entries. Page 295 * table entry (pte) is 32 bit wide and defines mapping 296 * for a single page. 297 */ 298 #define PTBL_SHIFT PAGE_SHIFT 299 #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ 300 #define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) 301 #define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ 302 303 /* Returns ptbl entry number for given va */ 304 #define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) 305 306 /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ 307 #define PTBL_PAGES 2 308 #define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ 309 310 #endif 311 312 /* 313 * Flags for pte_remove() routine. 314 */ 315 #define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ 316 #define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ 317 318 #define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) 319 320 /* 321 * Page Table Entry definitions and macros. 322 * 323 * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest 324 * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. 325 */ 326 #ifndef LOCORE 327 typedef uint64_t pte_t; 328 #endif 329 330 /* RPN mask, TLB0 4K pages */ 331 #define PTE_PA_MASK PAGE_MASK 332 333 #if defined(BOOKE_E500) 334 335 /* PTE bits assigned to MAS2, MAS3 flags */ 336 #define PTE_MAS2_SHIFT 19 337 #define PTE_W (MAS2_W << PTE_MAS2_SHIFT) 338 #define PTE_I (MAS2_I << PTE_MAS2_SHIFT) 339 #define PTE_M (MAS2_M << PTE_MAS2_SHIFT) 340 #define PTE_G (MAS2_G << PTE_MAS2_SHIFT) 341 #define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) 342 343 #define PTE_MAS3_SHIFT 2 344 #define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) 345 #define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) 346 #define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) 347 #define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) 348 #define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) 349 #define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) 350 #define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ 351 | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) 352 353 #define PTE_PS_SHIFT 8 354 #define PTE_PS_4KB (2 << PTE_PS_SHIFT) 355 356 #elif defined(BOOKE_PPC4XX) 357 358 #define PTE_WL1 TLB_WL1 359 #define PTE_IL2I TLB_IL2I 360 #define PTE_IL2D TLB_IL2D 361 362 #define PTE_W TLB_W 363 #define PTE_I TLB_I 364 #define PTE_M TLB_M 365 #define PTE_G TLB_G 366 367 #define PTE_UX TLB_UX 368 #define PTE_SX TLB_SX 369 #define PTE_UW TLB_UW 370 #define PTE_SW TLB_SW 371 #define PTE_UR TLB_UR 372 #define PTE_SR TLB_SR 373 374 #endif 375 376 /* Other PTE flags */ 377 #define PTE_VALID 0x00000001 /* Valid */ 378 #define PTE_MODIFIED 0x00001000 /* Modified */ 379 #define PTE_WIRED 0x00002000 /* Wired */ 380 #define PTE_MANAGED 0x00000002 /* Managed */ 381 #define PTE_REFERENCED 0x00040000 /* Referenced */ 382 383 /* 384 * Page Table Entry definitions and macros. 385 * 386 * We use the hardware page table entry format: 387 * 388 * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0 389 * --------------------------------------------------------------- 390 * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V 391 * --------------------------------------------------------------- 392 */ 393 394 /* PTE fields. */ 395 #define PTE_TSIZE_SHIFT (63-54) 396 #define PTE_TSIZE_MASK 0x7 397 #define PTE_TSIZE_SHIFT_DIRECT (63-55) 398 #define PTE_TSIZE_MASK_DIRECT 0xf 399 #define PTE_PS_DIRECT(ps) (ps<<PTE_TSIZE_SHIFT_DIRECT) /* Direct Entry Page Size */ 400 #define PTE_PS(ps) (ps<<PTE_TSIZE_SHIFT) /* Page Size */ 401 402 /* Macro argument must of pte_t type. */ 403 #define PTE_TSIZE(pte) (int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) 404 #define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) 405 406 /* Macro argument must of pte_t type. */ 407 #define PTE_ARPN_SHIFT 12 408 #define PTE_FLAGS_MASK 0x00ffffff 409 #define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) 410 #define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) 411 #define PTE_ISVALID(pte) ((*pte) & PTE_VALID) 412 #define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) 413 #define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) 414 #define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) 415 #define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) 416 417 #endif /* BOOKE */ 418 #endif /* _MACHINE_PTE_H_ */ 419