xref: /freebsd/sys/powerpc/include/pte.h (revision 17f4cae4a591331b2c700ede43ff33db21a59d27)
1f9bac91bSBenno Rice /*-
2f9bac91bSBenno Rice  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3f9bac91bSBenno Rice  * Copyright (C) 1995, 1996 TooLs GmbH.
4f9bac91bSBenno Rice  * All rights reserved.
5f9bac91bSBenno Rice  *
6f9bac91bSBenno Rice  * Redistribution and use in source and binary forms, with or without
7f9bac91bSBenno Rice  * modification, are permitted provided that the following conditions
8f9bac91bSBenno Rice  * are met:
9f9bac91bSBenno Rice  * 1. Redistributions of source code must retain the above copyright
10f9bac91bSBenno Rice  *    notice, this list of conditions and the following disclaimer.
11f9bac91bSBenno Rice  * 2. Redistributions in binary form must reproduce the above copyright
12f9bac91bSBenno Rice  *    notice, this list of conditions and the following disclaimer in the
13f9bac91bSBenno Rice  *    documentation and/or other materials provided with the distribution.
14f9bac91bSBenno Rice  * 3. All advertising materials mentioning features or use of this software
15f9bac91bSBenno Rice  *    must display the following acknowledgement:
16f9bac91bSBenno Rice  *	This product includes software developed by TooLs GmbH.
17f9bac91bSBenno Rice  * 4. The name of TooLs GmbH may not be used to endorse or promote products
18f9bac91bSBenno Rice  *    derived from this software without specific prior written permission.
19f9bac91bSBenno Rice  *
20f9bac91bSBenno Rice  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21f9bac91bSBenno Rice  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22f9bac91bSBenno Rice  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23f9bac91bSBenno Rice  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24f9bac91bSBenno Rice  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25f9bac91bSBenno Rice  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26f9bac91bSBenno Rice  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27f9bac91bSBenno Rice  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28f9bac91bSBenno Rice  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29f9bac91bSBenno Rice  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30f9bac91bSBenno Rice  *
31f9bac91bSBenno Rice  *	$NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $
32f9bac91bSBenno Rice  * $FreeBSD$
33f9bac91bSBenno Rice  */
34f9bac91bSBenno Rice 
35f9bac91bSBenno Rice #ifndef	_MACHINE_PTE_H_
36f9bac91bSBenno Rice #define	_MACHINE_PTE_H_
37f9bac91bSBenno Rice 
38ffb56695SRafal Jaworowski #if defined(AIM)
39ffb56695SRafal Jaworowski 
40f9bac91bSBenno Rice /*
41f9bac91bSBenno Rice  * Page Table Entries
42f9bac91bSBenno Rice  */
43f9bac91bSBenno Rice #ifndef	LOCORE
44f9bac91bSBenno Rice 
4558d7d1a8SPeter Grehan /* 32-bit PTE */
46f9bac91bSBenno Rice struct pte {
4758d7d1a8SPeter Grehan 	u_int32_t pte_hi;
4858d7d1a8SPeter Grehan 	u_int32_t pte_lo;
49f9bac91bSBenno Rice };
505244eac9SBenno Rice 
515244eac9SBenno Rice struct pteg {
525244eac9SBenno Rice 	struct	pte pt[8];
535244eac9SBenno Rice };
5458d7d1a8SPeter Grehan 
5558d7d1a8SPeter Grehan /* 64-bit (long) PTE */
5658d7d1a8SPeter Grehan struct lpte {
5758d7d1a8SPeter Grehan 	u_int64_t pte_hi;
5858d7d1a8SPeter Grehan 	u_int64_t pte_lo;
5958d7d1a8SPeter Grehan };
6058d7d1a8SPeter Grehan 
6158d7d1a8SPeter Grehan struct lpteg {
6258d7d1a8SPeter Grehan 	struct lpte pt[8];
6358d7d1a8SPeter Grehan };
6458d7d1a8SPeter Grehan 
65f9bac91bSBenno Rice #endif	/* LOCORE */
6658d7d1a8SPeter Grehan 
6758d7d1a8SPeter Grehan /* 32-bit PTE definitions */
6858d7d1a8SPeter Grehan 
69f9bac91bSBenno Rice /* High word: */
70f9bac91bSBenno Rice #define	PTE_VALID	0x80000000
71f9bac91bSBenno Rice #define	PTE_VSID_SHFT	7
72f9bac91bSBenno Rice #define	PTE_HID		0x00000040
73f9bac91bSBenno Rice #define	PTE_API		0x0000003f
74f9bac91bSBenno Rice /* Low word: */
75f9bac91bSBenno Rice #define	PTE_RPGN	0xfffff000
76f9bac91bSBenno Rice #define	PTE_REF		0x00000100
77f9bac91bSBenno Rice #define	PTE_CHG		0x00000080
78f9bac91bSBenno Rice #define	PTE_WIMG	0x00000078
79f9bac91bSBenno Rice #define	PTE_W		0x00000040
80f9bac91bSBenno Rice #define	PTE_I		0x00000020
81f9bac91bSBenno Rice #define	PTE_M		0x00000010
82f9bac91bSBenno Rice #define	PTE_G		0x00000008
83f9bac91bSBenno Rice #define	PTE_PP		0x00000003
845244eac9SBenno Rice #define	PTE_SO		0x00000000	/* Super. Only       (U: XX, S: RW) */
855244eac9SBenno Rice #define PTE_SW		0x00000001	/* Super. Write-Only (U: RO, S: RW) */
865244eac9SBenno Rice #define	PTE_BW		0x00000002	/* Supervisor        (U: RW, S: RW) */
875244eac9SBenno Rice #define	PTE_BR		0x00000003	/* Both Read Only    (U: RO, S: RO) */
885244eac9SBenno Rice #define	PTE_RW		PTE_BW
895244eac9SBenno Rice #define	PTE_RO		PTE_BR
90f9bac91bSBenno Rice 
918207b362SBenno Rice #define	PTE_EXEC	0x00000200	/* pseudo bit in attrs; page is exec */
928207b362SBenno Rice 
9358d7d1a8SPeter Grehan /* 64-bit PTE definitions */
9458d7d1a8SPeter Grehan 
9558d7d1a8SPeter Grehan /* High quadword: */
9658d7d1a8SPeter Grehan #define LPTE_VSID_SHIFT		12
9703479763SNathan Whitehorn #define LPTE_AVPN_MASK		0xFFFFFFFFFFFFFF80ULL
9858d7d1a8SPeter Grehan #define LPTE_API		0x0000000000000F80ULL
993b237732SNathan Whitehorn #define LPTE_LOCKED		0x0000000000000040ULL
1003b237732SNathan Whitehorn #define LPTE_WIRED		0x0000000000000008ULL
10158d7d1a8SPeter Grehan #define LPTE_BIG		0x0000000000000004ULL	/* 4kb/16Mb page */
10258d7d1a8SPeter Grehan #define LPTE_HID		0x0000000000000002ULL
10358d7d1a8SPeter Grehan #define LPTE_VALID		0x0000000000000001ULL
10458d7d1a8SPeter Grehan 
10558d7d1a8SPeter Grehan /* Low quadword: */
10658d7d1a8SPeter Grehan #define EXTEND_PTE(x)	UINT64_C(x)	/* make constants 64-bit */
10758d7d1a8SPeter Grehan #define	LPTE_RPGN	0xfffffffffffff000ULL
10858d7d1a8SPeter Grehan #define	LPTE_REF	EXTEND_PTE( PTE_REF )
10958d7d1a8SPeter Grehan #define	LPTE_CHG	EXTEND_PTE( PTE_CHG )
11058d7d1a8SPeter Grehan #define	LPTE_WIMG	EXTEND_PTE( PTE_WIMG )
11158d7d1a8SPeter Grehan #define	LPTE_W		EXTEND_PTE( PTE_W )
11258d7d1a8SPeter Grehan #define	LPTE_I		EXTEND_PTE( PTE_I )
11358d7d1a8SPeter Grehan #define	LPTE_M		EXTEND_PTE( PTE_M )
11458d7d1a8SPeter Grehan #define	LPTE_G		EXTEND_PTE( PTE_G )
11558d7d1a8SPeter Grehan #define	LPTE_NOEXEC	0x0000000000000004ULL
11658d7d1a8SPeter Grehan #define	LPTE_PP		EXTEND_PTE( PTE_PP )
11758d7d1a8SPeter Grehan 
11858d7d1a8SPeter Grehan #define	LPTE_SO		EXTEND_PTE( PTE_SO )	/* Super. Only */
11958d7d1a8SPeter Grehan #define	LPTE_SW		EXTEND_PTE( PTE_SW )	/* Super. Write-Only */
12058d7d1a8SPeter Grehan #define	LPTE_BW		EXTEND_PTE( PTE_BW )	/* Supervisor */
12158d7d1a8SPeter Grehan #define	LPTE_BR		EXTEND_PTE( PTE_BR )	/* Both Read Only */
12258d7d1a8SPeter Grehan #define	LPTE_RW		LPTE_BW
12358d7d1a8SPeter Grehan #define	LPTE_RO		LPTE_BR
12458d7d1a8SPeter Grehan 
125f9bac91bSBenno Rice #ifndef	LOCORE
126f9bac91bSBenno Rice typedef	struct pte pte_t;
12758d7d1a8SPeter Grehan typedef	struct lpte lpte_t;
128f9bac91bSBenno Rice #endif	/* LOCORE */
129f9bac91bSBenno Rice 
130f9bac91bSBenno Rice /*
131f9bac91bSBenno Rice  * Extract bits from address
132f9bac91bSBenno Rice  */
133f9bac91bSBenno Rice #define	ADDR_SR_SHFT	28
134c3e289e1SNathan Whitehorn #define	ADDR_PIDX	0x0ffff000UL
135f9bac91bSBenno Rice #define	ADDR_PIDX_SHFT	12
136f9bac91bSBenno Rice #define	ADDR_API_SHFT	22
13752a7870dSNathan Whitehorn #define	ADDR_API_SHFT64	16
138c3e289e1SNathan Whitehorn #define	ADDR_POFF	0x00000fffUL
139f9bac91bSBenno Rice 
140f9bac91bSBenno Rice /*
141f9bac91bSBenno Rice  * Bits in DSISR:
142f9bac91bSBenno Rice  */
143f9bac91bSBenno Rice #define	DSISR_DIRECT	0x80000000
144f9bac91bSBenno Rice #define	DSISR_NOTFOUND	0x40000000
145f9bac91bSBenno Rice #define	DSISR_PROTECT	0x08000000
146f9bac91bSBenno Rice #define	DSISR_INVRX	0x04000000
147f9bac91bSBenno Rice #define	DSISR_STORE	0x02000000
148f9bac91bSBenno Rice #define	DSISR_DABR	0x00400000
149f9bac91bSBenno Rice #define	DSISR_SEGMENT	0x00200000
150f9bac91bSBenno Rice #define	DSISR_EAR	0x00100000
151f9bac91bSBenno Rice 
152f9bac91bSBenno Rice /*
153f9bac91bSBenno Rice  * Bits in SRR1 on ISI:
154f9bac91bSBenno Rice  */
155f9bac91bSBenno Rice #define	ISSRR1_NOTFOUND	0x40000000
156f9bac91bSBenno Rice #define	ISSRR1_DIRECT	0x10000000
157f9bac91bSBenno Rice #define	ISSRR1_PROTECT	0x08000000
158f9bac91bSBenno Rice #define	ISSRR1_SEGMENT	0x00200000
159f9bac91bSBenno Rice 
160f9bac91bSBenno Rice #ifdef	_KERNEL
161f9bac91bSBenno Rice #ifndef	LOCORE
162812344bcSAlfred Perlstein extern u_int dsisr(void);
163f9bac91bSBenno Rice #endif	/* _KERNEL */
164f9bac91bSBenno Rice #endif	/* LOCORE */
165ffb56695SRafal Jaworowski 
166*17f4cae4SRafal Jaworowski #else /* BOOKE */
167ffb56695SRafal Jaworowski 
168ffb56695SRafal Jaworowski #include <machine/tlb.h>
169ffb56695SRafal Jaworowski 
170ffb56695SRafal Jaworowski /*
171ffb56695SRafal Jaworowski  * 1st level - page table directory (pdir)
172ffb56695SRafal Jaworowski  *
173ffb56695SRafal Jaworowski  * pdir consists of 1024 entries, each being a pointer to
174ffb56695SRafal Jaworowski  * second level entity, i.e. the actual page table (ptbl).
175ffb56695SRafal Jaworowski  */
176ffb56695SRafal Jaworowski #define PDIR_SHIFT	22
177ffb56695SRafal Jaworowski #define PDIR_SIZE	(1 << PDIR_SHIFT)	/* va range mapped by pdir */
178ffb56695SRafal Jaworowski #define PDIR_MASK	(~(PDIR_SIZE - 1))
179ffb56695SRafal Jaworowski #define PDIR_NENTRIES	1024			/* number of page tables in pdir */
180ffb56695SRafal Jaworowski 
181ffb56695SRafal Jaworowski /* Returns pdir entry number for given va */
182ffb56695SRafal Jaworowski #define PDIR_IDX(va)	((va) >> PDIR_SHIFT)
183ffb56695SRafal Jaworowski 
184ffb56695SRafal Jaworowski #define PDIR_ENTRY_SHIFT 2	/* entry size is 2^2 = 4 bytes */
185ffb56695SRafal Jaworowski 
186ffb56695SRafal Jaworowski /*
187ffb56695SRafal Jaworowski  * 2nd level - page table (ptbl)
188ffb56695SRafal Jaworowski  *
189ffb56695SRafal Jaworowski  * Page table covers 1024 page table entries. Page
190ffb56695SRafal Jaworowski  * table entry (pte) is 32 bit wide and defines mapping
191ffb56695SRafal Jaworowski  * for a single page.
192ffb56695SRafal Jaworowski  */
193ffb56695SRafal Jaworowski #define PTBL_SHIFT	PAGE_SHIFT
194ffb56695SRafal Jaworowski #define PTBL_SIZE	PAGE_SIZE		/* va range mapped by ptbl entry */
195c3e289e1SNathan Whitehorn #define PTBL_MASK	((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1))
196ffb56695SRafal Jaworowski #define PTBL_NENTRIES	1024			/* number of pages mapped by ptbl */
197ffb56695SRafal Jaworowski 
198ffb56695SRafal Jaworowski /* Returns ptbl entry number for given va */
199ffb56695SRafal Jaworowski #define PTBL_IDX(va)	(((va) & PTBL_MASK) >> PTBL_SHIFT)
200ffb56695SRafal Jaworowski 
201ffb56695SRafal Jaworowski /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */
202ffb56695SRafal Jaworowski #define PTBL_PAGES	2
203ffb56695SRafal Jaworowski #define PTBL_ENTRY_SHIFT 3	/* entry size is 2^3 = 8 bytes */
204ffb56695SRafal Jaworowski 
205ffb56695SRafal Jaworowski /*
206ffb56695SRafal Jaworowski  * Flags for pte_remove() routine.
207ffb56695SRafal Jaworowski  */
208ffb56695SRafal Jaworowski #define PTBL_HOLD	0x00000001	/* do not unhold ptbl pages */
209ffb56695SRafal Jaworowski #define PTBL_UNHOLD	0x00000002	/* unhold and attempt to free ptbl pages */
210ffb56695SRafal Jaworowski 
211ffb56695SRafal Jaworowski #define PTBL_HOLD_FLAG(pmap)	(((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD)
212ffb56695SRafal Jaworowski 
213ffb56695SRafal Jaworowski /*
214ffb56695SRafal Jaworowski  * Page Table Entry definitions and macros.
215ffb56695SRafal Jaworowski  */
216ffb56695SRafal Jaworowski #ifndef	LOCORE
217b2b734e7SRafal Jaworowski struct pte {
218ffb56695SRafal Jaworowski 	vm_offset_t rpn;
219b2b734e7SRafal Jaworowski 	uint32_t flags;
220ffb56695SRafal Jaworowski };
221b2b734e7SRafal Jaworowski typedef struct pte pte_t;
222ffb56695SRafal Jaworowski #endif
223ffb56695SRafal Jaworowski 
224ffb56695SRafal Jaworowski /* RPN mask, TLB0 4K pages */
225ffb56695SRafal Jaworowski #define PTE_PA_MASK	PAGE_MASK
226ffb56695SRafal Jaworowski 
227*17f4cae4SRafal Jaworowski #if defined(BOOKE_E500)
228*17f4cae4SRafal Jaworowski 
229ffb56695SRafal Jaworowski /* PTE bits assigned to MAS2, MAS3 flags */
230ffb56695SRafal Jaworowski #define PTE_W		MAS2_W
231ffb56695SRafal Jaworowski #define PTE_I		MAS2_I
232ffb56695SRafal Jaworowski #define PTE_M		MAS2_M
233ffb56695SRafal Jaworowski #define PTE_G		MAS2_G
234ffb56695SRafal Jaworowski #define PTE_MAS2_MASK	(MAS2_G | MAS2_M | MAS2_I | MAS2_W)
235ffb56695SRafal Jaworowski 
236ffb56695SRafal Jaworowski #define PTE_MAS3_SHIFT	8
237ffb56695SRafal Jaworowski #define PTE_UX		(MAS3_UX << PTE_MAS3_SHIFT)
238ffb56695SRafal Jaworowski #define PTE_SX		(MAS3_SX << PTE_MAS3_SHIFT)
239ffb56695SRafal Jaworowski #define PTE_UW		(MAS3_UW << PTE_MAS3_SHIFT)
240ffb56695SRafal Jaworowski #define PTE_SW		(MAS3_SW << PTE_MAS3_SHIFT)
241ffb56695SRafal Jaworowski #define PTE_UR		(MAS3_UR << PTE_MAS3_SHIFT)
242ffb56695SRafal Jaworowski #define PTE_SR		(MAS3_SR << PTE_MAS3_SHIFT)
243ffb56695SRafal Jaworowski #define PTE_MAS3_MASK	((MAS3_UX | MAS3_SX | MAS3_UW	\
244ffb56695SRafal Jaworowski 			| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
245ffb56695SRafal Jaworowski 
246*17f4cae4SRafal Jaworowski #elif defined(BOOKE_PPC4XX)
247*17f4cae4SRafal Jaworowski 
248*17f4cae4SRafal Jaworowski #define PTE_WL1		TLB_WL1
249*17f4cae4SRafal Jaworowski #define PTE_IL2I	TLB_IL2I
250*17f4cae4SRafal Jaworowski #define PTE_IL2D	TLB_IL2D
251*17f4cae4SRafal Jaworowski 
252*17f4cae4SRafal Jaworowski #define PTE_W		TLB_W
253*17f4cae4SRafal Jaworowski #define PTE_I		TLB_I
254*17f4cae4SRafal Jaworowski #define PTE_M		TLB_M
255*17f4cae4SRafal Jaworowski #define PTE_G		TLB_G
256*17f4cae4SRafal Jaworowski 
257*17f4cae4SRafal Jaworowski #define PTE_UX		TLB_UX
258*17f4cae4SRafal Jaworowski #define PTE_SX		TLB_SX
259*17f4cae4SRafal Jaworowski #define PTE_UW		TLB_UW
260*17f4cae4SRafal Jaworowski #define PTE_SW		TLB_SW
261*17f4cae4SRafal Jaworowski #define PTE_UR		TLB_UR
262*17f4cae4SRafal Jaworowski #define PTE_SR		TLB_SR
263*17f4cae4SRafal Jaworowski 
264*17f4cae4SRafal Jaworowski #endif
265*17f4cae4SRafal Jaworowski 
266ffb56695SRafal Jaworowski /* Other PTE flags */
267ffb56695SRafal Jaworowski #define PTE_VALID	0x80000000	/* Valid */
268ffb56695SRafal Jaworowski #define PTE_MODIFIED	0x40000000	/* Modified */
269ffb56695SRafal Jaworowski #define PTE_WIRED	0x20000000	/* Wired */
270ffb56695SRafal Jaworowski #define PTE_MANAGED	0x10000000	/* Managed */
271ffb56695SRafal Jaworowski #define PTE_REFERENCED	0x04000000	/* Referenced */
272ffb56695SRafal Jaworowski 
273ffb56695SRafal Jaworowski /* Macro argument must of pte_t type. */
274ffb56695SRafal Jaworowski #define PTE_PA(pte)		((pte)->rpn & ~PTE_PA_MASK)
275ffb56695SRafal Jaworowski #define PTE_ISVALID(pte)	((pte)->flags & PTE_VALID)
276ffb56695SRafal Jaworowski #define PTE_ISWIRED(pte)	((pte)->flags & PTE_WIRED)
277ffb56695SRafal Jaworowski #define PTE_ISMANAGED(pte)	((pte)->flags & PTE_MANAGED)
278ffb56695SRafal Jaworowski #define PTE_ISMODIFIED(pte)	((pte)->flags & PTE_MODIFIED)
279ffb56695SRafal Jaworowski #define PTE_ISREFERENCED(pte)	((pte)->flags & PTE_REFERENCED)
280ffb56695SRafal Jaworowski 
281*17f4cae4SRafal Jaworowski #endif /* BOOKE_PPC4XX */
282f9bac91bSBenno Rice #endif /* _MACHINE_PTE_H_ */
283