1 /*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by TooLs GmbH. 17 * 4. The name of TooLs GmbH may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $ 32 * $FreeBSD$ 33 */ 34 35 #ifndef _MACHINE_PSL_H_ 36 #define _MACHINE_PSL_H_ 37 38 #if defined(E500) 39 /* 40 * Machine State Register (MSR) - e500 core 41 * 42 * The PowerPC e500 does not implement the following bits: 43 * 44 * FP, FE0, FE1 - reserved, always cleared, setting has no effect. 45 * 46 */ 47 #define PSL_UCLE 0x04000000 /* User mode cache lock enable */ 48 #define PSL_SPE 0x02000000 /* SPE enable */ 49 #define PSL_WE 0x00040000 /* Wait state enable */ 50 #define PSL_CE 0x00020000 /* Critical interrupt enable */ 51 #define PSL_EE 0x00008000 /* External interrupt enable */ 52 #define PSL_PR 0x00004000 /* User mode */ 53 #define PSL_FP 0x00002000 /* Floating point available */ 54 #define PSL_ME 0x00001000 /* Machine check interrupt enable */ 55 #define PSL_FE0 0x00000800 /* Floating point exception mode 0 */ 56 #define PSL_UBLE 0x00000400 /* BTB lock enable */ 57 #define PSL_DE 0x00000200 /* Debug interrupt enable */ 58 #define PSL_FE1 0x00000100 /* Floating point exception mode 1 */ 59 #define PSL_IS 0x00000020 /* Instruction address space */ 60 #define PSL_DS 0x00000010 /* Data address space */ 61 #define PSL_PMM 0x00000004 /* Performance monitor mark */ 62 63 /* Initial kernel MSR, use IS=1 ad DS=1. */ 64 #define PSL_KERNSET_INIT (PSL_IS | PSL_DS) 65 #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) 66 #define PSL_USERSET (PSL_KERNSET | PSL_PR) 67 68 #else /* if defined(E500) */ 69 /* 70 * Machine State Register (MSR) 71 * 72 * The PowerPC 601 does not implement the following bits: 73 * 74 * VEC, POW, ILE, BE, RI, LE[*] 75 * 76 * [*] Little-endian mode on the 601 is implemented in the HID0 register. 77 */ 78 #define PSL_VEC 0x02000000 /* AltiVec vector unit available */ 79 #define PSL_POW 0x00040000 /* power management */ 80 #define PSL_ILE 0x00010000 /* interrupt endian mode (1 == le) */ 81 #define PSL_EE 0x00008000 /* external interrupt enable */ 82 #define PSL_PR 0x00004000 /* privilege mode (1 == user) */ 83 #define PSL_FP 0x00002000 /* floating point enable */ 84 #define PSL_ME 0x00001000 /* machine check enable */ 85 #define PSL_FE0 0x00000800 /* floating point interrupt mode 0 */ 86 #define PSL_SE 0x00000400 /* single-step trace enable */ 87 #define PSL_BE 0x00000200 /* branch trace enable */ 88 #define PSL_FE1 0x00000100 /* floating point interrupt mode 1 */ 89 #define PSL_IP 0x00000040 /* interrupt prefix */ 90 #define PSL_IR 0x00000020 /* instruction address relocation */ 91 #define PSL_DR 0x00000010 /* data address relocation */ 92 #define PSL_RI 0x00000002 /* recoverable interrupt */ 93 #define PSL_LE 0x00000001 /* endian mode (1 == le) */ 94 95 #define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE) 96 97 /* 98 * Floating-point exception modes: 99 */ 100 #define PSL_FE_DIS 0 /* none */ 101 #define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */ 102 #define PSL_FE_REC PSL_FE0 /* imprecise recoverable */ 103 #define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */ 104 #define PSL_FE_DFLT PSL_FE_DIS /* default == none */ 105 106 /* 107 * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR 108 */ 109 #define PSL_MBO 0 110 #define PSL_MBZ 0 111 112 #define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) 113 #define PSL_USERSET (PSL_KERNSET | PSL_PR) 114 115 #define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c) 116 117 #endif /* if defined(E500) */ 118 #endif /* _MACHINE_PSL_H_ */ 119