160727d8bSWarner Losh /*- 2*51369649SPedro F. Giffuni * SPDX-License-Identifier: BSD-4-Clause 3*51369649SPedro F. Giffuni * 4f9bac91bSBenno Rice * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. 5f9bac91bSBenno Rice * 6f9bac91bSBenno Rice * Redistribution and use in source and binary forms, with or without 7f9bac91bSBenno Rice * modification, are permitted provided that the following conditions 8f9bac91bSBenno Rice * are met: 9f9bac91bSBenno Rice * 1. Redistributions of source code must retain the above copyright 10f9bac91bSBenno Rice * notice, this list of conditions and the following disclaimer. 11f9bac91bSBenno Rice * 2. Redistributions in binary form must reproduce the above copyright 12f9bac91bSBenno Rice * notice, this list of conditions and the following disclaimer in the 13f9bac91bSBenno Rice * documentation and/or other materials provided with the distribution. 14f9bac91bSBenno Rice * 3. All advertising materials mentioning features or use of this software 15f9bac91bSBenno Rice * must display the following acknowledgement: 16f9bac91bSBenno Rice * This product includes software developed under OpenBSD by 17f9bac91bSBenno Rice * Per Fogelstrom Opsycon AB for RTMX Inc, North Carolina, USA. 18f9bac91bSBenno Rice * 4. The name of the author may not be used to endorse or promote products 19f9bac91bSBenno Rice * derived from this software without specific prior written permission. 20f9bac91bSBenno Rice * 21f9bac91bSBenno Rice * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 22f9bac91bSBenno Rice * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23f9bac91bSBenno Rice * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24f9bac91bSBenno Rice * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 25f9bac91bSBenno Rice * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26f9bac91bSBenno Rice * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27f9bac91bSBenno Rice * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28f9bac91bSBenno Rice * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29f9bac91bSBenno Rice * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30f9bac91bSBenno Rice * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31f9bac91bSBenno Rice * SUCH DAMAGE. 32f9bac91bSBenno Rice * 33f9bac91bSBenno Rice * $NetBSD: pio.h,v 1.1 1998/05/15 10:15:54 tsubai Exp $ 34f9bac91bSBenno Rice * $OpenBSD: pio.h,v 1.1 1997/10/13 10:53:47 pefo Exp $ 35f9bac91bSBenno Rice * $FreeBSD$ 36f9bac91bSBenno Rice */ 37f9bac91bSBenno Rice 38f9bac91bSBenno Rice #ifndef _MACHINE_PIO_H_ 39f9bac91bSBenno Rice #define _MACHINE_PIO_H_ 40f9bac91bSBenno Rice /* 41f9bac91bSBenno Rice * I/O macros. 42f9bac91bSBenno Rice */ 43f9bac91bSBenno Rice 44bc96dcccSNathan Whitehorn /* 45bc96dcccSNathan Whitehorn * Use sync so that bus space operations cannot sneak out the bottom of 46bc96dcccSNathan Whitehorn * mutex-protected sections (mutex release does not guarantee completion of 47bc96dcccSNathan Whitehorn * accesses to caching-inhibited memory on some systems) 48bc96dcccSNathan Whitehorn */ 49bc96dcccSNathan Whitehorn #define powerpc_iomb() __asm __volatile("sync" : : : "memory") 5013d47f30SNathan Whitehorn 51f9bac91bSBenno Rice static __inline void 52f9bac91bSBenno Rice __outb(volatile u_int8_t *a, u_int8_t v) 53f9bac91bSBenno Rice { 54f9bac91bSBenno Rice *a = v; 5513d47f30SNathan Whitehorn powerpc_iomb(); 56f9bac91bSBenno Rice } 57f9bac91bSBenno Rice 58f9bac91bSBenno Rice static __inline void 59f9bac91bSBenno Rice __outw(volatile u_int16_t *a, u_int16_t v) 60f9bac91bSBenno Rice { 61f9bac91bSBenno Rice *a = v; 6213d47f30SNathan Whitehorn powerpc_iomb(); 63f9bac91bSBenno Rice } 64f9bac91bSBenno Rice 65f9bac91bSBenno Rice static __inline void 66f9bac91bSBenno Rice __outl(volatile u_int32_t *a, u_int32_t v) 67f9bac91bSBenno Rice { 68f9bac91bSBenno Rice *a = v; 6913d47f30SNathan Whitehorn powerpc_iomb(); 70f9bac91bSBenno Rice } 71f9bac91bSBenno Rice 72f9bac91bSBenno Rice static __inline void 73ef0e1c23SRafal Jaworowski __outll(volatile u_int64_t *a, u_int64_t v) 74ef0e1c23SRafal Jaworowski { 75ef0e1c23SRafal Jaworowski *a = v; 7613d47f30SNathan Whitehorn powerpc_iomb(); 77ef0e1c23SRafal Jaworowski } 78ef0e1c23SRafal Jaworowski 79ef0e1c23SRafal Jaworowski static __inline void 80f9bac91bSBenno Rice __outwrb(volatile u_int16_t *a, u_int16_t v) 81f9bac91bSBenno Rice { 82f9bac91bSBenno Rice __asm__ volatile("sthbrx %0, 0, %1" :: "r"(v), "r"(a)); 8313d47f30SNathan Whitehorn powerpc_iomb(); 84f9bac91bSBenno Rice } 85f9bac91bSBenno Rice 86f9bac91bSBenno Rice static __inline void 87f9bac91bSBenno Rice __outlrb(volatile u_int32_t *a, u_int32_t v) 88f9bac91bSBenno Rice { 89f9bac91bSBenno Rice __asm__ volatile("stwbrx %0, 0, %1" :: "r"(v), "r"(a)); 9013d47f30SNathan Whitehorn powerpc_iomb(); 91f9bac91bSBenno Rice } 92f9bac91bSBenno Rice 93f9bac91bSBenno Rice static __inline u_int8_t 94f9bac91bSBenno Rice __inb(volatile u_int8_t *a) 95f9bac91bSBenno Rice { 96f9bac91bSBenno Rice u_int8_t _v_; 97f9bac91bSBenno Rice 98f9bac91bSBenno Rice _v_ = *a; 9913d47f30SNathan Whitehorn powerpc_iomb(); 100f9bac91bSBenno Rice return _v_; 101f9bac91bSBenno Rice } 102f9bac91bSBenno Rice 103f9bac91bSBenno Rice static __inline u_int16_t 104f9bac91bSBenno Rice __inw(volatile u_int16_t *a) 105f9bac91bSBenno Rice { 106f9bac91bSBenno Rice u_int16_t _v_; 107f9bac91bSBenno Rice 108f9bac91bSBenno Rice _v_ = *a; 10913d47f30SNathan Whitehorn powerpc_iomb(); 110f9bac91bSBenno Rice return _v_; 111f9bac91bSBenno Rice } 112f9bac91bSBenno Rice 113f9bac91bSBenno Rice static __inline u_int32_t 114f9bac91bSBenno Rice __inl(volatile u_int32_t *a) 115f9bac91bSBenno Rice { 116f9bac91bSBenno Rice u_int32_t _v_; 117f9bac91bSBenno Rice 118f9bac91bSBenno Rice _v_ = *a; 11913d47f30SNathan Whitehorn powerpc_iomb(); 120f9bac91bSBenno Rice return _v_; 121f9bac91bSBenno Rice } 122f9bac91bSBenno Rice 123ef0e1c23SRafal Jaworowski static __inline u_int64_t 124ef0e1c23SRafal Jaworowski __inll(volatile u_int64_t *a) 125ef0e1c23SRafal Jaworowski { 126ef0e1c23SRafal Jaworowski u_int64_t _v_; 127ef0e1c23SRafal Jaworowski 128ef0e1c23SRafal Jaworowski _v_ = *a; 12913d47f30SNathan Whitehorn powerpc_iomb(); 130ef0e1c23SRafal Jaworowski return _v_; 131ef0e1c23SRafal Jaworowski } 132ef0e1c23SRafal Jaworowski 133f9bac91bSBenno Rice static __inline u_int16_t 134f9bac91bSBenno Rice __inwrb(volatile u_int16_t *a) 135f9bac91bSBenno Rice { 136f9bac91bSBenno Rice u_int16_t _v_; 137f9bac91bSBenno Rice 138f9bac91bSBenno Rice __asm__ volatile("lhbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); 13913d47f30SNathan Whitehorn powerpc_iomb(); 140f9bac91bSBenno Rice return _v_; 141f9bac91bSBenno Rice } 142f9bac91bSBenno Rice 143f9bac91bSBenno Rice static __inline u_int32_t 144f9bac91bSBenno Rice __inlrb(volatile u_int32_t *a) 145f9bac91bSBenno Rice { 146f9bac91bSBenno Rice u_int32_t _v_; 147f9bac91bSBenno Rice 148f9bac91bSBenno Rice __asm__ volatile("lwbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); 14913d47f30SNathan Whitehorn powerpc_iomb(); 150f9bac91bSBenno Rice return _v_; 151f9bac91bSBenno Rice } 152f9bac91bSBenno Rice 153f9bac91bSBenno Rice #define outb(a,v) (__outb((volatile u_int8_t *)(a), v)) 154f9bac91bSBenno Rice #define out8(a,v) outb(a,v) 155f9bac91bSBenno Rice #define outw(a,v) (__outw((volatile u_int16_t *)(a), v)) 156f9bac91bSBenno Rice #define out16(a,v) outw(a,v) 157f9bac91bSBenno Rice #define outl(a,v) (__outl((volatile u_int32_t *)(a), v)) 158f9bac91bSBenno Rice #define out32(a,v) outl(a,v) 159ef0e1c23SRafal Jaworowski #define outll(a,v) (__outll((volatile u_int64_t *)(a), v)) 160ef0e1c23SRafal Jaworowski #define out64(a,v) outll(a,v) 161f9bac91bSBenno Rice #define inb(a) (__inb((volatile u_int8_t *)(a))) 162f9bac91bSBenno Rice #define in8(a) inb(a) 163f9bac91bSBenno Rice #define inw(a) (__inw((volatile u_int16_t *)(a))) 164f9bac91bSBenno Rice #define in16(a) inw(a) 165f9bac91bSBenno Rice #define inl(a) (__inl((volatile u_int32_t *)(a))) 166f9bac91bSBenno Rice #define in32(a) inl(a) 167ef0e1c23SRafal Jaworowski #define inll(a) (__inll((volatile u_int64_t *)(a))) 168ef0e1c23SRafal Jaworowski #define in64(a) inll(a) 169f9bac91bSBenno Rice 170f9bac91bSBenno Rice #define out8rb(a,v) outb(a,v) 171f9bac91bSBenno Rice #define outwrb(a,v) (__outwrb((volatile u_int16_t *)(a), v)) 172f9bac91bSBenno Rice #define out16rb(a,v) outwrb(a,v) 173f9bac91bSBenno Rice #define outlrb(a,v) (__outlrb((volatile u_int32_t *)(a), v)) 174f9bac91bSBenno Rice #define out32rb(a,v) outlrb(a,v) 175f9bac91bSBenno Rice #define in8rb(a) inb(a) 176f9bac91bSBenno Rice #define inwrb(a) (__inwrb((volatile u_int16_t *)(a))) 177f9bac91bSBenno Rice #define in16rb(a) inwrb(a) 178f9bac91bSBenno Rice #define inlrb(a) (__inlrb((volatile u_int32_t *)(a))) 179f9bac91bSBenno Rice #define in32rb(a) inlrb(a) 180f9bac91bSBenno Rice 181f9bac91bSBenno Rice 182f9bac91bSBenno Rice static __inline void 183f9bac91bSBenno Rice __outsb(volatile u_int8_t *a, const u_int8_t *s, size_t c) 184f9bac91bSBenno Rice { 185f9bac91bSBenno Rice while (c--) 186f9bac91bSBenno Rice *a = *s++; 18713d47f30SNathan Whitehorn powerpc_iomb(); 188f9bac91bSBenno Rice } 189f9bac91bSBenno Rice 190f9bac91bSBenno Rice static __inline void 191f9bac91bSBenno Rice __outsw(volatile u_int16_t *a, const u_int16_t *s, size_t c) 192f9bac91bSBenno Rice { 193f9bac91bSBenno Rice while (c--) 194f9bac91bSBenno Rice *a = *s++; 19513d47f30SNathan Whitehorn powerpc_iomb(); 196f9bac91bSBenno Rice } 197f9bac91bSBenno Rice 198f9bac91bSBenno Rice static __inline void 199f9bac91bSBenno Rice __outsl(volatile u_int32_t *a, const u_int32_t *s, size_t c) 200f9bac91bSBenno Rice { 201f9bac91bSBenno Rice while (c--) 202f9bac91bSBenno Rice *a = *s++; 20313d47f30SNathan Whitehorn powerpc_iomb(); 204f9bac91bSBenno Rice } 205f9bac91bSBenno Rice 206f9bac91bSBenno Rice static __inline void 207ef0e1c23SRafal Jaworowski __outsll(volatile u_int64_t *a, const u_int64_t *s, size_t c) 208ef0e1c23SRafal Jaworowski { 209ef0e1c23SRafal Jaworowski while (c--) 210ef0e1c23SRafal Jaworowski *a = *s++; 21113d47f30SNathan Whitehorn powerpc_iomb(); 212ef0e1c23SRafal Jaworowski } 213ef0e1c23SRafal Jaworowski 214ef0e1c23SRafal Jaworowski static __inline void 215f9bac91bSBenno Rice __outswrb(volatile u_int16_t *a, const u_int16_t *s, size_t c) 216f9bac91bSBenno Rice { 217f9bac91bSBenno Rice while (c--) 218f9bac91bSBenno Rice __asm__ volatile("sthbrx %0, 0, %1" :: "r"(*s++), "r"(a)); 21913d47f30SNathan Whitehorn powerpc_iomb(); 220f9bac91bSBenno Rice } 221f9bac91bSBenno Rice 222f9bac91bSBenno Rice static __inline void 223f9bac91bSBenno Rice __outslrb(volatile u_int32_t *a, const u_int32_t *s, size_t c) 224f9bac91bSBenno Rice { 225f9bac91bSBenno Rice while (c--) 226f9bac91bSBenno Rice __asm__ volatile("stwbrx %0, 0, %1" :: "r"(*s++), "r"(a)); 22713d47f30SNathan Whitehorn powerpc_iomb(); 228f9bac91bSBenno Rice } 229f9bac91bSBenno Rice 230f9bac91bSBenno Rice static __inline void 231f9bac91bSBenno Rice __insb(volatile u_int8_t *a, u_int8_t *d, size_t c) 232f9bac91bSBenno Rice { 233f9bac91bSBenno Rice while (c--) 234f9bac91bSBenno Rice *d++ = *a; 23513d47f30SNathan Whitehorn powerpc_iomb(); 236f9bac91bSBenno Rice } 237f9bac91bSBenno Rice 238f9bac91bSBenno Rice static __inline void 239f9bac91bSBenno Rice __insw(volatile u_int16_t *a, u_int16_t *d, size_t c) 240f9bac91bSBenno Rice { 241f9bac91bSBenno Rice while (c--) 242f9bac91bSBenno Rice *d++ = *a; 24313d47f30SNathan Whitehorn powerpc_iomb(); 244f9bac91bSBenno Rice } 245f9bac91bSBenno Rice 246f9bac91bSBenno Rice static __inline void 247f9bac91bSBenno Rice __insl(volatile u_int32_t *a, u_int32_t *d, size_t c) 248f9bac91bSBenno Rice { 249f9bac91bSBenno Rice while (c--) 250f9bac91bSBenno Rice *d++ = *a; 25113d47f30SNathan Whitehorn powerpc_iomb(); 252f9bac91bSBenno Rice } 253f9bac91bSBenno Rice 254f9bac91bSBenno Rice static __inline void 255ef0e1c23SRafal Jaworowski __insll(volatile u_int64_t *a, u_int64_t *d, size_t c) 256ef0e1c23SRafal Jaworowski { 257ef0e1c23SRafal Jaworowski while (c--) 258ef0e1c23SRafal Jaworowski *d++ = *a; 25913d47f30SNathan Whitehorn powerpc_iomb(); 260ef0e1c23SRafal Jaworowski } 261ef0e1c23SRafal Jaworowski 262ef0e1c23SRafal Jaworowski static __inline void 263f9bac91bSBenno Rice __inswrb(volatile u_int16_t *a, u_int16_t *d, size_t c) 264f9bac91bSBenno Rice { 265f9bac91bSBenno Rice while (c--) 266f9bac91bSBenno Rice __asm__ volatile("lhbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); 26713d47f30SNathan Whitehorn powerpc_iomb(); 268f9bac91bSBenno Rice } 269f9bac91bSBenno Rice 270f9bac91bSBenno Rice static __inline void 271f9bac91bSBenno Rice __inslrb(volatile u_int32_t *a, u_int32_t *d, size_t c) 272f9bac91bSBenno Rice { 273f9bac91bSBenno Rice while (c--) 274f9bac91bSBenno Rice __asm__ volatile("lwbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); 27513d47f30SNathan Whitehorn powerpc_iomb(); 276f9bac91bSBenno Rice } 277f9bac91bSBenno Rice 278f9bac91bSBenno Rice #define outsb(a,s,c) (__outsb((volatile u_int8_t *)(a), s, c)) 279f9bac91bSBenno Rice #define outs8(a,s,c) outsb(a,s,c) 280f9bac91bSBenno Rice #define outsw(a,s,c) (__outsw((volatile u_int16_t *)(a), s, c)) 281f9bac91bSBenno Rice #define outs16(a,s,c) outsw(a,s,c) 282f9bac91bSBenno Rice #define outsl(a,s,c) (__outsl((volatile u_int32_t *)(a), s, c)) 283f9bac91bSBenno Rice #define outs32(a,s,c) outsl(a,s,c) 284ef0e1c23SRafal Jaworowski #define outsll(a,s,c) (__outsll((volatile u_int64_t *)(a), s, c)) 285ef0e1c23SRafal Jaworowski #define outs64(a,s,c) outsll(a,s,c) 286f9bac91bSBenno Rice #define insb(a,d,c) (__insb((volatile u_int8_t *)(a), d, c)) 287f9bac91bSBenno Rice #define ins8(a,d,c) insb(a,d,c) 288f9bac91bSBenno Rice #define insw(a,d,c) (__insw((volatile u_int16_t *)(a), d, c)) 289f9bac91bSBenno Rice #define ins16(a,d,c) insw(a,d,c) 290f9bac91bSBenno Rice #define insl(a,d,c) (__insl((volatile u_int32_t *)(a), d, c)) 291f9bac91bSBenno Rice #define ins32(a,d,c) insl(a,d,c) 292ef0e1c23SRafal Jaworowski #define insll(a,d,c) (__insll((volatile u_int64_t *)(a), d, c)) 293ef0e1c23SRafal Jaworowski #define ins64(a,d,c) insll(a,d,c) 294f9bac91bSBenno Rice 295f9bac91bSBenno Rice #define outs8rb(a,s,c) outsb(a,s,c) 296f9bac91bSBenno Rice #define outswrb(a,s,c) (__outswrb((volatile u_int16_t *)(a), s, c)) 297f9bac91bSBenno Rice #define outs16rb(a,s,c) outswrb(a,s,c) 298f9bac91bSBenno Rice #define outslrb(a,s,c) (__outslrb((volatile u_int32_t *)(a), s, c)) 299f9bac91bSBenno Rice #define outs32rb(a,s,c) outslrb(a,s,c) 300f9bac91bSBenno Rice #define ins8rb(a,d,c) insb(a,d,c) 301f9bac91bSBenno Rice #define inswrb(a,d,c) (__inswrb((volatile u_int16_t *)(a), d, c)) 302f9bac91bSBenno Rice #define ins16rb(a,d,c) inswrb(a,d,c) 303f9bac91bSBenno Rice #define inslrb(a,d,c) (__inslrb((volatile u_int32_t *)(a), d, c)) 304f9bac91bSBenno Rice #define ins32rb(a,d,c) inslrb(a,d,c) 305f9bac91bSBenno Rice 306f9bac91bSBenno Rice #endif /*_MACHINE_PIO_H_*/ 307