xref: /freebsd/sys/powerpc/include/pcpu.h (revision 5ab1c5846ff41be24b1f6beb0317bf8258cd4409)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
5  * Copyright (c) Peter Wemm <peter@netplex.com.au>
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 
32 #ifndef	_MACHINE_PCPU_H_
33 #define	_MACHINE_PCPU_H_
34 
35 #include <machine/cpufunc.h>
36 #include <machine/slb.h>
37 #include <machine/tlb.h>
38 
39 struct pmap;
40 struct pvo_entry;
41 #define	CPUSAVE_LEN	9
42 
43 #define	PCPU_MD_COMMON_FIELDS						\
44 	int		pc_inside_intr;					\
45 	struct pmap	*pc_curpmap;		/* current pmap */	\
46 	struct thread	*pc_fputhread;		/* current fpu user */  \
47 	struct thread	*pc_vecthread;		/* current vec user */  \
48 	struct thread	*pc_htmthread;		/* current htm user */  \
49 	uintptr_t	pc_hwref;					\
50 	int		pc_bsp;						\
51 	volatile int	pc_awake;					\
52 	uint32_t	pc_ipimask;					\
53 	register_t	pc_tempsave[CPUSAVE_LEN];			\
54 	register_t	pc_disisave[CPUSAVE_LEN];			\
55 	register_t	pc_dbsave[CPUSAVE_LEN];				\
56 	void		*pc_restore;					\
57 	vm_offset_t	pc_qmap_addr;
58 
59 #define PCPU_MD_AIM32_FIELDS						\
60 	struct pvo_entry *qmap_pvo;					\
61 	struct mtx	qmap_lock;					\
62 	char		__pad[128];
63 
64 #define PCPU_MD_AIM64_FIELDS						\
65 	struct slb	slb[64];					\
66 	struct slb	**userslb;					\
67 	register_t	slbsave[18];					\
68 	uint8_t		slbstack[1024];				\
69 	struct pvo_entry *qmap_pvo;					\
70 	struct mtx	qmap_lock;					\
71 	char		__pad[1345];
72 
73 #ifdef __powerpc64__
74 #define PCPU_MD_AIM_FIELDS	PCPU_MD_AIM64_FIELDS
75 #else
76 #define PCPU_MD_AIM_FIELDS	PCPU_MD_AIM32_FIELDS
77 #endif
78 
79 #define	BOOKE_CRITSAVE_LEN	(CPUSAVE_LEN + 2)
80 #define	BOOKE_TLB_MAXNEST	4
81 #define	BOOKE_TLB_SAVELEN	16
82 #define	BOOKE_TLBSAVE_LEN	(BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
83 
84 #ifdef __powerpc64__
85 #define	BOOKE_PCPU_PAD	901
86 #else
87 #define	BOOKE_PCPU_PAD	365
88 #endif
89 #define PCPU_MD_BOOKE_FIELDS						\
90 	register_t	critsave[BOOKE_CRITSAVE_LEN];		\
91 	register_t	mchksave[CPUSAVE_LEN];			\
92 	register_t	tlbsave[BOOKE_TLBSAVE_LEN];		\
93 	register_t	tlb_level;				\
94 	uintptr_t	*tlb_lock;				\
95 	int		tid_next;					\
96 	char		__pad[BOOKE_PCPU_PAD];
97 
98 /* Definitions for register offsets within the exception tmp save areas */
99 #define	CPUSAVE_R27	0		/* where r27 gets saved */
100 #define	CPUSAVE_R28	1		/* where r28 gets saved */
101 #define	CPUSAVE_R29	2		/* where r29 gets saved */
102 #define	CPUSAVE_R30	3		/* where r30 gets saved */
103 #define	CPUSAVE_R31	4		/* where r31 gets saved */
104 #define	CPUSAVE_AIM_DAR		5	/* where SPR_DAR gets saved */
105 #define	CPUSAVE_AIM_DSISR	6	/* where SPR_DSISR gets saved */
106 #define	CPUSAVE_BOOKE_DEAR	5	/* where SPR_DEAR gets saved */
107 #define	CPUSAVE_BOOKE_ESR	6	/* where SPR_ESR gets saved */
108 #define	CPUSAVE_SRR0	7		/* where SRR0 gets saved */
109 #define	CPUSAVE_SRR1	8		/* where SRR1 gets saved */
110 #define	BOOKE_CRITSAVE_SRR0	9	/* where real SRR0 gets saved (critical) */
111 #define	BOOKE_CRITSAVE_SRR1	10	/* where real SRR0 gets saved (critical) */
112 
113 /* Book-E TLBSAVE is more elaborate */
114 #define TLBSAVE_BOOKE_LR	0
115 #define TLBSAVE_BOOKE_CR	1
116 #define TLBSAVE_BOOKE_SRR0	2
117 #define TLBSAVE_BOOKE_SRR1	3
118 #define TLBSAVE_BOOKE_R20	4
119 #define TLBSAVE_BOOKE_R21	5
120 #define TLBSAVE_BOOKE_R22	6
121 #define TLBSAVE_BOOKE_R23	7
122 #define TLBSAVE_BOOKE_R24	8
123 #define TLBSAVE_BOOKE_R25	9
124 #define TLBSAVE_BOOKE_R26	10
125 #define TLBSAVE_BOOKE_R27	11
126 #define TLBSAVE_BOOKE_R28	12
127 #define TLBSAVE_BOOKE_R29	13
128 #define TLBSAVE_BOOKE_R30	14
129 #define TLBSAVE_BOOKE_R31	15
130 
131 #define	PCPU_MD_FIELDS		\
132 	PCPU_MD_COMMON_FIELDS	\
133 	union {			\
134 	    struct {		\
135 		PCPU_MD_AIM_FIELDS	\
136 	    } pc_aim;		\
137 	    struct {		\
138 		PCPU_MD_BOOKE_FIELDS	\
139 	    } pc_booke;		\
140 	}
141 
142 #ifdef _KERNEL
143 
144 #define pcpup	(get_pcpu())
145 
146 static __inline __pure2 struct thread *
147 __curthread(void)
148 {
149 	struct thread *td;
150 #ifdef __powerpc64__
151 	__asm __volatile("mr %0,13" : "=r"(td));
152 #else
153 	__asm __volatile("mr %0,2" : "=r"(td));
154 #endif
155 	return (td);
156 }
157 #define curthread (__curthread())
158 
159 #define	PCPU_GET(member)	(pcpup->pc_ ## member)
160 
161 /*
162  * XXX The implementation of this operation should be made atomic
163  * with respect to preemption.
164  */
165 #define	PCPU_ADD(member, value)	(pcpup->pc_ ## member += (value))
166 #define	PCPU_INC(member)	PCPU_ADD(member, 1)
167 #define	PCPU_PTR(member)	(&pcpup->pc_ ## member)
168 #define	PCPU_SET(member,value)	(pcpup->pc_ ## member = (value))
169 
170 #endif	/* _KERNEL */
171 
172 #endif	/* !_MACHINE_PCPU_H_ */
173