1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2002 Benno Rice. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _POWERPC_OPENPICVAR_H_ 31 #define _POWERPC_OPENPICVAR_H_ 32 33 #define OPENPIC_DEVSTR "OpenPIC Interrupt Controller" 34 35 #define OPENPIC_IRQMAX 256 /* h/w allows more */ 36 37 #define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */ 38 #define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */ 39 40 /* Names match the macros in openpicreg.h. */ 41 struct openpic_timer { 42 uint32_t tcnt; 43 uint32_t tbase; 44 uint32_t tvec; 45 uint32_t tdst; 46 }; 47 48 struct openpic_softc { 49 device_t sc_dev; 50 struct resource *sc_memr; 51 struct resource *sc_intr; 52 bus_space_tag_t sc_bt; 53 bus_space_handle_t sc_bh; 54 char *sc_version; 55 int sc_rid; 56 int sc_irq; 57 void *sc_icookie; 58 u_int sc_ncpu; 59 u_int sc_nirq; 60 int sc_psim; 61 u_int sc_quirks; 62 63 /* Saved states. */ 64 uint32_t sc_saved_config; 65 uint32_t sc_saved_ipis[4]; 66 uint32_t sc_saved_prios[4]; 67 struct openpic_timer sc_saved_timers[OPENPIC_TIMERS]; 68 uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT]; 69 70 }; 71 72 extern devclass_t openpic_devclass; 73 74 /* 75 * Bus-independent attach i/f 76 */ 77 int openpic_common_attach(device_t, uint32_t); 78 79 /* 80 * PIC interface. 81 */ 82 void openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **); 83 void openpic_config(device_t, u_int, enum intr_trigger, enum intr_polarity); 84 void openpic_dispatch(device_t, struct trapframe *); 85 void openpic_enable(device_t, u_int, u_int, void **); 86 void openpic_eoi(device_t, u_int, void *); 87 void openpic_ipi(device_t, u_int); 88 void openpic_mask(device_t, u_int, void *); 89 void openpic_unmask(device_t, u_int, void *); 90 91 int openpic_suspend(device_t dev); 92 int openpic_resume(device_t dev); 93 94 #endif /* _POWERPC_OPENPICVAR_H_ */ 95