1 /*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp 27 * $FreeBSD$ 28 */ 29 30 /* 31 * Size of OpenPIC register space 32 */ 33 #define OPENPIC_SIZE 0x40000 34 35 /* 36 * Per Processor Registers [private access] (0x00000 - 0x00fff) 37 */ 38 39 /* IPI dispatch command reg */ 40 #define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10) 41 42 /* current task priority reg */ 43 #define OPENPIC_TPR 0x80 44 #define OPENPIC_TPR_MASK 0x0000000f 45 46 #define OPENPIC_WHOAMI 0x90 47 48 /* interrupt acknowledge reg */ 49 #define OPENPIC_IACK 0xa0 50 51 /* end of interrupt reg */ 52 #define OPENPIC_EOI 0xb0 53 54 /* 55 * Global registers (0x01000-0x0ffff) 56 */ 57 58 /* feature reporting reg 0 */ 59 #define OPENPIC_FEATURE 0x1000 60 #define OPENPIC_FEATURE_VERSION_MASK 0x000000ff 61 #define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 62 #define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 63 #define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 64 #define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 65 66 /* global config reg 0 */ 67 #define OPENPIC_CONFIG 0x1020 68 #define OPENPIC_CONFIG_RESET 0x80000000 69 #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 70 71 /* interrupt configuration mode (direct or serial) */ 72 #define OPENPIC_ICR 0x1030 73 #define OPENPIC_ICR_SERIAL_MODE (1 << 27) 74 #define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 75 #define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 76 77 /* vendor ID */ 78 #define OPENPIC_VENDOR_ID 0x1080 79 80 /* processor initialization reg */ 81 #define OPENPIC_PROC_INIT 0x1090 82 83 /* IPI vector/priority reg */ 84 #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 85 86 /* spurious intr. vector */ 87 #define OPENPIC_SPURIOUS_VECTOR 0x10e0 88 89 /* Timer registers */ 90 #define OPENPIC_TIMERS 4 91 #define OPENPIC_TFREQ 0x10f0 92 #define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40) 93 #define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40) 94 #define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40) 95 #define OPENPIC_TDST(t) (0x1130 + (t) * 0x40) 96 97 /* 98 * Interrupt Source Configuration Registers (0x10000 - 0x1ffff) 99 */ 100 101 /* interrupt vector/priority reg */ 102 #define OPENPIC_SRC_VECTOR_COUNT 64 103 #ifndef OPENPIC_SRC_VECTOR 104 #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 105 #endif 106 #define OPENPIC_SENSE_LEVEL 0x00400000 107 #define OPENPIC_SENSE_EDGE 0x00000000 108 #define OPENPIC_POLARITY_POSITIVE 0x00800000 109 #define OPENPIC_POLARITY_NEGATIVE 0x00000000 110 #define OPENPIC_IMASK 0x80000000 111 #define OPENPIC_ACTIVITY 0x40000000 112 #define OPENPIC_PRIORITY_MASK 0x000f0000 113 #define OPENPIC_PRIORITY_SHIFT 16 114 #define OPENPIC_VECTOR_MASK 0x000000ff 115 116 /* interrupt destination cpu */ 117 #ifndef OPENPIC_IDEST 118 #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 119 #endif 120 121 /* 122 * Per Processor Registers [global access] (0x20000 - 0x3ffff) 123 */ 124 125 #define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000) 126 127 #define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \ 128 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi)) 129 130 #define OPENPIC_PCPU_TPR(cpu) \ 131 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR) 132 133 #define OPENPIC_PCPU_WHOAMI(cpu) \ 134 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI) 135 136 #define OPENPIC_PCPU_IACK(cpu) \ 137 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK) 138 139 #define OPENPIC_PCPU_EOI(cpu) \ 140 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI) 141 142