1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Size of OpenPIC register space 34 */ 35 #define OPENPIC_SIZE 0x40000 36 37 /* 38 * Per Processor Registers [private access] (0x00000 - 0x00fff) 39 */ 40 41 /* IPI dispatch command reg */ 42 #define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10) 43 44 /* current task priority reg */ 45 #define OPENPIC_TPR 0x80 46 #define OPENPIC_TPR_MASK 0x0000000f 47 48 #define OPENPIC_WHOAMI 0x90 49 50 /* interrupt acknowledge reg */ 51 #define OPENPIC_IACK 0xa0 52 53 /* end of interrupt reg */ 54 #define OPENPIC_EOI 0xb0 55 56 /* 57 * Global registers (0x01000-0x0ffff) 58 */ 59 60 /* feature reporting reg 0 */ 61 #define OPENPIC_FEATURE 0x1000 62 #define OPENPIC_FEATURE_VERSION_MASK 0x000000ff 63 #define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 64 #define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 65 #define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 66 #define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 67 68 /* global config reg 0 */ 69 #define OPENPIC_CONFIG 0x1020 70 #define OPENPIC_CONFIG_RESET 0x80000000 71 #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 72 73 /* interrupt configuration mode (direct or serial) */ 74 #define OPENPIC_ICR 0x1030 75 #define OPENPIC_ICR_SERIAL_MODE (1 << 27) 76 #define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 77 #define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 78 79 /* vendor ID */ 80 #define OPENPIC_VENDOR_ID 0x1080 81 82 /* processor initialization reg */ 83 #define OPENPIC_PROC_INIT 0x1090 84 85 /* IPI vector/priority reg */ 86 #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 87 88 /* spurious intr. vector */ 89 #define OPENPIC_SPURIOUS_VECTOR 0x10e0 90 91 /* Timer registers */ 92 #define OPENPIC_TIMERS 4 93 #define OPENPIC_TFREQ 0x10f0 94 #define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40) 95 #define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40) 96 #define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40) 97 #define OPENPIC_TDST(t) (0x1130 + (t) * 0x40) 98 99 /* 100 * Interrupt Source Configuration Registers (0x10000 - 0x1ffff) 101 */ 102 103 /* interrupt vector/priority reg */ 104 #define OPENPIC_SRC_VECTOR_COUNT 64 105 #ifndef OPENPIC_SRC_VECTOR 106 #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 107 #endif 108 #define OPENPIC_SENSE_LEVEL 0x00400000 109 #define OPENPIC_SENSE_EDGE 0x00000000 110 #define OPENPIC_POLARITY_POSITIVE 0x00800000 111 #define OPENPIC_POLARITY_NEGATIVE 0x00000000 112 #define OPENPIC_IMASK 0x80000000 113 #define OPENPIC_ACTIVITY 0x40000000 114 #define OPENPIC_PRIORITY_MASK 0x000f0000 115 #define OPENPIC_PRIORITY_SHIFT 16 116 #define OPENPIC_VECTOR_MASK 0x000000ff 117 118 /* interrupt destination cpu */ 119 #ifndef OPENPIC_IDEST 120 #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 121 #endif 122 123 /* 124 * Per Processor Registers [global access] (0x20000 - 0x3ffff) 125 */ 126 127 #define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000) 128 129 #define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \ 130 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi)) 131 132 #define OPENPIC_PCPU_TPR(cpu) \ 133 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR) 134 135 #define OPENPIC_PCPU_WHOAMI(cpu) \ 136 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI) 137 138 #define OPENPIC_PCPU_IACK(cpu) \ 139 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK) 140 141 #define OPENPIC_PCPU_EOI(cpu) \ 142 (OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI) 143 144