1 /*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: openpicreg.h,v 1.2 2001/02/05 19:22:23 briggs Exp $ 27 * $FreeBSD$ 28 */ 29 30 /* 31 * GLOBAL/TIMER register (IDU base + 0x1000) 32 */ 33 34 /* feature reporting reg 0 */ 35 #define OPENPIC_FEATURE 0x1000 36 37 /* global config reg 0 */ 38 #define OPENPIC_CONFIG 0x1020 39 #define OPENPIC_CONFIG_RESET 0x80000000 40 #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 41 42 /* vendor ID */ 43 #define OPENPIC_VENDOR_ID 0x1080 44 45 /* processor initialization reg */ 46 #define OPENPIC_PROC_INIT 0x1090 47 48 /* IPI vector/priority reg */ 49 #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 50 51 /* spurious intr. vector */ 52 #define OPENPIC_SPURIOUS_VECTOR 0x10e0 53 54 55 /* 56 * INTERRUPT SOURCE register (IDU base + 0x10000) 57 */ 58 59 /* interrupt vector/priority reg */ 60 #ifndef OPENPIC_SRC_VECTOR 61 #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 62 #endif 63 #define OPENPIC_SENSE_LEVEL 0x00400000 64 #define OPENPIC_SENSE_EDGE 0x00000000 65 #define OPENPIC_POLARITY_POSITIVE 0x00800000 66 #define OPENPIC_POLARITY_NEGATIVE 0x00000000 67 #define OPENPIC_IMASK 0x80000000 68 #define OPENPIC_ACTIVITY 0x40000000 69 #define OPENPIC_PRIORITY_MASK 0x000f0000 70 #define OPENPIC_PRIORITY_SHIFT 16 71 #define OPENPIC_VECTOR_MASK 0x000000ff 72 73 /* interrupt destination cpu */ 74 #ifndef OPENPIC_IDEST 75 #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 76 #endif 77 78 /* 79 * PROCESSOR register (IDU base + 0x20000) 80 */ 81 82 /* IPI command reg */ 83 #define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi)) 84 85 /* current task priority reg */ 86 #define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 87 #define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 88 89 /* interrupt acknowledge reg */ 90 #define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 91 92 /* end of interrupt reg */ 93 #define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 94