1 /*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $ 27 * $FreeBSD$ 28 */ 29 30 #ifndef _POWERPC_HID_H_ 31 #define _POWERPC_HID_H_ 32 33 /* Hardware Implementation Dependent registers for the PowerPC */ 34 35 #define HID0_EMCP 0x80000000 /* Enable MCP */ 36 #define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ 37 #define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ 38 #define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ 39 #define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ 40 #define HID0_EICE 0x04000000 /* Enable ICE output */ 41 #define HID0_TBEN 0x04000000 /* Time base enable (7450) */ 42 #define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ 43 #define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ 44 #define HID0_STEN 0x01000000 /* Software table search enable (7450) */ 45 #define HID0_DOZE 0x00800000 /* Enable doze mode */ 46 #define HID0_NAP 0x00400000 /* Enable nap mode */ 47 #define HID0_SLEEP 0x00200000 /* Enable sleep mode */ 48 #define HID0_DPM 0x00100000 /* Enable Dynamic power management */ 49 #define HID0_RISEG 0x00080000 /* Read I-SEG */ 50 #define HID0_BHTCLR 0x00080000 /* Clear branch history table (7450) */ 51 #define HID0_EIEC 0x00040000 /* Enable internal error checking */ 52 #define HID0_XAEN 0x00040000 /* Enable eXtended Addressing (7450) */ 53 #define HID0_NHR 0x00010000 /* Not hard reset */ 54 #define HID0_ICE 0x00008000 /* Enable i-cache */ 55 #define HID0_DCE 0x00004000 /* Enable d-cache */ 56 #define HID0_ILOCK 0x00002000 /* i-cache lock */ 57 #define HID0_DLOCK 0x00001000 /* d-cache lock */ 58 #define HID0_ICFI 0x00000800 /* i-cache flush invalidate */ 59 #define HID0_DCFI 0x00000400 /* d-cache flush invalidate */ 60 #define HID0_SPD 0x00000200 /* Disable speculative cache access */ 61 #define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */ 62 #define HID0_SGE 0x00000080 /* Enable store gathering */ 63 #define HID0_DCFA 0x00000040 /* Data cache flush assist */ 64 #define HID0_BTIC 0x00000020 /* Enable BTIC */ 65 #define HID0_ABE 0x00000008 /* Enable address broadcast */ 66 #define HID0_BHT 0x00000004 /* Enable branch history table */ 67 #define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ 68 69 #define HID0_BITMASK \ 70 "\20" \ 71 "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \ 72 "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \ 73 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \ 74 "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI" 75 76 #define HID0_7450_BITMASK \ 77 "\20" \ 78 "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \ 79 "\030b8\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \ 80 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011b23" \ 81 "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI" 82 83 /* 84 * HID0 bit definitions per cpu model 85 * 86 * bit 603 604 750 7400 7410 7450 87 * 0 EMCP EMCP EMCP EMCP EMCP - 88 * 1 - ECP DBP - - - 89 * 2 EBA EBA EBA EBA EDA - 90 * 3 EBD EBD EBD EBD EBD - 91 * 4 SBCLK - BCLK BCKL BCLK - 92 * 5 EICE - - - - TBEN 93 * 6 ECLK - ECLK ECLK ECLK - 94 * 7 PAR PAR PAR PAR PAR STEN 95 * 8 DOZE - DOZE DOZE DOZE - 96 * 9 NAP - NAP NAP NAP NAP 97 * 10 SLEEP - SLEEP SLEEP SLEEP SLEEP 98 * 11 DPM - DPM DPM DPM DPM 99 * 12 RISEG - - RISEG - - 100 * 13 - - - EIEC EIEC BHTCLR 101 * 14 - - - - - XAEN 102 * 15 - NHR NHR NHR NHR NHR 103 * 16 ICE ICE ICE ICE ICE ICE 104 * 17 DCE DCE DCE DCE DCE DCE 105 * 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK 106 * 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK 107 * 20 ICFI ICFI ICFI ICFI ICFI ICFI 108 * 21 DCFI DCFI DCFI DCFI DCFI DCFI 109 * 22 - - SPD SPD SPG SPD 110 * 23 - - IFEM IFTT IFTT - 111 * 24 - SIE SGE SGE SGE SGE 112 * 25 - - DCFA DCFA DCFA - 113 * 26 - - BTIC BTIC BTIC BTIC 114 * 27 FBIOB - - - - LRSTK 115 * 28 - - ABE - - FOLD 116 * 29 - BHT BHT BHT BHT BHT 117 * 30 - - - NOPDST NOPDST NOPDST 118 * 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI 119 * 120 * 604: ECP = Enable cache parity checking 121 * 604: SIE = Serial instruction execution disable 122 * 7450: TBEN = Time Base Enable 123 * 7450: STEN = Software table lookup enable 124 * 7450: BHTCLR = Branch history clear 125 * 7450: LRSTK = Link Register Stack Enable 126 * 7450: FOLD = Branch folding enable 127 */ 128 129 #endif /* _POWERPC_HID_H_ */ 130