1 /*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $ 27 * $FreeBSD$ 28 */ 29 30 #ifndef _POWERPC_HID_H_ 31 #define _POWERPC_HID_H_ 32 33 /* Hardware Implementation Dependent registers for the PowerPC */ 34 35 #define HID0_EMCP 0x80000000 /* Enable machine check pin */ 36 #define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ 37 #define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ 38 #define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ 39 #define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ 40 #define HID0_EICE 0x04000000 /* Enable ICE output */ 41 #define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ 42 #define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ 43 #define HID0_STEN 0x01000000 /* Software table search enable (7450) */ 44 #define HID0_DEEPNAP 0x01000000 /* Enable deep nap mode (970) */ 45 #define HID0_HBATEN 0x00800000 /* High BAT enable (74[45][578]) */ 46 #define HID0_DOZE 0x00800000 /* Enable doze mode */ 47 #define HID0_NAP 0x00400000 /* Enable nap mode */ 48 #define HID0_SLEEP 0x00200000 /* Enable sleep mode */ 49 #define HID0_DPM 0x00100000 /* Enable Dynamic power management */ 50 #define HID0_RISEG 0x00080000 /* Read I-SEG */ 51 #define HID0_TG 0x00040000 /* Timebase Granularity (OEA64) */ 52 #define HID0_BHTCLR 0x00040000 /* Clear branch history table (7450) */ 53 #define HID0_EIEC 0x00040000 /* Enable internal error checking */ 54 #define HID0_XAEN 0x00020000 /* Enable eXtended Addressing (7450) */ 55 #define HID0_NHR 0x00010000 /* Not hard reset */ 56 #define HID0_ICE 0x00008000 /* Enable i-cache */ 57 #define HID0_DCE 0x00004000 /* Enable d-cache */ 58 #define HID0_ILOCK 0x00002000 /* i-cache lock */ 59 #define HID0_DLOCK 0x00001000 /* d-cache lock */ 60 #define HID0_ICFI 0x00000800 /* i-cache flush invalidate */ 61 #define HID0_DCFI 0x00000400 /* d-cache flush invalidate */ 62 #define HID0_SPD 0x00000200 /* Disable speculative cache access */ 63 #define HID0_XBSEN 0x00000100 /* Extended BAT block-size enable (7457) */ 64 #define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */ 65 #define HID0_XBSEN 0x00000100 /* Extended BAT block size enable (7455+)*/ 66 #define HID0_SGE 0x00000080 /* Enable store gathering */ 67 #define HID0_DCFA 0x00000040 /* Data cache flush assist */ 68 #define HID0_BTIC 0x00000020 /* Enable BTIC */ 69 #define HID0_LRSTK 0x00000010 /* Link register stack enable (7450) */ 70 #define HID0_ABE 0x00000008 /* Enable address broadcast */ 71 #define HID0_FOLD 0x00000008 /* Branch folding enable (7450) */ 72 #define HID0_BHT 0x00000004 /* Enable branch history table */ 73 #define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ 74 75 #define HID0_AIM_TBEN 0x04000000 /* Time base enable (7450) */ 76 77 #define HID0_E500_TBEN 0x00004000 /* Time Base and decr. enable */ 78 #define HID0_E500_SEL_TBCLK 0x00002000 /* Select Time Base clock */ 79 #define HID0_E500_MAS7UPDEN 0x00000080 /* Enable MAS7 update (e500v2) */ 80 81 #define HID0_E500MC_L2MMU_MHD 0x40000000 /* L2MMU Multiple Hit Detection */ 82 83 #define HID0_BITMASK \ 84 "\20" \ 85 "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \ 86 "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \ 87 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \ 88 "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI" 89 90 #define HID0_7450_BITMASK \ 91 "\20" \ 92 "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \ 93 "\030HBATEN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \ 94 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \ 95 "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI" 96 97 #define HID0_E500_BITMASK \ 98 "\20" \ 99 "\040EMCP\037b1\036b2\035b3\034b4\033b5\032b6\031b7" \ 100 "\030DOZE\027NAP\026SLEEP\025b11\024b12\023b13\022b14\021b15" \ 101 "\020b16\017TBEN\016SEL_TBCLK\015b19\014b20\013b21\012b22\011b23" \ 102 "\010EN_MAS7_UPDATE\007DCFA\006b26\005b27\004b28\003b29\002b30\001NOPTI" 103 104 #define HID0_970_BITMASK \ 105 "\20" \ 106 "\040ONEPPC\037SINGLE\036ISYNCSC\035SERGP\031DEEPNAP\030DOZE" \ 107 "\027NAP\025DPM\023TG\022HANGDETECT\021NHR\020INORDER" \ 108 "\016TBCTRL\015TBEN\012CIABREN\011HDICEEN\001ENATTN" 109 110 #define HID0_E500MC_BITMASK \ 111 "\20" \ 112 "\040EMCP\037EN_L2MMU_MHD\036b2\035b3\034b4\033b5\032b6\031b7" \ 113 "\030b8\027b9\026b10\025b11\024b12\023b13\022b14\021b15" \ 114 "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23" \ 115 "\010EN_MAS7_UPDATE\007DCFA\006b26\005CIGLSO\004b28\003b29\002b30\001NOPTI" 116 117 #define HID0_E5500_BITMASK \ 118 "\20" \ 119 "\040EMCP\037EN_L2MMU_MHD\036b2\035b3\034b4\033b5\032b6\031b7" \ 120 "\030b8\027b9\026b10\025b11\024b12\023b13\022b14\021b15" \ 121 "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23" \ 122 "\010b24\007DCFA\006b26\005CIGLSO\004b28\003b29\002b30\001NOPTI" 123 124 /* 125 * HID0 bit definitions per cpu model 126 * 127 * bit 603 604 750 7400 7410 7450 7457 e500 128 * 0 EMCP EMCP EMCP EMCP EMCP - - EMCP 129 * 1 - ECP DBP - - - - - 130 * 2 EBA EBA EBA EBA EDA - - - 131 * 3 EBD EBD EBD EBD EBD - - - 132 * 4 SBCLK - BCLK BCKL BCLK - - - 133 * 5 EICE - - - - TBEN TBEN - 134 * 6 ECLK - ECLK ECLK ECLK - - - 135 * 7 PAR PAR PAR PAR PAR STEN STEN - 136 * 8 DOZE - DOZE DOZE DOZE - HBATEN DOZE 137 * 9 NAP - NAP NAP NAP NAP NAP NAP 138 * 10 SLEEP - SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP 139 * 11 DPM - DPM DPM DPM DPM DPM - 140 * 12 RISEG - - RISEG - - - - 141 * 13 - - - EIEC EIEC BHTCLR BHTCLR - 142 * 14 - - - - - XAEN XAEN - 143 * 15 - NHR NHR NHR NHR NHR NHR - 144 * 16 ICE ICE ICE ICE ICE ICE ICE - 145 * 17 DCE DCE DCE DCE DCE DCE DCE TBEN 146 * 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK SEL_TBCLK 147 * 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK - 148 * 20 ICFI ICFI ICFI ICFI ICFI ICFI ICFI - 149 * 21 DCFI DCFI DCFI DCFI DCFI DCFI DCFI - 150 * 22 - - SPD SPD SPG SPD SPD - 151 * 23 - - IFEM IFTT IFTT - XBSEN - 152 * 24 - SIE SGE SGE SGE SGE SGE EN_MAS7_UPDATE 153 * 25 - - DCFA DCFA DCFA - - DCFA 154 * 26 - - BTIC BTIC BTIC BTIC BTIC - 155 * 27 FBIOB - - - - LRSTK LRSTK - 156 * 28 - - ABE - - FOLD FOLD - 157 * 29 - BHT BHT BHT BHT BHT BHT - 158 * 30 - - - NOPDST NOPDST NOPDST NOPDST - 159 * 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI NOPTI NOPTI 160 * 161 * bit e500mc e5500 162 * 0 EMCP EMCP 163 * 1 EN_L2MMU_MHD EN_L2MMU_MHD 164 * 2 - - 165 * 3 - - 166 * 4 - - 167 * 5 - - 168 * 6 - - 169 * 7 - - 170 * 8 - - 171 * 9 - - 172 * 10 - - 173 * 11 - - 174 * 12 - - 175 * 13 - - 176 * 14 - - 177 * 15 - - 178 * 16 - - 179 * 17 - - 180 * 18 - - 181 * 19 - - 182 * 20 - - 183 * 21 - - 184 * 22 - - 185 * 23 - - 186 * 24 EN_MAS7_UPDATE - 187 * 25 DCFA DCFA 188 * 26 - - 189 * 27 CIGLSO CIGLSO 190 * 28 - - 191 * 29 - - 192 * 30 - - 193 * 31 NOPTI NOPTI 194 * 195 * 604: ECP = Enable cache parity checking 196 * 604: SIE = Serial instruction execution disable 197 * 7450: TBEN = Time Base Enable 198 * 7450: STEN = Software table lookup enable 199 * 7450: BHTCLR = Branch history clear 200 * 7450: XAEN = Extended Addressing Enabled 201 * 7450: LRSTK = Link Register Stack Enable 202 * 7450: FOLD = Branch folding enable 203 * 7457: HBATEN = High BAT Enable 204 * 7457: XBSEN = Extended BAT Block Size Enable 205 */ 206 207 #define HID1_E500_ABE 0x00001000 /* Address broadcast enable */ 208 #define HID1_E500_ASTME 0x00002000 /* Address bus streaming mode enable */ 209 #define HID1_E500_RFXE 0x00020000 /* Read fault exception enable */ 210 211 #define HID0_E500_DEFAULT_SET (HID0_EMCP | HID0_E500_TBEN | \ 212 HID0_E500_MAS7UPDEN) 213 #define HID1_E500_DEFAULT_SET (HID1_E500_ABE | HID1_E500_ASTME) 214 #define HID0_E500MC_DEFAULT_SET (HID0_EMCP | HID0_E500MC_L2MMU_MHD | \ 215 HID0_E500_MAS7UPDEN) 216 #define HID0_E5500_DEFAULT_SET (HID0_EMCP | HID0_E500MC_L2MMU_MHD) 217 218 #define HID5_970_DCBZ_SIZE_HI 0x00000080UL /* dcbz does a 32-byte store */ 219 #define HID4_970_DISABLE_LG_PG 0x00000004ULL /* disables large pages */ 220 221 #endif /* _POWERPC_HID_H_ */ 222