1f9bac91bSBenno Rice /*- 251369649SPedro F. Giffuni * SPDX-License-Identifier: BSD-4-Clause 351369649SPedro F. Giffuni * 4f9bac91bSBenno Rice * Copyright (C) 1996 Wolfgang Solfrank. 5f9bac91bSBenno Rice * Copyright (C) 1996 TooLs GmbH. 6f9bac91bSBenno Rice * All rights reserved. 7f9bac91bSBenno Rice * 8f9bac91bSBenno Rice * Redistribution and use in source and binary forms, with or without 9f9bac91bSBenno Rice * modification, are permitted provided that the following conditions 10f9bac91bSBenno Rice * are met: 11f9bac91bSBenno Rice * 1. Redistributions of source code must retain the above copyright 12f9bac91bSBenno Rice * notice, this list of conditions and the following disclaimer. 13f9bac91bSBenno Rice * 2. Redistributions in binary form must reproduce the above copyright 14f9bac91bSBenno Rice * notice, this list of conditions and the following disclaimer in the 15f9bac91bSBenno Rice * documentation and/or other materials provided with the distribution. 16f9bac91bSBenno Rice * 3. All advertising materials mentioning features or use of this software 17f9bac91bSBenno Rice * must display the following acknowledgement: 18f9bac91bSBenno Rice * This product includes software developed by TooLs GmbH. 19f9bac91bSBenno Rice * 4. The name of TooLs GmbH may not be used to endorse or promote products 20f9bac91bSBenno Rice * derived from this software without specific prior written permission. 21f9bac91bSBenno Rice * 22f9bac91bSBenno Rice * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 23f9bac91bSBenno Rice * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24f9bac91bSBenno Rice * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25f9bac91bSBenno Rice * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26f9bac91bSBenno Rice * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 27f9bac91bSBenno Rice * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 28f9bac91bSBenno Rice * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29f9bac91bSBenno Rice * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 30f9bac91bSBenno Rice * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 31f9bac91bSBenno Rice * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32f9bac91bSBenno Rice * 33f9bac91bSBenno Rice * $NetBSD: fpu.h,v 1.2 1999/12/07 15:14:56 danw Exp $ 34f9bac91bSBenno Rice */ 35f9bac91bSBenno Rice 36f9bac91bSBenno Rice #ifndef _MACHINE_FPU_H_ 37f9bac91bSBenno Rice #define _MACHINE_FPU_H_ 38f9bac91bSBenno Rice 39f9bac91bSBenno Rice #define FPSCR_FX 0x80000000 40f9bac91bSBenno Rice #define FPSCR_FEX 0x40000000 41f9bac91bSBenno Rice #define FPSCR_VX 0x20000000 42f9bac91bSBenno Rice #define FPSCR_OX 0x10000000 43f9bac91bSBenno Rice #define FPSCR_UX 0x08000000 44f9bac91bSBenno Rice #define FPSCR_ZX 0x04000000 45f9bac91bSBenno Rice #define FPSCR_XX 0x02000000 46f9bac91bSBenno Rice #define FPSCR_VXSNAN 0x01000000 47f9bac91bSBenno Rice #define FPSCR_VXISI 0x00800000 48f9bac91bSBenno Rice #define FPSCR_VXIDI 0x00400000 49f9bac91bSBenno Rice #define FPSCR_VXZDZ 0x00200000 50f9bac91bSBenno Rice #define FPSCR_VXIMZ 0x00100000 51f9bac91bSBenno Rice #define FPSCR_VXVC 0x00080000 52f9bac91bSBenno Rice #define FPSCR_FR 0x00040000 53f9bac91bSBenno Rice #define FPSCR_FI 0x00020000 54f9bac91bSBenno Rice #define FPSCR_FPRF 0x0001f000 55f9bac91bSBenno Rice #define FPSCR_C 0x00010000 56f9bac91bSBenno Rice #define FPSCR_FPCC 0x0000f000 57f9bac91bSBenno Rice #define FPSCR_FL 0x00008000 58f9bac91bSBenno Rice #define FPSCR_FG 0x00004000 59f9bac91bSBenno Rice #define FPSCR_FE 0x00002000 60f9bac91bSBenno Rice #define FPSCR_FU 0x00001000 61f9bac91bSBenno Rice #define FPSCR_VXSOFT 0x00000400 62f9bac91bSBenno Rice #define FPSCR_VXSQRT 0x00000200 63f9bac91bSBenno Rice #define FPSCR_VXCVI 0x00000100 64f9bac91bSBenno Rice #define FPSCR_VE 0x00000080 65f9bac91bSBenno Rice #define FPSCR_OE 0x00000040 66f9bac91bSBenno Rice #define FPSCR_UE 0x00000020 67f9bac91bSBenno Rice #define FPSCR_ZE 0x00000010 68f9bac91bSBenno Rice #define FPSCR_XE 0x00000008 69f9bac91bSBenno Rice #define FPSCR_NI 0x00000004 70f9bac91bSBenno Rice #define FPSCR_RN 0x00000003 71f9bac91bSBenno Rice 72eeaa8979SBenno Rice #ifdef _KERNEL 73eeaa8979SBenno Rice 74eeaa8979SBenno Rice void enable_fpu(struct thread *); 75eeaa8979SBenno Rice void save_fpu(struct thread *); 762e655675SJustin Hibbits void save_fpu_nodrop(struct thread *); 775d0e8619SAlfredo Dal'Ava Junior void cleanup_fpscr(void); 785d0e8619SAlfredo Dal'Ava Junior u_int get_fpu_exception(struct thread *); 79*a6662c37SShawn Anastasio void enable_fpu_kern(void); 80*a6662c37SShawn Anastasio void disable_fpu(struct thread *td); 81*a6662c37SShawn Anastasio 82*a6662c37SShawn Anastasio /* 83*a6662c37SShawn Anastasio * Flags for fpu_kern_alloc_ctx(), fpu_kern_enter() and fpu_kern_thread(). 84*a6662c37SShawn Anastasio */ 85*a6662c37SShawn Anastasio #define FPU_KERN_NORMAL 0x0000 86*a6662c37SShawn Anastasio #define FPU_KERN_NOWAIT 0x0001 87*a6662c37SShawn Anastasio #define FPU_KERN_KTHR 0x0002 88*a6662c37SShawn Anastasio #define FPU_KERN_NOCTX 0x0004 89*a6662c37SShawn Anastasio 90*a6662c37SShawn Anastasio struct fpu_kern_ctx; 91*a6662c37SShawn Anastasio 92*a6662c37SShawn Anastasio struct fpu_kern_ctx *fpu_kern_alloc_ctx(u_int flags); 93*a6662c37SShawn Anastasio void fpu_kern_free_ctx(struct fpu_kern_ctx *ctx); 94*a6662c37SShawn Anastasio void fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, 95*a6662c37SShawn Anastasio u_int flags); 96*a6662c37SShawn Anastasio int fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx); 97*a6662c37SShawn Anastasio int fpu_kern_thread(u_int flags); 98*a6662c37SShawn Anastasio int is_fpu_kern_thread(u_int flags); 995d8dd7e6SMarcel Moolenaar 100eeaa8979SBenno Rice #endif /* _KERNEL */ 101eeaa8979SBenno Rice 102f9bac91bSBenno Rice #endif /* _MACHINE_FPU_H_ */ 103