xref: /freebsd/sys/powerpc/include/cpu.h (revision 9a7fefa51e8c3ae788d9aef8d7b291db612d0de0)
1f9bac91bSBenno Rice /*
2f9bac91bSBenno Rice  * Copyright (C) 1995-1997 Wolfgang Solfrank.
3f9bac91bSBenno Rice  * Copyright (C) 1995-1997 TooLs GmbH.
4f9bac91bSBenno Rice  * All rights reserved.
5f9bac91bSBenno Rice  *
6f9bac91bSBenno Rice  * Redistribution and use in source and binary forms, with or without
7f9bac91bSBenno Rice  * modification, are permitted provided that the following conditions
8f9bac91bSBenno Rice  * are met:
9f9bac91bSBenno Rice  * 1. Redistributions of source code must retain the above copyright
10f9bac91bSBenno Rice  *    notice, this list of conditions and the following disclaimer.
11f9bac91bSBenno Rice  * 2. Redistributions in binary form must reproduce the above copyright
12f9bac91bSBenno Rice  *    notice, this list of conditions and the following disclaimer in the
13f9bac91bSBenno Rice  *    documentation and/or other materials provided with the distribution.
14f9bac91bSBenno Rice  * 3. All advertising materials mentioning features or use of this software
15f9bac91bSBenno Rice  *    must display the following acknowledgement:
16f9bac91bSBenno Rice  *	This product includes software developed by TooLs GmbH.
17f9bac91bSBenno Rice  * 4. The name of TooLs GmbH may not be used to endorse or promote products
18f9bac91bSBenno Rice  *    derived from this software without specific prior written permission.
19f9bac91bSBenno Rice  *
20f9bac91bSBenno Rice  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21f9bac91bSBenno Rice  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22f9bac91bSBenno Rice  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23f9bac91bSBenno Rice  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24f9bac91bSBenno Rice  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25f9bac91bSBenno Rice  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26f9bac91bSBenno Rice  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27f9bac91bSBenno Rice  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28f9bac91bSBenno Rice  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29f9bac91bSBenno Rice  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30f9bac91bSBenno Rice  *
31f9bac91bSBenno Rice  *	$NetBSD: cpu.h,v 1.11 2000/05/26 21:19:53 thorpej Exp $
32f9bac91bSBenno Rice  * $FreeBSD$
33f9bac91bSBenno Rice  */
34f9bac91bSBenno Rice 
35f9bac91bSBenno Rice #ifndef _MACHINE_CPU_H_
36f9bac91bSBenno Rice #define	_MACHINE_CPU_H_
37f9bac91bSBenno Rice 
38f9bac91bSBenno Rice #include <machine/frame.h>
39f9bac91bSBenno Rice #include <machine/pcb.h>
40f9bac91bSBenno Rice #include <machine/psl.h>
41f9bac91bSBenno Rice 
42f9bac91bSBenno Rice #define	CLKF_USERMODE(frame)	(((frame)->srr1 & PSL_PR) != 0)
43f9bac91bSBenno Rice #define	CLKF_BASEPRI(frame)	((frame)->pri == 0)
44f9bac91bSBenno Rice #define	CLKF_PC(frame)		((frame)->srr0)
45f9bac91bSBenno Rice #define	CLKF_INTR(frame)	((frame)->depth > 0)
46f9bac91bSBenno Rice 
479a7fefa5SBenno Rice #define	TRAPF_USERMODE(frame)	(((frame)->srr1 & PSL_PR) != 0)
48c791ba59SBenno Rice #define	TRAPF_PC(frame)		((frame)->srr0)
49c791ba59SBenno Rice 
50f9bac91bSBenno Rice #define	cpu_swapout(p)
51f9bac91bSBenno Rice #define	cpu_number()		0
52f9bac91bSBenno Rice 
53d163144bSBenno Rice void	delay(int);
54f9bac91bSBenno Rice #define	DELAY(n)		delay(n)
55f9bac91bSBenno Rice 
56f9bac91bSBenno Rice extern char bootpath[];
57f9bac91bSBenno Rice 
58f9bac91bSBenno Rice #if defined(_KERNEL) || defined(_STANDALONE)
59f9bac91bSBenno Rice #define	CACHELINESIZE	32
60f9bac91bSBenno Rice #endif
61f9bac91bSBenno Rice 
62f9bac91bSBenno Rice extern void __syncicache __P((void *, int));
63f9bac91bSBenno Rice 
64f9bac91bSBenno Rice /*
65f9bac91bSBenno Rice  * CTL_MACHDEP definitions.
66f9bac91bSBenno Rice  */
67f9bac91bSBenno Rice #define	CPU_CACHELINE	1
68f9bac91bSBenno Rice #define	CPU_MAXID	2
69f9bac91bSBenno Rice #define CPU_CONSDEV	1
70f9bac91bSBenno Rice 
71f9bac91bSBenno Rice #define	CTL_MACHDEP_NAMES { \
72f9bac91bSBenno Rice 	{ 0, 0 }, \
73f9bac91bSBenno Rice 	{ "cachelinesize", CTLTYPE_INT }, \
74f9bac91bSBenno Rice }
75f9bac91bSBenno Rice 
76f9bac91bSBenno Rice static __inline u_int64_t
77f9bac91bSBenno Rice get_cyclecount(void)
78f9bac91bSBenno Rice {
79f9bac91bSBenno Rice 	u_int32_t upper, lower;
80f9bac91bSBenno Rice 	u_int64_t time;
81f9bac91bSBenno Rice 
82f9bac91bSBenno Rice 	__asm __volatile(
83f9bac91bSBenno Rice 		"mftb %0\n"
84f9bac91bSBenno Rice 		"mftbu %1"
85f9bac91bSBenno Rice 		: "=r" (lower), "=r" (upper));
86f9bac91bSBenno Rice 
87f9bac91bSBenno Rice 	time = (u_int64_t)upper;
88f9bac91bSBenno Rice 	time = (time << 32) + lower;
89f9bac91bSBenno Rice 	return (time);
90f9bac91bSBenno Rice }
91f9bac91bSBenno Rice 
925fd2c51eSMark Peek #define	cpu_getstack(td)	((td)->td_frame->fixreg[1])
93f9bac91bSBenno Rice 
94f9bac91bSBenno Rice void	savectx __P((struct pcb *));
95d163144bSBenno Rice void	fork_trampoline(void);
96f9bac91bSBenno Rice 
97f9bac91bSBenno Rice #endif	/* _MACHINE_CPU_H_ */
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