1 /* $NetBSD: fpu_subr.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */ 2 3 /* 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 */ 42 43 /* 44 * FPU subroutines. 45 */ 46 47 #include <sys/types.h> 48 #include <sys/systm.h> 49 50 #include <machine/fpu.h> 51 52 #include <powerpc/fpu/fpu_arith.h> 53 #include <powerpc/fpu/fpu_emu.h> 54 55 /* 56 * Shift the given number right rsh bits. Any bits that `fall off' will get 57 * shoved into the sticky field; we return the resulting sticky. Note that 58 * shifting NaNs is legal (this will never shift all bits out); a NaN's 59 * sticky field is ignored anyway. 60 */ 61 int 62 fpu_shr(struct fpn *fp, int rsh) 63 { 64 u_int m0, m1, m2, m3, s; 65 int lsh; 66 67 #ifdef DIAGNOSTIC 68 if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp))) 69 panic("fpu_rightshift 1"); 70 #endif 71 72 m0 = fp->fp_mant[0]; 73 m1 = fp->fp_mant[1]; 74 m2 = fp->fp_mant[2]; 75 m3 = fp->fp_mant[3]; 76 77 /* If shifting all the bits out, take a shortcut. */ 78 if (rsh >= FP_NMANT) { 79 #ifdef DIAGNOSTIC 80 if ((m0 | m1 | m2 | m3) == 0) 81 panic("fpu_rightshift 2"); 82 #endif 83 fp->fp_mant[0] = 0; 84 fp->fp_mant[1] = 0; 85 fp->fp_mant[2] = 0; 86 fp->fp_mant[3] = 0; 87 #ifdef notdef 88 if ((m0 | m1 | m2 | m3) == 0) 89 fp->fp_class = FPC_ZERO; 90 else 91 #endif 92 fp->fp_sticky = 1; 93 return (1); 94 } 95 96 /* Squish out full words. */ 97 s = fp->fp_sticky; 98 if (rsh >= 32 * 3) { 99 s |= m3 | m2 | m1; 100 m3 = m0, m2 = 0, m1 = 0, m0 = 0; 101 } else if (rsh >= 32 * 2) { 102 s |= m3 | m2; 103 m3 = m1, m2 = m0, m1 = 0, m0 = 0; 104 } else if (rsh >= 32) { 105 s |= m3; 106 m3 = m2, m2 = m1, m1 = m0, m0 = 0; 107 } 108 109 /* Handle any remaining partial word. */ 110 if ((rsh &= 31) != 0) { 111 lsh = 32 - rsh; 112 s |= m3 << lsh; 113 m3 = (m3 >> rsh) | (m2 << lsh); 114 m2 = (m2 >> rsh) | (m1 << lsh); 115 m1 = (m1 >> rsh) | (m0 << lsh); 116 m0 >>= rsh; 117 } 118 fp->fp_mant[0] = m0; 119 fp->fp_mant[1] = m1; 120 fp->fp_mant[2] = m2; 121 fp->fp_mant[3] = m3; 122 fp->fp_sticky = s; 123 return (s); 124 } 125 126 /* 127 * Force a number to be normal, i.e., make its fraction have all zero 128 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms 129 * and (sometimes) for intermediate results. 130 * 131 * Internally, this may use a `supernormal' -- a number whose fp_mant 132 * is greater than or equal to 2.0 -- so as a side effect you can hand it 133 * a supernormal and it will fix it (provided fp->fp_mant[3] == 0). 134 */ 135 void 136 fpu_norm(struct fpn *fp) 137 { 138 u_int m0, m1, m2, m3, top, sup, nrm; 139 int lsh, rsh, exp; 140 141 exp = fp->fp_exp; 142 m0 = fp->fp_mant[0]; 143 m1 = fp->fp_mant[1]; 144 m2 = fp->fp_mant[2]; 145 m3 = fp->fp_mant[3]; 146 147 /* Handle severe subnormals with 32-bit moves. */ 148 if (m0 == 0) { 149 if (m1) 150 m0 = m1, m1 = m2, m2 = m3, m3 = 0, exp -= 32; 151 else if (m2) 152 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32; 153 else if (m3) 154 m0 = m3, m1 = 0, m2 = 0, m3 = 0, exp -= 3 * 32; 155 else { 156 fp->fp_class = FPC_ZERO; 157 return; 158 } 159 } 160 161 /* Now fix any supernormal or remaining subnormal. */ 162 nrm = FP_1; 163 sup = nrm << 1; 164 if (m0 >= sup) { 165 /* 166 * We have a supernormal number. We need to shift it right. 167 * We may assume m3==0. 168 */ 169 for (rsh = 1, top = m0 >> 1; top >= sup; rsh++) /* XXX slow */ 170 top >>= 1; 171 exp += rsh; 172 lsh = 32 - rsh; 173 m3 = m2 << lsh; 174 m2 = (m2 >> rsh) | (m1 << lsh); 175 m1 = (m1 >> rsh) | (m0 << lsh); 176 m0 = top; 177 } else if (m0 < nrm) { 178 /* 179 * We have a regular denorm (a subnormal number), and need 180 * to shift it left. 181 */ 182 for (lsh = 1, top = m0 << 1; top < nrm; lsh++) /* XXX slow */ 183 top <<= 1; 184 exp -= lsh; 185 rsh = 32 - lsh; 186 m0 = top | (m1 >> rsh); 187 m1 = (m1 << lsh) | (m2 >> rsh); 188 m2 = (m2 << lsh) | (m3 >> rsh); 189 m3 <<= lsh; 190 } 191 192 fp->fp_exp = exp; 193 fp->fp_mant[0] = m0; 194 fp->fp_mant[1] = m1; 195 fp->fp_mant[2] = m2; 196 fp->fp_mant[3] = m3; 197 } 198 199 /* 200 * Concoct a `fresh' Quiet NaN per Appendix N. 201 * As a side effect, we set NV (invalid) for the current exceptions. 202 */ 203 struct fpn * 204 fpu_newnan(struct fpemu *fe) 205 { 206 struct fpn *fp; 207 208 fe->fe_cx |= FPSCR_VXSNAN; 209 fp = &fe->fe_f3; 210 fp->fp_class = FPC_QNAN; 211 fp->fp_sign = 0; 212 fp->fp_mant[0] = FP_1 - 1; 213 fp->fp_mant[1] = fp->fp_mant[2] = fp->fp_mant[3] = ~0; 214 DUMPFPN(FPE_REG, fp); 215 return (fp); 216 } 217