1 /* $NetBSD: fpu_mul.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */ 2 3 /* 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_mul.c 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * Perform an FPU multiply (return x * y). 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/fpu.h> 56 57 #include <powerpc/fpu/fpu_arith.h> 58 #include <powerpc/fpu/fpu_emu.h> 59 60 /* 61 * The multiplication algorithm for normal numbers is as follows: 62 * 63 * The fraction of the product is built in the usual stepwise fashion. 64 * Each step consists of shifting the accumulator right one bit 65 * (maintaining any guard bits) and, if the next bit in y is set, 66 * adding the multiplicand (x) to the accumulator. Then, in any case, 67 * we advance one bit leftward in y. Algorithmically: 68 * 69 * A = 0; 70 * for (bit = 0; bit < FP_NMANT; bit++) { 71 * sticky |= A & 1, A >>= 1; 72 * if (Y & (1 << bit)) 73 * A += X; 74 * } 75 * 76 * (X and Y here represent the mantissas of x and y respectively.) 77 * The resultant accumulator (A) is the product's mantissa. It may 78 * be as large as 11.11111... in binary and hence may need to be 79 * shifted right, but at most one bit. 80 * 81 * Since we do not have efficient multiword arithmetic, we code the 82 * accumulator as four separate words, just like any other mantissa. 83 * We use local variables in the hope that this is faster than memory. 84 * We keep x->fp_mant in locals for the same reason. 85 * 86 * In the algorithm above, the bits in y are inspected one at a time. 87 * We will pick them up 32 at a time and then deal with those 32, one 88 * at a time. Note, however, that we know several things about y: 89 * 90 * - the guard and round bits at the bottom are sure to be zero; 91 * 92 * - often many low bits are zero (y is often from a single or double 93 * precision source); 94 * 95 * - bit FP_NMANT-1 is set, and FP_1*2 fits in a word. 96 * 97 * We can also test for 32-zero-bits swiftly. In this case, the center 98 * part of the loop---setting sticky, shifting A, and not adding---will 99 * run 32 times without adding X to A. We can do a 32-bit shift faster 100 * by simply moving words. Since zeros are common, we optimize this case. 101 * Furthermore, since A is initially zero, we can omit the shift as well 102 * until we reach a nonzero word. 103 */ 104 struct fpn * 105 fpu_mul(struct fpemu *fe) 106 { 107 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 108 u_int a3, a2, a1, a0, x3, x2, x1, x0, bit, m; 109 int sticky; 110 FPU_DECL_CARRY; 111 112 /* 113 * Put the `heavier' operand on the right (see fpu_emu.h). 114 * Then we will have one of the following cases, taken in the 115 * following order: 116 * 117 * - y = NaN. Implied: if only one is a signalling NaN, y is. 118 * The result is y. 119 * - y = Inf. Implied: x != NaN (is 0, number, or Inf: the NaN 120 * case was taken care of earlier). 121 * If x = 0, the result is NaN. Otherwise the result 122 * is y, with its sign reversed if x is negative. 123 * - x = 0. Implied: y is 0 or number. 124 * The result is 0 (with XORed sign as usual). 125 * - other. Implied: both x and y are numbers. 126 * The result is x * y (XOR sign, multiply bits, add exponents). 127 */ 128 DPRINTF(FPE_REG, ("fpu_mul:\n")); 129 DUMPFPN(FPE_REG, x); 130 DUMPFPN(FPE_REG, y); 131 DPRINTF(FPE_REG, ("=>\n")); 132 133 ORDER(x, y); 134 if (ISNAN(y)) { 135 y->fp_sign ^= x->fp_sign; 136 fe->fe_cx |= FPSCR_VXSNAN; 137 DUMPFPN(FPE_REG, y); 138 return (y); 139 } 140 if (ISINF(y)) { 141 if (ISZERO(x)) { 142 fe->fe_cx |= FPSCR_VXIMZ; 143 return (fpu_newnan(fe)); 144 } 145 y->fp_sign ^= x->fp_sign; 146 DUMPFPN(FPE_REG, y); 147 return (y); 148 } 149 if (ISZERO(x)) { 150 x->fp_sign ^= y->fp_sign; 151 DUMPFPN(FPE_REG, x); 152 return (x); 153 } 154 155 /* 156 * Setup. In the code below, the mask `m' will hold the current 157 * mantissa byte from y. The variable `bit' denotes the bit 158 * within m. We also define some macros to deal with everything. 159 */ 160 x3 = x->fp_mant[3]; 161 x2 = x->fp_mant[2]; 162 x1 = x->fp_mant[1]; 163 x0 = x->fp_mant[0]; 164 sticky = a3 = a2 = a1 = a0 = 0; 165 166 #define ADD /* A += X */ \ 167 FPU_ADDS(a3, a3, x3); \ 168 FPU_ADDCS(a2, a2, x2); \ 169 FPU_ADDCS(a1, a1, x1); \ 170 FPU_ADDC(a0, a0, x0) 171 172 #define SHR1 /* A >>= 1, with sticky */ \ 173 sticky |= a3 & 1, a3 = (a3 >> 1) | (a2 << 31), \ 174 a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 175 176 #define SHR32 /* A >>= 32, with sticky */ \ 177 sticky |= a3, a3 = a2, a2 = a1, a1 = a0, a0 = 0 178 179 #define STEP /* each 1-bit step of the multiplication */ \ 180 SHR1; if (bit & m) { ADD; }; bit <<= 1 181 182 /* 183 * We are ready to begin. The multiply loop runs once for each 184 * of the four 32-bit words. Some words, however, are special. 185 * As noted above, the low order bits of Y are often zero. Even 186 * if not, the first loop can certainly skip the guard bits. 187 * The last word of y has its highest 1-bit in position FP_NMANT-1, 188 * so we stop the loop when we move past that bit. 189 */ 190 if ((m = y->fp_mant[3]) == 0) { 191 /* SHR32; */ /* unneeded since A==0 */ 192 } else { 193 bit = 1 << FP_NG; 194 do { 195 STEP; 196 } while (bit != 0); 197 } 198 if ((m = y->fp_mant[2]) == 0) { 199 SHR32; 200 } else { 201 bit = 1; 202 do { 203 STEP; 204 } while (bit != 0); 205 } 206 if ((m = y->fp_mant[1]) == 0) { 207 SHR32; 208 } else { 209 bit = 1; 210 do { 211 STEP; 212 } while (bit != 0); 213 } 214 m = y->fp_mant[0]; /* definitely != 0 */ 215 bit = 1; 216 do { 217 STEP; 218 } while (bit <= m); 219 220 /* 221 * Done with mantissa calculation. Get exponent and handle 222 * 11.111...1 case, then put result in place. We reuse x since 223 * it already has the right class (FP_NUM). 224 */ 225 m = x->fp_exp + y->fp_exp; 226 if (a0 >= FP_2) { 227 SHR1; 228 m++; 229 } 230 x->fp_sign ^= y->fp_sign; 231 x->fp_exp = m; 232 x->fp_sticky = sticky; 233 x->fp_mant[3] = a3; 234 x->fp_mant[2] = a2; 235 x->fp_mant[1] = a1; 236 x->fp_mant[0] = a0; 237 238 DUMPFPN(FPE_REG, x); 239 return (x); 240 } 241