1 /* $NetBSD: fpu_mul.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */ 2 3 /* 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_mul.c 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * Perform an FPU multiply (return x * y). 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/fpu.h> 56 #include <machine/reg.h> 57 58 #include <powerpc/fpu/fpu_arith.h> 59 #include <powerpc/fpu/fpu_emu.h> 60 61 /* 62 * The multiplication algorithm for normal numbers is as follows: 63 * 64 * The fraction of the product is built in the usual stepwise fashion. 65 * Each step consists of shifting the accumulator right one bit 66 * (maintaining any guard bits) and, if the next bit in y is set, 67 * adding the multiplicand (x) to the accumulator. Then, in any case, 68 * we advance one bit leftward in y. Algorithmically: 69 * 70 * A = 0; 71 * for (bit = 0; bit < FP_NMANT; bit++) { 72 * sticky |= A & 1, A >>= 1; 73 * if (Y & (1 << bit)) 74 * A += X; 75 * } 76 * 77 * (X and Y here represent the mantissas of x and y respectively.) 78 * The resultant accumulator (A) is the product's mantissa. It may 79 * be as large as 11.11111... in binary and hence may need to be 80 * shifted right, but at most one bit. 81 * 82 * Since we do not have efficient multiword arithmetic, we code the 83 * accumulator as four separate words, just like any other mantissa. 84 * We use local variables in the hope that this is faster than memory. 85 * We keep x->fp_mant in locals for the same reason. 86 * 87 * In the algorithm above, the bits in y are inspected one at a time. 88 * We will pick them up 32 at a time and then deal with those 32, one 89 * at a time. Note, however, that we know several things about y: 90 * 91 * - the guard and round bits at the bottom are sure to be zero; 92 * 93 * - often many low bits are zero (y is often from a single or double 94 * precision source); 95 * 96 * - bit FP_NMANT-1 is set, and FP_1*2 fits in a word. 97 * 98 * We can also test for 32-zero-bits swiftly. In this case, the center 99 * part of the loop---setting sticky, shifting A, and not adding---will 100 * run 32 times without adding X to A. We can do a 32-bit shift faster 101 * by simply moving words. Since zeros are common, we optimize this case. 102 * Furthermore, since A is initially zero, we can omit the shift as well 103 * until we reach a nonzero word. 104 */ 105 struct fpn * 106 fpu_mul(struct fpemu *fe) 107 { 108 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 109 u_int a3, a2, a1, a0, x3, x2, x1, x0, bit, m; 110 int sticky; 111 FPU_DECL_CARRY; 112 113 /* 114 * Put the `heavier' operand on the right (see fpu_emu.h). 115 * Then we will have one of the following cases, taken in the 116 * following order: 117 * 118 * - y = NaN. Implied: if only one is a signalling NaN, y is. 119 * The result is y. 120 * - y = Inf. Implied: x != NaN (is 0, number, or Inf: the NaN 121 * case was taken care of earlier). 122 * If x = 0, the result is NaN. Otherwise the result 123 * is y, with its sign reversed if x is negative. 124 * - x = 0. Implied: y is 0 or number. 125 * The result is 0 (with XORed sign as usual). 126 * - other. Implied: both x and y are numbers. 127 * The result is x * y (XOR sign, multiply bits, add exponents). 128 */ 129 DPRINTF(FPE_REG, ("fpu_mul:\n")); 130 DUMPFPN(FPE_REG, x); 131 DUMPFPN(FPE_REG, y); 132 DPRINTF(FPE_REG, ("=>\n")); 133 134 ORDER(x, y); 135 if (ISNAN(y)) { 136 y->fp_sign ^= x->fp_sign; 137 fe->fe_cx |= FPSCR_VXSNAN; 138 DUMPFPN(FPE_REG, y); 139 return (y); 140 } 141 if (ISINF(y)) { 142 if (ISZERO(x)) { 143 fe->fe_cx |= FPSCR_VXIMZ; 144 return (fpu_newnan(fe)); 145 } 146 y->fp_sign ^= x->fp_sign; 147 DUMPFPN(FPE_REG, y); 148 return (y); 149 } 150 if (ISZERO(x)) { 151 x->fp_sign ^= y->fp_sign; 152 DUMPFPN(FPE_REG, x); 153 return (x); 154 } 155 156 /* 157 * Setup. In the code below, the mask `m' will hold the current 158 * mantissa byte from y. The variable `bit' denotes the bit 159 * within m. We also define some macros to deal with everything. 160 */ 161 x3 = x->fp_mant[3]; 162 x2 = x->fp_mant[2]; 163 x1 = x->fp_mant[1]; 164 x0 = x->fp_mant[0]; 165 sticky = a3 = a2 = a1 = a0 = 0; 166 167 #define ADD /* A += X */ \ 168 FPU_ADDS(a3, a3, x3); \ 169 FPU_ADDCS(a2, a2, x2); \ 170 FPU_ADDCS(a1, a1, x1); \ 171 FPU_ADDC(a0, a0, x0) 172 173 #define SHR1 /* A >>= 1, with sticky */ \ 174 sticky |= a3 & 1, a3 = (a3 >> 1) | (a2 << 31), \ 175 a2 = (a2 >> 1) | (a1 << 31), a1 = (a1 >> 1) | (a0 << 31), a0 >>= 1 176 177 #define SHR32 /* A >>= 32, with sticky */ \ 178 sticky |= a3, a3 = a2, a2 = a1, a1 = a0, a0 = 0 179 180 #define STEP /* each 1-bit step of the multiplication */ \ 181 SHR1; if (bit & m) { ADD; }; bit <<= 1 182 183 /* 184 * We are ready to begin. The multiply loop runs once for each 185 * of the four 32-bit words. Some words, however, are special. 186 * As noted above, the low order bits of Y are often zero. Even 187 * if not, the first loop can certainly skip the guard bits. 188 * The last word of y has its highest 1-bit in position FP_NMANT-1, 189 * so we stop the loop when we move past that bit. 190 */ 191 if ((m = y->fp_mant[3]) == 0) { 192 /* SHR32; */ /* unneeded since A==0 */ 193 } else { 194 bit = 1 << FP_NG; 195 do { 196 STEP; 197 } while (bit != 0); 198 } 199 if ((m = y->fp_mant[2]) == 0) { 200 SHR32; 201 } else { 202 bit = 1; 203 do { 204 STEP; 205 } while (bit != 0); 206 } 207 if ((m = y->fp_mant[1]) == 0) { 208 SHR32; 209 } else { 210 bit = 1; 211 do { 212 STEP; 213 } while (bit != 0); 214 } 215 m = y->fp_mant[0]; /* definitely != 0 */ 216 bit = 1; 217 do { 218 STEP; 219 } while (bit <= m); 220 221 /* 222 * Done with mantissa calculation. Get exponent and handle 223 * 11.111...1 case, then put result in place. We reuse x since 224 * it already has the right class (FP_NUM). 225 */ 226 m = x->fp_exp + y->fp_exp; 227 if (a0 >= FP_2) { 228 SHR1; 229 m++; 230 } 231 x->fp_sign ^= y->fp_sign; 232 x->fp_exp = m; 233 x->fp_sticky = sticky; 234 x->fp_mant[3] = a3; 235 x->fp_mant[2] = a2; 236 x->fp_mant[1] = a1; 237 x->fp_mant[0] = a0; 238 239 DUMPFPN(FPE_REG, x); 240 return (x); 241 } 242