1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 */ 42 43 /* 44 * FPU subroutines: `implode' internal format numbers into the machine's 45 * `packed binary' format. 46 */ 47 48 #include <sys/cdefs.h> 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 52 #include <machine/fpu.h> 53 #include <machine/ieee.h> 54 #include <machine/ieeefp.h> 55 56 #include <powerpc/fpu/fpu_arith.h> 57 #include <powerpc/fpu/fpu_emu.h> 58 #include <powerpc/fpu/fpu_extern.h> 59 #include <powerpc/fpu/fpu_instr.h> 60 61 static int round(struct fpemu *, struct fpn *); 62 static int toinf(struct fpemu *, int); 63 64 /* 65 * Round a number (algorithm from Motorola MC68882 manual, modified for 66 * our internal format). Set inexact exception if rounding is required. 67 * Return true iff we rounded up. 68 * 69 * After rounding, we discard the guard and round bits by shifting right 70 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 71 * This saves effort later. 72 * 73 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 74 * responsibility to fix this if necessary. 75 */ 76 static int 77 round(struct fpemu *fe, struct fpn *fp) 78 { 79 u_int m0, m1, m2, m3; 80 int gr, s; 81 FPU_DECL_CARRY; 82 83 m0 = fp->fp_mant[0]; 84 m1 = fp->fp_mant[1]; 85 m2 = fp->fp_mant[2]; 86 m3 = fp->fp_mant[3]; 87 gr = m3 & 3; 88 s = fp->fp_sticky; 89 90 /* mant >>= FP_NG */ 91 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 92 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 93 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 94 m0 >>= FP_NG; 95 96 if ((gr | s) == 0) /* result is exact: no rounding needed */ 97 goto rounddown; 98 99 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */ 100 101 /* Go to rounddown to round down; break to round up. */ 102 switch ((fe->fe_fpscr) & FPSCR_RN) { 103 case FP_RN: 104 default: 105 /* 106 * Round only if guard is set (gr & 2). If guard is set, 107 * but round & sticky both clear, then we want to round 108 * but have a tie, so round to even, i.e., add 1 iff odd. 109 */ 110 if ((gr & 2) == 0) 111 goto rounddown; 112 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 113 break; 114 goto rounddown; 115 116 case FP_RZ: 117 /* Round towards zero, i.e., down. */ 118 goto rounddown; 119 120 case FP_RM: 121 /* Round towards -Inf: up if negative, down if positive. */ 122 if (fp->fp_sign) 123 break; 124 goto rounddown; 125 126 case FP_RP: 127 /* Round towards +Inf: up if positive, down otherwise. */ 128 if (!fp->fp_sign) 129 break; 130 goto rounddown; 131 } 132 133 /* Bump low bit of mantissa, with carry. */ 134 fe->fe_cx |= FPSCR_FR; 135 136 FPU_ADDS(m3, m3, 1); 137 FPU_ADDCS(m2, m2, 0); 138 FPU_ADDCS(m1, m1, 0); 139 FPU_ADDC(m0, m0, 0); 140 fp->fp_mant[0] = m0; 141 fp->fp_mant[1] = m1; 142 fp->fp_mant[2] = m2; 143 fp->fp_mant[3] = m3; 144 return (1); 145 146 rounddown: 147 fp->fp_mant[0] = m0; 148 fp->fp_mant[1] = m1; 149 fp->fp_mant[2] = m2; 150 fp->fp_mant[3] = m3; 151 return (0); 152 } 153 154 /* 155 * For overflow: return true if overflow is to go to +/-Inf, according 156 * to the sign of the overflowing result. If false, overflow is to go 157 * to the largest magnitude value instead. 158 */ 159 static int 160 toinf(struct fpemu *fe, int sign) 161 { 162 int inf; 163 164 /* look at rounding direction */ 165 switch ((fe->fe_fpscr) & FPSCR_RN) { 166 default: 167 case FP_RN: /* the nearest value is always Inf */ 168 inf = 1; 169 break; 170 171 case FP_RZ: /* toward 0 => never towards Inf */ 172 inf = 0; 173 break; 174 175 case FP_RP: /* toward +Inf iff positive */ 176 inf = sign == 0; 177 break; 178 179 case FP_RM: /* toward -Inf iff negative */ 180 inf = sign; 181 break; 182 } 183 if (inf) 184 fe->fe_cx |= FPSCR_OX; 185 return (inf); 186 } 187 188 /* 189 * fpn -> int (int value returned as return value). 190 * 191 * N.B.: this conversion always rounds towards zero (this is a peculiarity 192 * of the SPARC instruction set). 193 */ 194 u_int 195 fpu_ftoi(struct fpemu *fe, struct fpn *fp) 196 { 197 u_int i; 198 int sign, exp; 199 200 sign = fp->fp_sign; 201 switch (fp->fp_class) { 202 case FPC_ZERO: 203 return (0); 204 205 case FPC_NUM: 206 /* 207 * If exp >= 2^32, overflow. Otherwise shift value right 208 * into last mantissa word (this will not exceed 0xffffffff), 209 * shifting any guard and round bits out into the sticky 210 * bit. Then ``round'' towards zero, i.e., just set an 211 * inexact exception if sticky is set (see round()). 212 * If the result is > 0x80000000, or is positive and equals 213 * 0x80000000, overflow; otherwise the last fraction word 214 * is the result. 215 */ 216 if ((exp = fp->fp_exp) >= 32) 217 break; 218 /* NB: the following includes exp < 0 cases */ 219 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 220 fe->fe_cx |= FPSCR_UX; 221 i = fp->fp_mant[3]; 222 if (i >= ((u_int)0x80000000 + sign)) 223 break; 224 return (sign ? -i : i); 225 226 default: /* Inf, qNaN, sNaN */ 227 break; 228 } 229 /* overflow: replace any inexact exception with invalid */ 230 fe->fe_cx |= FPSCR_VXCVI; 231 return (0x7fffffff + sign); 232 } 233 234 /* 235 * fpn -> extended int (high bits of int value returned as return value). 236 * 237 * N.B.: this conversion always rounds towards zero (this is a peculiarity 238 * of the SPARC instruction set). 239 */ 240 u_int 241 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res) 242 { 243 u_int64_t i; 244 int sign, exp; 245 246 sign = fp->fp_sign; 247 switch (fp->fp_class) { 248 case FPC_ZERO: 249 res[1] = 0; 250 return (0); 251 252 case FPC_NUM: 253 /* 254 * If exp >= 2^64, overflow. Otherwise shift value right 255 * into last mantissa word (this will not exceed 0xffffffffffffffff), 256 * shifting any guard and round bits out into the sticky 257 * bit. Then ``round'' towards zero, i.e., just set an 258 * inexact exception if sticky is set (see round()). 259 * If the result is > 0x8000000000000000, or is positive and equals 260 * 0x8000000000000000, overflow; otherwise the last fraction word 261 * is the result. 262 */ 263 if ((exp = fp->fp_exp) >= 64) 264 break; 265 /* NB: the following includes exp < 0 cases */ 266 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 267 fe->fe_cx |= FPSCR_UX; 268 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 269 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 270 break; 271 return (sign ? -i : i); 272 273 default: /* Inf, qNaN, sNaN */ 274 break; 275 } 276 /* overflow: replace any inexact exception with invalid */ 277 fe->fe_cx |= FPSCR_VXCVI; 278 return (0x7fffffffffffffffLL + sign); 279 } 280 281 /* 282 * fpn -> single (32 bit single returned as return value). 283 * We assume <= 29 bits in a single-precision fraction (1.f part). 284 */ 285 u_int 286 fpu_ftos(struct fpemu *fe, struct fpn *fp) 287 { 288 u_int sign = fp->fp_sign << 31; 289 int exp; 290 291 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 292 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 293 294 /* Take care of non-numbers first. */ 295 if (ISNAN(fp)) { 296 /* 297 * Preserve upper bits of NaN, per SPARC V8 appendix N. 298 * Note that fp->fp_mant[0] has the quiet bit set, 299 * even if it is classified as a signalling NaN. 300 */ 301 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 302 exp = SNG_EXP_INFNAN; 303 goto done; 304 } 305 if (ISINF(fp)) 306 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 307 if (ISZERO(fp)) 308 return (sign); 309 310 /* 311 * Normals (including subnormals). Drop all the fraction bits 312 * (including the explicit ``implied'' 1 bit) down into the 313 * single-precision range. If the number is subnormal, move 314 * the ``implied'' 1 into the explicit range as well, and shift 315 * right to introduce leading zeroes. Rounding then acts 316 * differently for normals and subnormals: the largest subnormal 317 * may round to the smallest normal (1.0 x 2^minexp), or may 318 * remain subnormal. In the latter case, signal an underflow 319 * if the result was inexact or if underflow traps are enabled. 320 * 321 * Rounding a normal, on the other hand, always produces another 322 * normal (although either way the result might be too big for 323 * single precision, and cause an overflow). If rounding a 324 * normal produces 2.0 in the fraction, we need not adjust that 325 * fraction at all, since both 1.0 and 2.0 are zero under the 326 * fraction mask. 327 * 328 * Note that the guard and round bits vanish from the number after 329 * rounding. 330 */ 331 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 332 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 333 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 334 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 335 return (sign | SNG_EXP(1) | 0); 336 if ((fe->fe_cx & FPSCR_FI) || 337 (fe->fe_fpscr & FPSCR_UX)) 338 fe->fe_cx |= FPSCR_UX; 339 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 340 } 341 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 342 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 343 #ifdef DIAGNOSTIC 344 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 345 panic("fpu_ftos"); 346 #endif 347 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 348 exp++; 349 if (exp >= SNG_EXP_INFNAN) { 350 /* overflow to inf or to max single */ 351 if (toinf(fe, sign)) 352 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 353 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 354 } 355 done: 356 /* phew, made it */ 357 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 358 } 359 360 /* 361 * fpn -> double (32 bit high-order result returned; 32-bit low order result 362 * left in res[1]). Assumes <= 61 bits in double precision fraction. 363 * 364 * This code mimics fpu_ftos; see it for comments. 365 */ 366 u_int 367 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res) 368 { 369 u_int sign = fp->fp_sign << 31; 370 int exp; 371 372 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 373 #define DBL_MASK (DBL_EXP(1) - 1) 374 375 if (ISNAN(fp)) { 376 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 377 exp = DBL_EXP_INFNAN; 378 goto done; 379 } 380 if (ISINF(fp)) { 381 sign |= DBL_EXP(DBL_EXP_INFNAN); 382 goto zero; 383 } 384 if (ISZERO(fp)) { 385 zero: res[1] = 0; 386 return (sign); 387 } 388 389 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 390 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 391 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 392 res[1] = 0; 393 return (sign | DBL_EXP(1) | 0); 394 } 395 if ((fe->fe_cx & FPSCR_FI) || 396 (fe->fe_fpscr & FPSCR_UX)) 397 fe->fe_cx |= FPSCR_UX; 398 exp = 0; 399 goto done; 400 } 401 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 402 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 403 exp++; 404 if (exp >= DBL_EXP_INFNAN) { 405 fe->fe_cx |= FPSCR_OX | FPSCR_UX; 406 if (toinf(fe, sign)) { 407 res[1] = 0; 408 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 409 } 410 res[1] = ~0; 411 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 412 } 413 done: 414 res[1] = fp->fp_mant[3]; 415 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 416 } 417 418 /* 419 * Implode an fpn, writing the result into the given space. 420 */ 421 void 422 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space) 423 { 424 425 switch (type) { 426 case FTYPE_LNG: 427 space[0] = fpu_ftox(fe, fp, space); 428 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n", 429 space[0], space[1])); 430 break; 431 432 case FTYPE_INT: 433 space[0] = 0; 434 space[1] = fpu_ftoi(fe, fp); 435 DPRINTF(FPE_REG, ("fpu_implode: int %x\n", 436 space[1])); 437 break; 438 439 case FTYPE_SNG: 440 space[0] = fpu_ftos(fe, fp); 441 DPRINTF(FPE_REG, ("fpu_implode: single %x\n", 442 space[0])); 443 break; 444 445 case FTYPE_DBL: 446 space[0] = fpu_ftod(fe, fp, space); 447 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n", 448 space[0], space[1])); 449 break; break; 450 451 default: 452 panic("fpu_implode: invalid type %d", type); 453 } 454 } 455