1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * FPU subroutines: `implode' internal format numbers into the machine's 47 * `packed binary' format. 48 */ 49 50 #include <sys/cdefs.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 54 #include <machine/fpu.h> 55 #include <machine/ieee.h> 56 #include <machine/ieeefp.h> 57 58 #include <powerpc/fpu/fpu_arith.h> 59 #include <powerpc/fpu/fpu_emu.h> 60 #include <powerpc/fpu/fpu_extern.h> 61 #include <powerpc/fpu/fpu_instr.h> 62 63 static int round(struct fpemu *, struct fpn *); 64 static int toinf(struct fpemu *, int); 65 66 /* 67 * Round a number (algorithm from Motorola MC68882 manual, modified for 68 * our internal format). Set inexact exception if rounding is required. 69 * Return true iff we rounded up. 70 * 71 * After rounding, we discard the guard and round bits by shifting right 72 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 73 * This saves effort later. 74 * 75 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 76 * responsibility to fix this if necessary. 77 */ 78 static int 79 round(struct fpemu *fe, struct fpn *fp) 80 { 81 u_int m0, m1, m2, m3; 82 int gr, s; 83 FPU_DECL_CARRY; 84 85 m0 = fp->fp_mant[0]; 86 m1 = fp->fp_mant[1]; 87 m2 = fp->fp_mant[2]; 88 m3 = fp->fp_mant[3]; 89 gr = m3 & 3; 90 s = fp->fp_sticky; 91 92 /* mant >>= FP_NG */ 93 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 94 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 95 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 96 m0 >>= FP_NG; 97 98 if ((gr | s) == 0) /* result is exact: no rounding needed */ 99 goto rounddown; 100 101 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */ 102 103 /* Go to rounddown to round down; break to round up. */ 104 switch ((fe->fe_fpscr) & FPSCR_RN) { 105 case FP_RN: 106 default: 107 /* 108 * Round only if guard is set (gr & 2). If guard is set, 109 * but round & sticky both clear, then we want to round 110 * but have a tie, so round to even, i.e., add 1 iff odd. 111 */ 112 if ((gr & 2) == 0) 113 goto rounddown; 114 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 115 break; 116 goto rounddown; 117 118 case FP_RZ: 119 /* Round towards zero, i.e., down. */ 120 goto rounddown; 121 122 case FP_RM: 123 /* Round towards -Inf: up if negative, down if positive. */ 124 if (fp->fp_sign) 125 break; 126 goto rounddown; 127 128 case FP_RP: 129 /* Round towards +Inf: up if positive, down otherwise. */ 130 if (!fp->fp_sign) 131 break; 132 goto rounddown; 133 } 134 135 /* Bump low bit of mantissa, with carry. */ 136 fe->fe_cx |= FPSCR_FR; 137 138 FPU_ADDS(m3, m3, 1); 139 FPU_ADDCS(m2, m2, 0); 140 FPU_ADDCS(m1, m1, 0); 141 FPU_ADDC(m0, m0, 0); 142 fp->fp_mant[0] = m0; 143 fp->fp_mant[1] = m1; 144 fp->fp_mant[2] = m2; 145 fp->fp_mant[3] = m3; 146 return (1); 147 148 rounddown: 149 fp->fp_mant[0] = m0; 150 fp->fp_mant[1] = m1; 151 fp->fp_mant[2] = m2; 152 fp->fp_mant[3] = m3; 153 return (0); 154 } 155 156 /* 157 * For overflow: return true if overflow is to go to +/-Inf, according 158 * to the sign of the overflowing result. If false, overflow is to go 159 * to the largest magnitude value instead. 160 */ 161 static int 162 toinf(struct fpemu *fe, int sign) 163 { 164 int inf; 165 166 /* look at rounding direction */ 167 switch ((fe->fe_fpscr) & FPSCR_RN) { 168 default: 169 case FP_RN: /* the nearest value is always Inf */ 170 inf = 1; 171 break; 172 173 case FP_RZ: /* toward 0 => never towards Inf */ 174 inf = 0; 175 break; 176 177 case FP_RP: /* toward +Inf iff positive */ 178 inf = sign == 0; 179 break; 180 181 case FP_RM: /* toward -Inf iff negative */ 182 inf = sign; 183 break; 184 } 185 if (inf) 186 fe->fe_cx |= FPSCR_OX; 187 return (inf); 188 } 189 190 /* 191 * fpn -> int (int value returned as return value). 192 * 193 * N.B.: this conversion always rounds towards zero (this is a peculiarity 194 * of the SPARC instruction set). 195 */ 196 u_int 197 fpu_ftoi(struct fpemu *fe, struct fpn *fp) 198 { 199 u_int i; 200 int sign, exp; 201 202 sign = fp->fp_sign; 203 switch (fp->fp_class) { 204 case FPC_ZERO: 205 return (0); 206 207 case FPC_NUM: 208 /* 209 * If exp >= 2^32, overflow. Otherwise shift value right 210 * into last mantissa word (this will not exceed 0xffffffff), 211 * shifting any guard and round bits out into the sticky 212 * bit. Then ``round'' towards zero, i.e., just set an 213 * inexact exception if sticky is set (see round()). 214 * If the result is > 0x80000000, or is positive and equals 215 * 0x80000000, overflow; otherwise the last fraction word 216 * is the result. 217 */ 218 if ((exp = fp->fp_exp) >= 32) 219 break; 220 /* NB: the following includes exp < 0 cases */ 221 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 222 fe->fe_cx |= FPSCR_UX; 223 i = fp->fp_mant[3]; 224 if (i >= ((u_int)0x80000000 + sign)) 225 break; 226 return (sign ? -i : i); 227 228 default: /* Inf, qNaN, sNaN */ 229 break; 230 } 231 /* overflow: replace any inexact exception with invalid */ 232 fe->fe_cx |= FPSCR_VXCVI; 233 return (0x7fffffff + sign); 234 } 235 236 /* 237 * fpn -> extended int (high bits of int value returned as return value). 238 * 239 * N.B.: this conversion always rounds towards zero (this is a peculiarity 240 * of the SPARC instruction set). 241 */ 242 u_int 243 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res) 244 { 245 u_int64_t i; 246 int sign, exp; 247 248 sign = fp->fp_sign; 249 switch (fp->fp_class) { 250 case FPC_ZERO: 251 res[1] = 0; 252 return (0); 253 254 case FPC_NUM: 255 /* 256 * If exp >= 2^64, overflow. Otherwise shift value right 257 * into last mantissa word (this will not exceed 0xffffffffffffffff), 258 * shifting any guard and round bits out into the sticky 259 * bit. Then ``round'' towards zero, i.e., just set an 260 * inexact exception if sticky is set (see round()). 261 * If the result is > 0x8000000000000000, or is positive and equals 262 * 0x8000000000000000, overflow; otherwise the last fraction word 263 * is the result. 264 */ 265 if ((exp = fp->fp_exp) >= 64) 266 break; 267 /* NB: the following includes exp < 0 cases */ 268 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 269 fe->fe_cx |= FPSCR_UX; 270 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 271 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 272 break; 273 return (sign ? -i : i); 274 275 default: /* Inf, qNaN, sNaN */ 276 break; 277 } 278 /* overflow: replace any inexact exception with invalid */ 279 fe->fe_cx |= FPSCR_VXCVI; 280 return (0x7fffffffffffffffLL + sign); 281 } 282 283 /* 284 * fpn -> single (32 bit single returned as return value). 285 * We assume <= 29 bits in a single-precision fraction (1.f part). 286 */ 287 u_int 288 fpu_ftos(struct fpemu *fe, struct fpn *fp) 289 { 290 u_int sign = fp->fp_sign << 31; 291 int exp; 292 293 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 294 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 295 296 /* Take care of non-numbers first. */ 297 if (ISNAN(fp)) { 298 /* 299 * Preserve upper bits of NaN, per SPARC V8 appendix N. 300 * Note that fp->fp_mant[0] has the quiet bit set, 301 * even if it is classified as a signalling NaN. 302 */ 303 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 304 exp = SNG_EXP_INFNAN; 305 goto done; 306 } 307 if (ISINF(fp)) 308 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 309 if (ISZERO(fp)) 310 return (sign); 311 312 /* 313 * Normals (including subnormals). Drop all the fraction bits 314 * (including the explicit ``implied'' 1 bit) down into the 315 * single-precision range. If the number is subnormal, move 316 * the ``implied'' 1 into the explicit range as well, and shift 317 * right to introduce leading zeroes. Rounding then acts 318 * differently for normals and subnormals: the largest subnormal 319 * may round to the smallest normal (1.0 x 2^minexp), or may 320 * remain subnormal. In the latter case, signal an underflow 321 * if the result was inexact or if underflow traps are enabled. 322 * 323 * Rounding a normal, on the other hand, always produces another 324 * normal (although either way the result might be too big for 325 * single precision, and cause an overflow). If rounding a 326 * normal produces 2.0 in the fraction, we need not adjust that 327 * fraction at all, since both 1.0 and 2.0 are zero under the 328 * fraction mask. 329 * 330 * Note that the guard and round bits vanish from the number after 331 * rounding. 332 */ 333 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 334 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 335 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 336 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 337 return (sign | SNG_EXP(1) | 0); 338 if ((fe->fe_cx & FPSCR_FI) || 339 (fe->fe_fpscr & FPSCR_UX)) 340 fe->fe_cx |= FPSCR_UX; 341 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 342 } 343 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 344 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 345 #ifdef DIAGNOSTIC 346 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 347 panic("fpu_ftos"); 348 #endif 349 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 350 exp++; 351 if (exp >= SNG_EXP_INFNAN) { 352 /* overflow to inf or to max single */ 353 if (toinf(fe, sign)) 354 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 355 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 356 } 357 done: 358 /* phew, made it */ 359 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 360 } 361 362 /* 363 * fpn -> double (32 bit high-order result returned; 32-bit low order result 364 * left in res[1]). Assumes <= 61 bits in double precision fraction. 365 * 366 * This code mimics fpu_ftos; see it for comments. 367 */ 368 u_int 369 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res) 370 { 371 u_int sign = fp->fp_sign << 31; 372 int exp; 373 374 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 375 #define DBL_MASK (DBL_EXP(1) - 1) 376 377 if (ISNAN(fp)) { 378 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 379 exp = DBL_EXP_INFNAN; 380 goto done; 381 } 382 if (ISINF(fp)) { 383 sign |= DBL_EXP(DBL_EXP_INFNAN); 384 goto zero; 385 } 386 if (ISZERO(fp)) { 387 zero: res[1] = 0; 388 return (sign); 389 } 390 391 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 392 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 393 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 394 res[1] = 0; 395 return (sign | DBL_EXP(1) | 0); 396 } 397 if ((fe->fe_cx & FPSCR_FI) || 398 (fe->fe_fpscr & FPSCR_UX)) 399 fe->fe_cx |= FPSCR_UX; 400 exp = 0; 401 goto done; 402 } 403 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 404 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 405 exp++; 406 if (exp >= DBL_EXP_INFNAN) { 407 fe->fe_cx |= FPSCR_OX | FPSCR_UX; 408 if (toinf(fe, sign)) { 409 res[1] = 0; 410 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 411 } 412 res[1] = ~0; 413 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 414 } 415 done: 416 res[1] = fp->fp_mant[3]; 417 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 418 } 419 420 /* 421 * Implode an fpn, writing the result into the given space. 422 */ 423 void 424 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space) 425 { 426 427 switch (type) { 428 case FTYPE_LNG: 429 space[0] = fpu_ftox(fe, fp, space); 430 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n", 431 space[0], space[1])); 432 break; 433 434 case FTYPE_INT: 435 space[0] = 0; 436 space[1] = fpu_ftoi(fe, fp); 437 DPRINTF(FPE_REG, ("fpu_implode: int %x\n", 438 space[1])); 439 break; 440 441 case FTYPE_SNG: 442 space[0] = fpu_ftos(fe, fp); 443 DPRINTF(FPE_REG, ("fpu_implode: single %x\n", 444 space[0])); 445 break; 446 447 case FTYPE_DBL: 448 space[0] = fpu_ftod(fe, fp, space); 449 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n", 450 space[0], space[1])); 451 break; break; 452 453 default: 454 panic("fpu_implode: invalid type %d", type); 455 } 456 } 457