1 /* $NetBSD: fpu_implode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * FPU subroutines: `implode' internal format numbers into the machine's 47 * `packed binary' format. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 56 #include <machine/fpu.h> 57 #include <machine/ieee.h> 58 #include <machine/ieeefp.h> 59 #include <machine/reg.h> 60 61 #include <powerpc/fpu/fpu_arith.h> 62 #include <powerpc/fpu/fpu_emu.h> 63 #include <powerpc/fpu/fpu_extern.h> 64 #include <powerpc/fpu/fpu_instr.h> 65 66 static int round(struct fpemu *, struct fpn *); 67 static int toinf(struct fpemu *, int); 68 69 /* 70 * Round a number (algorithm from Motorola MC68882 manual, modified for 71 * our internal format). Set inexact exception if rounding is required. 72 * Return true iff we rounded up. 73 * 74 * After rounding, we discard the guard and round bits by shifting right 75 * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky). 76 * This saves effort later. 77 * 78 * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's 79 * responsibility to fix this if necessary. 80 */ 81 static int 82 round(struct fpemu *fe, struct fpn *fp) 83 { 84 u_int m0, m1, m2, m3; 85 int gr, s; 86 FPU_DECL_CARRY; 87 88 m0 = fp->fp_mant[0]; 89 m1 = fp->fp_mant[1]; 90 m2 = fp->fp_mant[2]; 91 m3 = fp->fp_mant[3]; 92 gr = m3 & 3; 93 s = fp->fp_sticky; 94 95 /* mant >>= FP_NG */ 96 m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG)); 97 m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG)); 98 m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG)); 99 m0 >>= FP_NG; 100 101 if ((gr | s) == 0) /* result is exact: no rounding needed */ 102 goto rounddown; 103 104 fe->fe_cx |= FPSCR_XX|FPSCR_FI; /* inexact */ 105 106 /* Go to rounddown to round down; break to round up. */ 107 switch ((fe->fe_fpscr) & FPSCR_RN) { 108 109 case FP_RN: 110 default: 111 /* 112 * Round only if guard is set (gr & 2). If guard is set, 113 * but round & sticky both clear, then we want to round 114 * but have a tie, so round to even, i.e., add 1 iff odd. 115 */ 116 if ((gr & 2) == 0) 117 goto rounddown; 118 if ((gr & 1) || fp->fp_sticky || (m3 & 1)) 119 break; 120 goto rounddown; 121 122 case FP_RZ: 123 /* Round towards zero, i.e., down. */ 124 goto rounddown; 125 126 case FP_RM: 127 /* Round towards -Inf: up if negative, down if positive. */ 128 if (fp->fp_sign) 129 break; 130 goto rounddown; 131 132 case FP_RP: 133 /* Round towards +Inf: up if positive, down otherwise. */ 134 if (!fp->fp_sign) 135 break; 136 goto rounddown; 137 } 138 139 /* Bump low bit of mantissa, with carry. */ 140 fe->fe_cx |= FPSCR_FR; 141 142 FPU_ADDS(m3, m3, 1); 143 FPU_ADDCS(m2, m2, 0); 144 FPU_ADDCS(m1, m1, 0); 145 FPU_ADDC(m0, m0, 0); 146 fp->fp_mant[0] = m0; 147 fp->fp_mant[1] = m1; 148 fp->fp_mant[2] = m2; 149 fp->fp_mant[3] = m3; 150 return (1); 151 152 rounddown: 153 fp->fp_mant[0] = m0; 154 fp->fp_mant[1] = m1; 155 fp->fp_mant[2] = m2; 156 fp->fp_mant[3] = m3; 157 return (0); 158 } 159 160 /* 161 * For overflow: return true if overflow is to go to +/-Inf, according 162 * to the sign of the overflowing result. If false, overflow is to go 163 * to the largest magnitude value instead. 164 */ 165 static int 166 toinf(struct fpemu *fe, int sign) 167 { 168 int inf; 169 170 /* look at rounding direction */ 171 switch ((fe->fe_fpscr) & FPSCR_RN) { 172 173 default: 174 case FP_RN: /* the nearest value is always Inf */ 175 inf = 1; 176 break; 177 178 case FP_RZ: /* toward 0 => never towards Inf */ 179 inf = 0; 180 break; 181 182 case FP_RP: /* toward +Inf iff positive */ 183 inf = sign == 0; 184 break; 185 186 case FP_RM: /* toward -Inf iff negative */ 187 inf = sign; 188 break; 189 } 190 if (inf) 191 fe->fe_cx |= FPSCR_OX; 192 return (inf); 193 } 194 195 /* 196 * fpn -> int (int value returned as return value). 197 * 198 * N.B.: this conversion always rounds towards zero (this is a peculiarity 199 * of the SPARC instruction set). 200 */ 201 u_int 202 fpu_ftoi(struct fpemu *fe, struct fpn *fp) 203 { 204 u_int i; 205 int sign, exp; 206 207 sign = fp->fp_sign; 208 switch (fp->fp_class) { 209 210 case FPC_ZERO: 211 return (0); 212 213 case FPC_NUM: 214 /* 215 * If exp >= 2^32, overflow. Otherwise shift value right 216 * into last mantissa word (this will not exceed 0xffffffff), 217 * shifting any guard and round bits out into the sticky 218 * bit. Then ``round'' towards zero, i.e., just set an 219 * inexact exception if sticky is set (see round()). 220 * If the result is > 0x80000000, or is positive and equals 221 * 0x80000000, overflow; otherwise the last fraction word 222 * is the result. 223 */ 224 if ((exp = fp->fp_exp) >= 32) 225 break; 226 /* NB: the following includes exp < 0 cases */ 227 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 228 fe->fe_cx |= FPSCR_UX; 229 i = fp->fp_mant[3]; 230 if (i >= ((u_int)0x80000000 + sign)) 231 break; 232 return (sign ? -i : i); 233 234 default: /* Inf, qNaN, sNaN */ 235 break; 236 } 237 /* overflow: replace any inexact exception with invalid */ 238 fe->fe_cx |= FPSCR_VXCVI; 239 return (0x7fffffff + sign); 240 } 241 242 /* 243 * fpn -> extended int (high bits of int value returned as return value). 244 * 245 * N.B.: this conversion always rounds towards zero (this is a peculiarity 246 * of the SPARC instruction set). 247 */ 248 u_int 249 fpu_ftox(struct fpemu *fe, struct fpn *fp, u_int *res) 250 { 251 u_int64_t i; 252 int sign, exp; 253 254 sign = fp->fp_sign; 255 switch (fp->fp_class) { 256 257 case FPC_ZERO: 258 res[1] = 0; 259 return (0); 260 261 case FPC_NUM: 262 /* 263 * If exp >= 2^64, overflow. Otherwise shift value right 264 * into last mantissa word (this will not exceed 0xffffffffffffffff), 265 * shifting any guard and round bits out into the sticky 266 * bit. Then ``round'' towards zero, i.e., just set an 267 * inexact exception if sticky is set (see round()). 268 * If the result is > 0x8000000000000000, or is positive and equals 269 * 0x8000000000000000, overflow; otherwise the last fraction word 270 * is the result. 271 */ 272 if ((exp = fp->fp_exp) >= 64) 273 break; 274 /* NB: the following includes exp < 0 cases */ 275 if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0) 276 fe->fe_cx |= FPSCR_UX; 277 i = ((u_int64_t)fp->fp_mant[2]<<32)|fp->fp_mant[3]; 278 if (i >= ((u_int64_t)0x8000000000000000LL + sign)) 279 break; 280 return (sign ? -i : i); 281 282 default: /* Inf, qNaN, sNaN */ 283 break; 284 } 285 /* overflow: replace any inexact exception with invalid */ 286 fe->fe_cx |= FPSCR_VXCVI; 287 return (0x7fffffffffffffffLL + sign); 288 } 289 290 /* 291 * fpn -> single (32 bit single returned as return value). 292 * We assume <= 29 bits in a single-precision fraction (1.f part). 293 */ 294 u_int 295 fpu_ftos(struct fpemu *fe, struct fpn *fp) 296 { 297 u_int sign = fp->fp_sign << 31; 298 int exp; 299 300 #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */ 301 #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */ 302 303 /* Take care of non-numbers first. */ 304 if (ISNAN(fp)) { 305 /* 306 * Preserve upper bits of NaN, per SPARC V8 appendix N. 307 * Note that fp->fp_mant[0] has the quiet bit set, 308 * even if it is classified as a signalling NaN. 309 */ 310 (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS); 311 exp = SNG_EXP_INFNAN; 312 goto done; 313 } 314 if (ISINF(fp)) 315 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 316 if (ISZERO(fp)) 317 return (sign); 318 319 /* 320 * Normals (including subnormals). Drop all the fraction bits 321 * (including the explicit ``implied'' 1 bit) down into the 322 * single-precision range. If the number is subnormal, move 323 * the ``implied'' 1 into the explicit range as well, and shift 324 * right to introduce leading zeroes. Rounding then acts 325 * differently for normals and subnormals: the largest subnormal 326 * may round to the smallest normal (1.0 x 2^minexp), or may 327 * remain subnormal. In the latter case, signal an underflow 328 * if the result was inexact or if underflow traps are enabled. 329 * 330 * Rounding a normal, on the other hand, always produces another 331 * normal (although either way the result might be too big for 332 * single precision, and cause an overflow). If rounding a 333 * normal produces 2.0 in the fraction, we need not adjust that 334 * fraction at all, since both 1.0 and 2.0 are zero under the 335 * fraction mask. 336 * 337 * Note that the guard and round bits vanish from the number after 338 * rounding. 339 */ 340 if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */ 341 /* -NG for g,r; -SNG_FRACBITS-exp for fraction */ 342 (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp); 343 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1)) 344 return (sign | SNG_EXP(1) | 0); 345 if ((fe->fe_cx & FPSCR_FI) || 346 (fe->fe_fpscr & FPSCR_UX)) 347 fe->fe_cx |= FPSCR_UX; 348 return (sign | SNG_EXP(0) | fp->fp_mant[3]); 349 } 350 /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */ 351 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS); 352 #ifdef DIAGNOSTIC 353 if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0) 354 panic("fpu_ftos"); 355 #endif 356 if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2)) 357 exp++; 358 if (exp >= SNG_EXP_INFNAN) { 359 /* overflow to inf or to max single */ 360 if (toinf(fe, sign)) 361 return (sign | SNG_EXP(SNG_EXP_INFNAN)); 362 return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK); 363 } 364 done: 365 /* phew, made it */ 366 return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK)); 367 } 368 369 /* 370 * fpn -> double (32 bit high-order result returned; 32-bit low order result 371 * left in res[1]). Assumes <= 61 bits in double precision fraction. 372 * 373 * This code mimics fpu_ftos; see it for comments. 374 */ 375 u_int 376 fpu_ftod(struct fpemu *fe, struct fpn *fp, u_int *res) 377 { 378 u_int sign = fp->fp_sign << 31; 379 int exp; 380 381 #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31)) 382 #define DBL_MASK (DBL_EXP(1) - 1) 383 384 if (ISNAN(fp)) { 385 (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS); 386 exp = DBL_EXP_INFNAN; 387 goto done; 388 } 389 if (ISINF(fp)) { 390 sign |= DBL_EXP(DBL_EXP_INFNAN); 391 goto zero; 392 } 393 if (ISZERO(fp)) { 394 zero: res[1] = 0; 395 return (sign); 396 } 397 398 if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) { 399 (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp); 400 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) { 401 res[1] = 0; 402 return (sign | DBL_EXP(1) | 0); 403 } 404 if ((fe->fe_cx & FPSCR_FI) || 405 (fe->fe_fpscr & FPSCR_UX)) 406 fe->fe_cx |= FPSCR_UX; 407 exp = 0; 408 goto done; 409 } 410 (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS); 411 if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2)) 412 exp++; 413 if (exp >= DBL_EXP_INFNAN) { 414 fe->fe_cx |= FPSCR_OX | FPSCR_UX; 415 if (toinf(fe, sign)) { 416 res[1] = 0; 417 return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0); 418 } 419 res[1] = ~0; 420 return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK); 421 } 422 done: 423 res[1] = fp->fp_mant[3]; 424 return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK)); 425 } 426 427 /* 428 * Implode an fpn, writing the result into the given space. 429 */ 430 void 431 fpu_implode(struct fpemu *fe, struct fpn *fp, int type, u_int *space) 432 { 433 434 switch (type) { 435 436 case FTYPE_LNG: 437 space[0] = fpu_ftox(fe, fp, space); 438 DPRINTF(FPE_REG, ("fpu_implode: long %x %x\n", 439 space[0], space[1])); 440 break; 441 442 case FTYPE_INT: 443 space[0] = 0; 444 space[1] = fpu_ftoi(fe, fp); 445 DPRINTF(FPE_REG, ("fpu_implode: int %x\n", 446 space[1])); 447 break; 448 449 case FTYPE_SNG: 450 space[0] = fpu_ftos(fe, fp); 451 DPRINTF(FPE_REG, ("fpu_implode: single %x\n", 452 space[0])); 453 break; 454 455 case FTYPE_DBL: 456 space[0] = fpu_ftod(fe, fp, space); 457 DPRINTF(FPE_REG, ("fpu_implode: double %x %x\n", 458 space[0], space[1])); 459 break; break; 460 461 default: 462 panic("fpu_implode: invalid type %d", type); 463 } 464 } 465