1 /* $NetBSD: fpu_explode.c,v 1.6 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 */ 42 43 /* 44 * FPU subroutines: `explode' the machine's `packed binary' format numbers 45 * into our internal format. 46 */ 47 48 #include <sys/cdefs.h> 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 52 #include <machine/fpu.h> 53 #include <machine/ieee.h> 54 #include <machine/pcb.h> 55 56 #include <powerpc/fpu/fpu_arith.h> 57 #include <powerpc/fpu/fpu_emu.h> 58 #include <powerpc/fpu/fpu_extern.h> 59 #include <powerpc/fpu/fpu_instr.h> 60 61 /* 62 * N.B.: in all of the following, we assume the FP format is 63 * 64 * --------------------------- 65 * | s | exponent | fraction | 66 * --------------------------- 67 * 68 * (which represents -1**s * 1.fraction * 2**exponent), so that the 69 * sign bit is way at the top (bit 31), the exponent is next, and 70 * then the remaining bits mark the fraction. A zero exponent means 71 * zero or denormalized (0.fraction rather than 1.fraction), and the 72 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 73 * 74 * Since the sign bit is always the topmost bit---this holds even for 75 * integers---we set that outside all the *tof functions. Each function 76 * returns the class code for the new number (but note that we use 77 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 78 */ 79 80 /* 81 * int -> fpn. 82 */ 83 int 84 fpu_itof(struct fpn *fp, u_int i) 85 { 86 87 if (i == 0) 88 return (FPC_ZERO); 89 /* 90 * The value FP_1 represents 2^FP_LG, so set the exponent 91 * there and let normalization fix it up. Convert negative 92 * numbers to sign-and-magnitude. Note that this relies on 93 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 94 */ 95 fp->fp_exp = FP_LG; 96 fp->fp_mant[0] = (int)i < 0 ? -i : i; 97 fp->fp_mant[1] = 0; 98 fp->fp_mant[2] = 0; 99 fp->fp_mant[3] = 0; 100 fpu_norm(fp); 101 return (FPC_NUM); 102 } 103 104 /* 105 * 64-bit int -> fpn. 106 */ 107 int 108 fpu_xtof(struct fpn *fp, u_int64_t i) 109 { 110 111 if (i == 0) 112 return (FPC_ZERO); 113 /* 114 * The value FP_1 represents 2^FP_LG, so set the exponent 115 * there and let normalization fix it up. Convert negative 116 * numbers to sign-and-magnitude. Note that this relies on 117 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 118 */ 119 fp->fp_exp = FP_LG2; 120 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 121 fp->fp_mant[2] = 0; 122 fp->fp_mant[3] = 0; 123 fpu_norm(fp); 124 return (FPC_NUM); 125 } 126 127 #define mask(nbits) ((1L << (nbits)) - 1) 128 129 /* 130 * All external floating formats convert to internal in the same manner, 131 * as defined here. Note that only normals get an implied 1.0 inserted. 132 */ 133 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 134 if (exp == 0) { \ 135 if (allfrac == 0) \ 136 return (FPC_ZERO); \ 137 fp->fp_exp = 1 - expbias; \ 138 fp->fp_mant[0] = f0; \ 139 fp->fp_mant[1] = f1; \ 140 fp->fp_mant[2] = f2; \ 141 fp->fp_mant[3] = f3; \ 142 fpu_norm(fp); \ 143 return (FPC_NUM); \ 144 } \ 145 if (exp == (2 * expbias + 1)) { \ 146 if (allfrac == 0) \ 147 return (FPC_INF); \ 148 fp->fp_mant[0] = f0; \ 149 fp->fp_mant[1] = f1; \ 150 fp->fp_mant[2] = f2; \ 151 fp->fp_mant[3] = f3; \ 152 return (FPC_QNAN); \ 153 } \ 154 fp->fp_exp = exp - expbias; \ 155 fp->fp_mant[0] = FP_1 | f0; \ 156 fp->fp_mant[1] = f1; \ 157 fp->fp_mant[2] = f2; \ 158 fp->fp_mant[3] = f3; \ 159 return (FPC_NUM) 160 161 /* 162 * 32-bit single precision -> fpn. 163 * We assume a single occupies at most (64-FP_LG) bits in the internal 164 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 165 */ 166 int 167 fpu_stof(struct fpn *fp, u_int i) 168 { 169 int exp; 170 u_int frac, f0, f1; 171 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 172 173 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 174 frac = i & mask(SNG_FRACBITS); 175 f0 = frac >> SNG_SHIFT; 176 f1 = frac << (32 - SNG_SHIFT); 177 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 178 } 179 180 /* 181 * 64-bit double -> fpn. 182 * We assume this uses at most (96-FP_LG) bits. 183 */ 184 int 185 fpu_dtof(struct fpn *fp, u_int i, u_int j) 186 { 187 int exp; 188 u_int frac, f0, f1, f2; 189 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 190 191 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 192 frac = i & mask(DBL_FRACBITS - 32); 193 f0 = frac >> DBL_SHIFT; 194 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 195 f2 = j << (32 - DBL_SHIFT); 196 frac |= j; 197 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 198 } 199 200 /* 201 * Explode the contents of a register / regpair / regquad. 202 * If the input is a signalling NaN, an NV (invalid) exception 203 * will be set. (Note that nothing but NV can occur until ALU 204 * operations are performed.) 205 */ 206 void 207 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg) 208 { 209 u_int s, *space; 210 u_int64_t l, *xspace; 211 212 xspace = (u_int64_t *)&fe->fe_fpstate->fpr[reg].fpr; 213 l = xspace[0]; 214 space = (u_int *)&fe->fe_fpstate->fpr[reg].fpr; 215 s = space[0]; 216 fp->fp_sign = s >> 31; 217 fp->fp_sticky = 0; 218 switch (type) { 219 case FTYPE_LNG: 220 s = fpu_xtof(fp, l); 221 break; 222 223 case FTYPE_INT: 224 s = fpu_itof(fp, space[1]); 225 break; 226 227 case FTYPE_SNG: 228 s = fpu_stof(fp, s); 229 break; 230 231 case FTYPE_DBL: 232 s = fpu_dtof(fp, s, space[1]); 233 break; 234 235 default: 236 panic("fpu_explode"); 237 panic("fpu_explode: invalid type %d", type); 238 } 239 240 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 241 /* 242 * Input is a signalling NaN. All operations that return 243 * an input NaN operand put it through a ``NaN conversion'', 244 * which basically just means ``turn on the quiet bit''. 245 * We do this here so that all NaNs internally look quiet 246 * (we can tell signalling ones by their class). 247 */ 248 fp->fp_mant[0] |= FP_QUIETBIT; 249 fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */ 250 s = FPC_SNAN; 251 } 252 fp->fp_class = s; 253 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 254 ((type == FTYPE_INT) ? 'i' : 255 ((type == FTYPE_SNG) ? 's' : 256 ((type == FTYPE_DBL) ? 'd' : '?'))), 257 reg)); 258 DUMPFPN(FPE_REG, fp); 259 DPRINTF(FPE_REG, ("\n")); 260 } 261