1 /* $NetBSD: fpu_emu.h,v 1.3 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * Floating point emulator (tailored for SPARC, but structurally 47 * machine-independent). 48 * 49 * Floating point numbers are carried around internally in an `expanded' 50 * or `unpacked' form consisting of: 51 * - sign 52 * - unbiased exponent 53 * - mantissa (`1.' + 112-bit fraction + guard + round) 54 * - sticky bit 55 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 56 * always nonzero. Additional low-order `guard' and `round' bits are 57 * scrunched in, making the entire mantissa 115 bits long. This is divided 58 * into four 32-bit words, with `spare' bits left over in the upper part 59 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 60 * number is thus kept within the half-open interval [1.0,2.0) (but see 61 * the `number classes' below). This holds even for denormalized numbers: 62 * when we explode an external denorm, we normalize it, introducing low-order 63 * zero bits, so that the rest of the code always sees normalized values. 64 * 65 * Note that a number of our algorithms use the `spare' bits at the top. 66 * The most demanding algorithm---the one for sqrt---depends on two such 67 * bits, so that it can represent values up to (but not including) 8.0, 68 * and then it needs a carry on top of that, so that we need three `spares'. 69 * 70 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 71 * whole words from the mantissa into it. 72 * 73 * All operations are done in this internal extended precision. According 74 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 75 * it is OK to do a+b in extended precision and then round the result to 76 * single precision---provided single, double, and extended precisions are 77 * `far enough apart' (they always are), but we will try to avoid any such 78 * extra work where possible. 79 */ 80 struct fpn { 81 int fp_class; /* see below */ 82 int fp_sign; /* 0 => positive, 1 => negative */ 83 int fp_exp; /* exponent (unbiased) */ 84 int fp_sticky; /* nonzero bits lost at right end */ 85 u_int fp_mant[4]; /* 115-bit mantissa */ 86 }; 87 88 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 89 #define FP_NG 2 /* number of low-order guard bits */ 90 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 91 #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 92 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 93 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 94 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 95 96 /* 97 * Number classes. Since zero, Inf, and NaN cannot be represented using 98 * the above layout, we distinguish these from other numbers via a class. 99 * In addition, to make computation easier and to follow Appendix N of 100 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 101 */ 102 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 103 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 104 #define FPC_ZERO 0 /* zero (sign matters) */ 105 #define FPC_NUM 1 /* number (sign matters) */ 106 #define FPC_INF 2 /* infinity (sign matters) */ 107 108 #define ISSNAN(fp) ((fp)->fp_class == FPC_SNAN) 109 #define ISQNAN(fp) ((fp)->fp_class == FPC_QNAN) 110 #define ISNAN(fp) ((fp)->fp_class < 0) 111 #define ISZERO(fp) ((fp)->fp_class == 0) 112 #define ISINF(fp) ((fp)->fp_class == FPC_INF) 113 114 /* 115 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 116 * to the `more significant' operand for our purposes. Appendix N says that 117 * the result of a computation involving two numbers are: 118 * 119 * If both are SNaN: operand 2, converted to Quiet 120 * If only one is SNaN: the SNaN operand, converted to Quiet 121 * If both are QNaN: operand 2 122 * If only one is QNaN: the QNaN operand 123 * 124 * In addition, in operations with an Inf operand, the result is usually 125 * Inf. The class numbers are carefully arranged so that if 126 * (unsigned)class(op1) > (unsigned)class(op2) 127 * then op1 is the one we want; otherwise op2 is the one we want. 128 */ 129 #define ORDER(x, y) { \ 130 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 131 SWAP(x, y); \ 132 } 133 #define SWAP(x, y) { \ 134 struct fpn *swap; \ 135 swap = (x), (x) = (y), (y) = swap; \ 136 } 137 138 /* 139 * Emulator state. 140 */ 141 struct fpemu { 142 struct fpu *fe_fpstate; /* registers, etc */ 143 int fe_fpscr; /* fpscr copy (modified during op) */ 144 int fe_cx; /* keep track of exceptions */ 145 struct fpn fe_f1; /* operand 1 */ 146 struct fpn fe_f2; /* operand 2, if required */ 147 struct fpn fe_f3; /* available storage for result */ 148 }; 149 150 /* 151 * Arithmetic functions. 152 * Each of these may modify its inputs (f1,f2) and/or the temporary. 153 * Each returns a pointer to the result and/or sets exceptions. 154 */ 155 struct fpn *fpu_add(struct fpemu *); 156 #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe)) 157 struct fpn *fpu_mul(struct fpemu *); 158 struct fpn *fpu_div(struct fpemu *); 159 struct fpn *fpu_sqrt(struct fpemu *); 160 161 /* 162 * Other functions. 163 */ 164 165 /* Perform a compare instruction (with or without unordered exception). */ 166 void fpu_compare(struct fpemu *, int); 167 168 /* Build a new Quiet NaN (sign=0, frac=all 1's). */ 169 struct fpn *fpu_newnan(struct fpemu *); 170 171 void fpu_norm(struct fpn *); 172 173 /* 174 * Shift a number right some number of bits, taking care of round/sticky. 175 * Note that the result is probably not a well-formed number (it will lack 176 * the normal 1-bit mant[0]&FP_1). 177 */ 178 int fpu_shr(struct fpn *, int); 179 180 void fpu_explode(struct fpemu *, struct fpn *, int, int); 181 void fpu_implode(struct fpemu *, struct fpn *, int, u_int *); 182 183 #ifdef DEBUG 184 #define FPE_EX 0x1 185 #define FPE_INSN 0x2 186 #define FPE_OP 0x4 187 #define FPE_REG 0x8 188 extern int fpe_debug; 189 void fpu_dumpfpn(struct fpn *); 190 #define DPRINTF(x, y) if (fpe_debug & (x)) printf y 191 #define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f)) 192 #else 193 #define DPRINTF(x, y) 194 #define DUMPFPN(x, f) 195 #endif 196