1 /* $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright 2001 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1992, 1993 42 * The Regents of the University of California. All rights reserved. 43 * 44 * This software was developed by the Computer Systems Engineering group 45 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 46 * contributed to Berkeley. 47 * 48 * All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the University of 51 * California, Lawrence Berkeley Laboratory. 52 * 53 * Redistribution and use in source and binary forms, with or without 54 * modification, are permitted provided that the following conditions 55 * are met: 56 * 1. Redistributions of source code must retain the above copyright 57 * notice, this list of conditions and the following disclaimer. 58 * 2. Redistributions in binary form must reproduce the above copyright 59 * notice, this list of conditions and the following disclaimer in the 60 * documentation and/or other materials provided with the distribution. 61 * 3. Neither the name of the University nor the names of its contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 75 * SUCH DAMAGE. 76 * 77 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 78 */ 79 80 #include <sys/cdefs.h> 81 __FBSDID("$FreeBSD$"); 82 83 #include "opt_ddb.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kdb.h> 88 #include <sys/kernel.h> 89 #include <sys/proc.h> 90 #include <sys/sysctl.h> 91 #include <sys/signal.h> 92 #include <sys/syslog.h> 93 #include <sys/signalvar.h> 94 95 #include <machine/fpu.h> 96 97 #include <powerpc/fpu/fpu_emu.h> 98 #include <powerpc/fpu/fpu_extern.h> 99 #include <powerpc/fpu/fpu_instr.h> 100 101 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 102 "FPU emulator"); 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static u_int fpu_emu_evcnt_##name; \ 106 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD, \ 107 &fpu_emu_evcnt_##name, 0, "") 108 109 #define FPU_EMU_EVCNT_INCR(name) fpu_emu_evcnt_##name++ 110 111 FPU_EMU_EVCNT_DECL(stfiwx); 112 FPU_EMU_EVCNT_DECL(fpstore); 113 FPU_EMU_EVCNT_DECL(fpload); 114 FPU_EMU_EVCNT_DECL(fcmpu); 115 FPU_EMU_EVCNT_DECL(frsp); 116 FPU_EMU_EVCNT_DECL(fctiw); 117 FPU_EMU_EVCNT_DECL(fcmpo); 118 FPU_EMU_EVCNT_DECL(mtfsb1); 119 FPU_EMU_EVCNT_DECL(fnegabs); 120 FPU_EMU_EVCNT_DECL(mcrfs); 121 FPU_EMU_EVCNT_DECL(mtfsb0); 122 FPU_EMU_EVCNT_DECL(fmr); 123 FPU_EMU_EVCNT_DECL(mtfsfi); 124 FPU_EMU_EVCNT_DECL(fnabs); 125 FPU_EMU_EVCNT_DECL(fabs); 126 FPU_EMU_EVCNT_DECL(mffs); 127 FPU_EMU_EVCNT_DECL(mtfsf); 128 FPU_EMU_EVCNT_DECL(fctid); 129 FPU_EMU_EVCNT_DECL(fcfid); 130 FPU_EMU_EVCNT_DECL(fdiv); 131 FPU_EMU_EVCNT_DECL(fsub); 132 FPU_EMU_EVCNT_DECL(fadd); 133 FPU_EMU_EVCNT_DECL(fsqrt); 134 FPU_EMU_EVCNT_DECL(fsel); 135 FPU_EMU_EVCNT_DECL(fpres); 136 FPU_EMU_EVCNT_DECL(fmul); 137 FPU_EMU_EVCNT_DECL(frsqrte); 138 FPU_EMU_EVCNT_DECL(fmulsub); 139 FPU_EMU_EVCNT_DECL(fmuladd); 140 FPU_EMU_EVCNT_DECL(fnmsub); 141 FPU_EMU_EVCNT_DECL(fnmadd); 142 143 /* FPSR exception masks */ 144 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 145 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 146 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 147 FPSCR_VXSQRT|FPSCR_VXCVI) 148 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 149 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 150 151 int fpe_debug = 0; 152 153 #ifdef DEBUG 154 vm_offset_t opc_disasm(vm_offset_t, int); 155 156 /* 157 * Dump a `fpn' structure. 158 */ 159 void 160 fpu_dumpfpn(struct fpn *fp) 161 { 162 static const char *class[] = { 163 "SNAN", "QNAN", "ZERO", "NUM", "INF" 164 }; 165 166 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 167 fp->fp_sign ? '-' : ' ', 168 fp->fp_mant[0], fp->fp_mant[1], 169 fp->fp_mant[2], fp->fp_mant[3], 170 fp->fp_exp); 171 } 172 #endif 173 174 /* 175 * fpu_execute returns the following error numbers (0 = no error): 176 */ 177 #define FPE 1 /* take a floating point exception */ 178 #define NOTFPU 2 /* not an FPU instruction */ 179 #define FAULT 3 180 181 /* 182 * Emulate a floating-point instruction. 183 * Return zero for success, else signal number. 184 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 185 */ 186 int 187 fpu_emulate(struct trapframe *frame, struct fpu *fpf) 188 { 189 union instr insn; 190 struct fpemu fe; 191 int sig; 192 193 /* initialize insn.is_datasize to tell it is *not* initialized */ 194 fe.fe_fpstate = fpf; 195 fe.fe_cx = 0; 196 197 /* always set this (to avoid a warning) */ 198 199 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 200 #ifdef DEBUG 201 printf("fpu_emulate: fault reading opcode\n"); 202 #endif 203 return SIGSEGV; 204 } 205 206 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 207 insn.i_int, (void *)frame->srr0)); 208 209 if ((insn.i_any.i_opcd == OPC_TWI) || 210 ((insn.i_any.i_opcd == OPC_integer_31) && 211 (insn.i_x.i_xo == OPC31_TW))) { 212 /* Check for the two trap insns. */ 213 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 214 return (SIGTRAP); 215 } 216 sig = 0; 217 switch (fpu_execute(frame, &fe, &insn)) { 218 case 0: 219 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 220 frame->srr0 += 4; 221 break; 222 223 case FPE: 224 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 225 sig = SIGFPE; 226 break; 227 228 case FAULT: 229 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 230 sig = SIGSEGV; 231 break; 232 233 case NOTFPU: 234 default: 235 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 236 #ifdef DEBUG 237 if (fpe_debug & FPE_EX) { 238 printf("fpu_emulate: illegal insn %x at %p:", 239 insn.i_int, (void *) (frame->srr0)); 240 opc_disasm(frame->srr0, insn.i_int); 241 } 242 #endif 243 sig = SIGILL; 244 #ifdef DEBUG 245 if (fpe_debug & FPE_EX) 246 kdb_enter(KDB_WHY_UNSET, "illegal instruction"); 247 #endif 248 break; 249 } 250 251 return (sig); 252 } 253 254 /* 255 * Execute an FPU instruction (one that runs entirely in the FPU; not 256 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 257 * modified to reflect the setting the hardware would have left. 258 * 259 * Note that we do not catch all illegal opcodes, so you can, for instance, 260 * multiply two integers this way. 261 */ 262 int 263 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 264 { 265 struct fpn *fp; 266 union instr instr = *insn; 267 int *a; 268 vm_offset_t addr; 269 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 270 unsigned int cond; 271 struct fpu *fs; 272 273 /* Setup work. */ 274 fp = NULL; 275 fs = fe->fe_fpstate; 276 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 277 278 /* 279 * On PowerPC all floating point values are stored in registers 280 * as doubles, even when used for single precision operations. 281 */ 282 type = FTYPE_DBL; 283 cond = instr.i_any.i_rc; 284 setcr = 0; 285 bf = 0; /* XXX gcc */ 286 287 #if defined(DDB) && defined(DEBUG) 288 if (fpe_debug & FPE_EX) { 289 vm_offset_t loc = tf->srr0; 290 291 printf("Trying to emulate: %p ", (void *)loc); 292 opc_disasm(loc, instr.i_int); 293 } 294 #endif 295 296 /* 297 * `Decode' and execute instruction. 298 */ 299 300 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 301 instr.i_any.i_opcd == OPC_integer_31) { 302 /* 303 * Handle load/store insns: 304 * 305 * Convert to/from single if needed, calculate addr, 306 * and update index reg if needed. 307 */ 308 double buf; 309 size_t size = sizeof(float); 310 int store, update; 311 312 cond = 0; /* ld/st never set condition codes */ 313 314 if (instr.i_any.i_opcd == OPC_integer_31) { 315 if (instr.i_x.i_xo == OPC31_STFIWX) { 316 FPU_EMU_EVCNT_INCR(stfiwx); 317 318 /* Store as integer */ 319 ra = instr.i_x.i_ra; 320 rb = instr.i_x.i_rb; 321 DPRINTF(FPE_INSN, 322 ("reg %d has %jx reg %d has %jx\n", 323 ra, (uintmax_t)tf->fixreg[ra], rb, 324 (uintmax_t)tf->fixreg[rb])); 325 326 addr = tf->fixreg[rb]; 327 if (ra != 0) 328 addr += tf->fixreg[ra]; 329 rt = instr.i_x.i_rt; 330 a = (int *)&fs->fpr[rt].fpr; 331 DPRINTF(FPE_INSN, 332 ("fpu_execute: Store INT %x at %p\n", 333 a[1], (void *)addr)); 334 if (copyout(&a[1], (void *)addr, sizeof(int))) 335 return (FAULT); 336 return (0); 337 } 338 339 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 340 /* Not an indexed FP load/store op */ 341 return (NOTFPU); 342 343 store = (instr.i_x.i_xo & 0x80); 344 if (instr.i_x.i_xo & 0x40) 345 size = sizeof(double); 346 else 347 type = FTYPE_SNG; 348 update = (instr.i_x.i_xo & 0x20); 349 350 /* calculate EA of load/store */ 351 ra = instr.i_x.i_ra; 352 rb = instr.i_x.i_rb; 353 DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n", 354 ra, (uintmax_t)tf->fixreg[ra], rb, 355 (uintmax_t)tf->fixreg[rb])); 356 addr = tf->fixreg[rb]; 357 if (ra != 0) 358 addr += tf->fixreg[ra]; 359 rt = instr.i_x.i_rt; 360 } else { 361 store = instr.i_d.i_opcd & 0x4; 362 if (instr.i_d.i_opcd & 0x2) 363 size = sizeof(double); 364 else 365 type = FTYPE_SNG; 366 update = instr.i_d.i_opcd & 0x1; 367 368 /* calculate EA of load/store */ 369 ra = instr.i_d.i_ra; 370 addr = instr.i_d.i_d; 371 DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n", 372 ra, (uintmax_t)tf->fixreg[ra], 373 (uintmax_t)addr)); 374 if (ra != 0) 375 addr += tf->fixreg[ra]; 376 rt = instr.i_d.i_rt; 377 } 378 379 if (update && ra == 0) 380 return (NOTFPU); 381 382 if (store) { 383 /* Store */ 384 FPU_EMU_EVCNT_INCR(fpstore); 385 if (type != FTYPE_DBL) { 386 DPRINTF(FPE_INSN, 387 ("fpu_execute: Store SNG at %p\n", 388 (void *)addr)); 389 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 390 fpu_implode(fe, fp, type, (void *)&buf); 391 if (copyout(&buf, (void *)addr, size)) 392 return (FAULT); 393 } else { 394 DPRINTF(FPE_INSN, 395 ("fpu_execute: Store DBL at %p\n", 396 (void *)addr)); 397 if (copyout(&fs->fpr[rt].fpr, (void *)addr, 398 size)) 399 return (FAULT); 400 } 401 } else { 402 /* Load */ 403 FPU_EMU_EVCNT_INCR(fpload); 404 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 405 (void *)addr)); 406 if (copyin((const void *)addr, &fs->fpr[rt].fpr, 407 size)) 408 return (FAULT); 409 if (type != FTYPE_DBL) { 410 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 411 fpu_implode(fe, fp, FTYPE_DBL, 412 (u_int *)&fs->fpr[rt].fpr); 413 } 414 } 415 if (update) 416 tf->fixreg[ra] = addr; 417 /* Complete. */ 418 return (0); 419 #ifdef notyet 420 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 421 /* These are 64-bit extensions */ 422 return (NOTFPU); 423 #endif 424 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 425 instr.i_any.i_opcd == OPC_dp_fp_63) { 426 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 427 !(instr.i_a.i_xo & OPC63M_MASK)) { 428 /* Format X */ 429 rt = instr.i_x.i_rt; 430 ra = instr.i_x.i_ra; 431 rb = instr.i_x.i_rb; 432 433 /* One of the special opcodes.... */ 434 switch (instr.i_x.i_xo) { 435 case OPC63_FCMPU: 436 FPU_EMU_EVCNT_INCR(fcmpu); 437 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 438 rt >>= 2; 439 fpu_explode(fe, &fe->fe_f1, type, ra); 440 fpu_explode(fe, &fe->fe_f2, type, rb); 441 fpu_compare(fe, 0); 442 /* Make sure we do the condition regs. */ 443 cond = 0; 444 /* N.B.: i_rs is already left shifted by two. */ 445 bf = instr.i_x.i_rs & 0xfc; 446 setcr = 1; 447 break; 448 449 case OPC63_FRSP: 450 /* 451 * Convert to single: 452 * 453 * PowerPC uses this to round a double 454 * precision value to single precision, 455 * but values in registers are always 456 * stored in double precision format. 457 */ 458 FPU_EMU_EVCNT_INCR(frsp); 459 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 460 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 461 fpu_implode(fe, fp, FTYPE_SNG, 462 (u_int *)&fs->fpr[rt].fpr); 463 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 464 type = FTYPE_DBL; 465 break; 466 case OPC63_FCTIW: 467 case OPC63_FCTIWZ: 468 FPU_EMU_EVCNT_INCR(fctiw); 469 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 470 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 471 type = FTYPE_INT; 472 break; 473 case OPC63_FCMPO: 474 FPU_EMU_EVCNT_INCR(fcmpo); 475 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 476 rt >>= 2; 477 fpu_explode(fe, &fe->fe_f1, type, ra); 478 fpu_explode(fe, &fe->fe_f2, type, rb); 479 fpu_compare(fe, 1); 480 /* Make sure we do the condition regs. */ 481 cond = 0; 482 /* N.B.: i_rs is already left shifted by two. */ 483 bf = instr.i_x.i_rs & 0xfc; 484 setcr = 1; 485 break; 486 case OPC63_MTFSB1: 487 FPU_EMU_EVCNT_INCR(mtfsb1); 488 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 489 fe->fe_fpscr |= 490 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 491 break; 492 case OPC63_FNEG: 493 FPU_EMU_EVCNT_INCR(fnegabs); 494 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 495 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 496 sizeof(double)); 497 a = (int *)&fs->fpr[rt].fpr; 498 *a ^= (1U << 31); 499 break; 500 case OPC63_MCRFS: 501 FPU_EMU_EVCNT_INCR(mcrfs); 502 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 503 cond = 0; 504 rt &= 0x1c; 505 ra &= 0x1c; 506 /* Extract the bits we want */ 507 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 508 /* Clear the bits we copied. */ 509 fe->fe_cx = 510 (FPSR_EX_MSK | (0xf << (28 - ra))); 511 fe->fe_fpscr &= fe->fe_cx; 512 /* Now shove them in the right part of cr */ 513 tf->cr &= ~(0xf << (28 - rt)); 514 tf->cr |= (mask << (28 - rt)); 515 break; 516 case OPC63_MTFSB0: 517 FPU_EMU_EVCNT_INCR(mtfsb0); 518 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 519 fe->fe_fpscr &= 520 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 521 break; 522 case OPC63_FMR: 523 FPU_EMU_EVCNT_INCR(fmr); 524 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 525 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 526 sizeof(double)); 527 break; 528 case OPC63_MTFSFI: 529 FPU_EMU_EVCNT_INCR(mtfsfi); 530 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 531 rb >>= 1; 532 rt &= 0x1c; /* Already left-shifted 4 */ 533 fe->fe_cx = rb << (28 - rt); 534 mask = 0xf<<(28 - rt); 535 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 536 fe->fe_cx; 537 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 538 break; 539 case OPC63_FNABS: 540 FPU_EMU_EVCNT_INCR(fnabs); 541 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 542 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 543 sizeof(double)); 544 a = (int *)&fs->fpr[rt].fpr; 545 *a |= (1U << 31); 546 break; 547 case OPC63_FABS: 548 FPU_EMU_EVCNT_INCR(fabs); 549 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 550 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 551 sizeof(double)); 552 a = (int *)&fs->fpr[rt].fpr; 553 *a &= ~(1U << 31); 554 break; 555 case OPC63_MFFS: 556 FPU_EMU_EVCNT_INCR(mffs); 557 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 558 memcpy(&fs->fpr[rt].fpr, &fs->fpscr, 559 sizeof(fs->fpscr)); 560 break; 561 case OPC63_MTFSF: 562 FPU_EMU_EVCNT_INCR(mtfsf); 563 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 564 if ((rt = instr.i_xfl.i_flm) == -1) 565 mask = -1; 566 else { 567 mask = 0; 568 /* Convert 1 bit -> 4 bits */ 569 for (ra = 0; ra < 8; ra ++) 570 if (rt & (1<<ra)) 571 mask |= (0xf<<(4*ra)); 572 } 573 a = (int *)&fs->fpr[rt].fpr; 574 fe->fe_cx = mask & a[1]; 575 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 576 (fe->fe_cx); 577 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 578 break; 579 case OPC63_FCTID: 580 case OPC63_FCTIDZ: 581 FPU_EMU_EVCNT_INCR(fctid); 582 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 583 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 584 type = FTYPE_LNG; 585 break; 586 case OPC63_FCFID: 587 FPU_EMU_EVCNT_INCR(fcfid); 588 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 589 type = FTYPE_LNG; 590 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 591 type = FTYPE_DBL; 592 break; 593 default: 594 return (NOTFPU); 595 break; 596 } 597 } else { 598 /* Format A */ 599 rt = instr.i_a.i_frt; 600 ra = instr.i_a.i_fra; 601 rb = instr.i_a.i_frb; 602 rc = instr.i_a.i_frc; 603 604 /* 605 * All arithmetic operations work on registers, which 606 * are stored as doubles. 607 */ 608 type = FTYPE_DBL; 609 switch ((unsigned int)instr.i_a.i_xo) { 610 case OPC59_FDIVS: 611 FPU_EMU_EVCNT_INCR(fdiv); 612 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 613 fpu_explode(fe, &fe->fe_f1, type, ra); 614 fpu_explode(fe, &fe->fe_f2, type, rb); 615 fp = fpu_div(fe); 616 break; 617 case OPC59_FSUBS: 618 FPU_EMU_EVCNT_INCR(fsub); 619 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 620 fpu_explode(fe, &fe->fe_f1, type, ra); 621 fpu_explode(fe, &fe->fe_f2, type, rb); 622 fp = fpu_sub(fe); 623 break; 624 case OPC59_FADDS: 625 FPU_EMU_EVCNT_INCR(fadd); 626 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 627 fpu_explode(fe, &fe->fe_f1, type, ra); 628 fpu_explode(fe, &fe->fe_f2, type, rb); 629 fp = fpu_add(fe); 630 break; 631 case OPC59_FSQRTS: 632 FPU_EMU_EVCNT_INCR(fsqrt); 633 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 634 fpu_explode(fe, &fe->fe_f1, type, rb); 635 fp = fpu_sqrt(fe); 636 break; 637 case OPC63M_FSEL: 638 FPU_EMU_EVCNT_INCR(fsel); 639 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 640 a = (int *)&fe->fe_fpstate->fpr[ra].fpr; 641 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 642 /* fra < 0 */ 643 rc = rb; 644 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 645 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr, 646 sizeof(double)); 647 break; 648 case OPC59_FRES: 649 FPU_EMU_EVCNT_INCR(fpres); 650 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 651 fpu_explode(fe, &fe->fe_f1, type, rb); 652 fp = fpu_sqrt(fe); 653 /* now we've gotta overwrite the dest reg */ 654 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 655 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 656 fpu_div(fe); 657 break; 658 case OPC59_FMULS: 659 FPU_EMU_EVCNT_INCR(fmul); 660 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 661 fpu_explode(fe, &fe->fe_f1, type, ra); 662 fpu_explode(fe, &fe->fe_f2, type, rc); 663 fp = fpu_mul(fe); 664 break; 665 case OPC63M_FRSQRTE: 666 /* Reciprocal sqrt() estimate */ 667 FPU_EMU_EVCNT_INCR(frsqrte); 668 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 669 fpu_explode(fe, &fe->fe_f1, type, rb); 670 fp = fpu_sqrt(fe); 671 fe->fe_f2 = *fp; 672 /* now we've gotta overwrite the dest reg */ 673 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 674 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 675 fpu_div(fe); 676 break; 677 case OPC59_FMSUBS: 678 FPU_EMU_EVCNT_INCR(fmulsub); 679 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 680 fpu_explode(fe, &fe->fe_f1, type, ra); 681 fpu_explode(fe, &fe->fe_f2, type, rc); 682 fp = fpu_mul(fe); 683 fe->fe_f1 = *fp; 684 fpu_explode(fe, &fe->fe_f2, type, rb); 685 fp = fpu_sub(fe); 686 break; 687 case OPC59_FMADDS: 688 FPU_EMU_EVCNT_INCR(fmuladd); 689 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 690 fpu_explode(fe, &fe->fe_f1, type, ra); 691 fpu_explode(fe, &fe->fe_f2, type, rc); 692 fp = fpu_mul(fe); 693 fe->fe_f1 = *fp; 694 fpu_explode(fe, &fe->fe_f2, type, rb); 695 fp = fpu_add(fe); 696 break; 697 case OPC59_FNMSUBS: 698 FPU_EMU_EVCNT_INCR(fnmsub); 699 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 700 fpu_explode(fe, &fe->fe_f1, type, ra); 701 fpu_explode(fe, &fe->fe_f2, type, rc); 702 fp = fpu_mul(fe); 703 fe->fe_f1 = *fp; 704 fpu_explode(fe, &fe->fe_f2, type, rb); 705 fp = fpu_sub(fe); 706 /* Negate */ 707 fp->fp_sign ^= 1; 708 break; 709 case OPC59_FNMADDS: 710 FPU_EMU_EVCNT_INCR(fnmadd); 711 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 712 fpu_explode(fe, &fe->fe_f1, type, ra); 713 fpu_explode(fe, &fe->fe_f2, type, rc); 714 fp = fpu_mul(fe); 715 fe->fe_f1 = *fp; 716 fpu_explode(fe, &fe->fe_f2, type, rb); 717 fp = fpu_add(fe); 718 /* Negate */ 719 fp->fp_sign ^= 1; 720 break; 721 default: 722 return (NOTFPU); 723 break; 724 } 725 726 /* If the instruction was single precision, round */ 727 if (!(instr.i_any.i_opcd & 0x4)) { 728 fpu_implode(fe, fp, FTYPE_SNG, 729 (u_int *)&fs->fpr[rt].fpr); 730 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 731 } 732 } 733 } else { 734 return (NOTFPU); 735 } 736 737 /* 738 * ALU operation is complete. Collapse the result and then check 739 * for exceptions. If we got any, and they are enabled, do not 740 * alter the destination register, just stop with an exception. 741 * Otherwise set new current exceptions and accrue. 742 */ 743 if (fp) 744 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr); 745 cx = fe->fe_cx; 746 fsr = fe->fe_fpscr; 747 if (cx != 0) { 748 fsr &= ~FPSCR_FX; 749 if ((cx^fsr)&FPSR_EX_MSK) 750 fsr |= FPSCR_FX; 751 mask = fsr & FPSR_EX; 752 mask <<= (25-3); 753 if (cx & mask) 754 fsr |= FPSCR_FEX; 755 if (cx & FPSCR_FPRF) { 756 /* Need to replace CC */ 757 fsr &= ~FPSCR_FPRF; 758 } 759 if (cx & (FPSR_EXOP)) 760 fsr |= FPSCR_VX; 761 fsr |= cx; 762 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 763 } 764 765 if (cond) { 766 cond = fsr & 0xf0000000; 767 /* Isolate condition codes */ 768 cond >>= 28; 769 /* Move fpu condition codes to cr[1] */ 770 tf->cr &= (0x0f000000); 771 tf->cr |= (cond<<24); 772 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 773 } 774 775 if (setcr) { 776 cond = fsr & FPSCR_FPCC; 777 /* Isolate condition codes */ 778 cond <<= 16; 779 /* Move fpu condition codes to cr[1] */ 780 tf->cr &= ~(0xf0000000>>bf); 781 tf->cr |= (cond>>bf); 782 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n", 783 bf/4, (uintmax_t)tf->cr, cond)); 784 } 785 786 ((int *)&fs->fpscr)[1] = fsr; 787 if (fsr & FPSCR_FEX) 788 return(FPE); 789 return (0); /* success */ 790 } 791