1 /* $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright 2001 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1992, 1993 42 * The Regents of the University of California. All rights reserved. 43 * 44 * This software was developed by the Computer Systems Engineering group 45 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 46 * contributed to Berkeley. 47 * 48 * All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the University of 51 * California, Lawrence Berkeley Laboratory. 52 * 53 * Redistribution and use in source and binary forms, with or without 54 * modification, are permitted provided that the following conditions 55 * are met: 56 * 1. Redistributions of source code must retain the above copyright 57 * notice, this list of conditions and the following disclaimer. 58 * 2. Redistributions in binary form must reproduce the above copyright 59 * notice, this list of conditions and the following disclaimer in the 60 * documentation and/or other materials provided with the distribution. 61 * 3. Neither the name of the University nor the names of its contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 75 * SUCH DAMAGE. 76 * 77 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 78 */ 79 80 #include <sys/cdefs.h> 81 #include "opt_ddb.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/kdb.h> 86 #include <sys/kernel.h> 87 #include <sys/proc.h> 88 #include <sys/sysctl.h> 89 #include <sys/signal.h> 90 #include <sys/syslog.h> 91 #include <sys/signalvar.h> 92 93 #include <machine/fpu.h> 94 95 #include <powerpc/fpu/fpu_emu.h> 96 #include <powerpc/fpu/fpu_extern.h> 97 #include <powerpc/fpu/fpu_instr.h> 98 99 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 100 "FPU emulator"); 101 102 #define FPU_EMU_EVCNT_DECL(name) \ 103 static u_int fpu_emu_evcnt_##name; \ 104 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD, \ 105 &fpu_emu_evcnt_##name, 0, "") 106 107 #define FPU_EMU_EVCNT_INCR(name) fpu_emu_evcnt_##name++ 108 109 FPU_EMU_EVCNT_DECL(stfiwx); 110 FPU_EMU_EVCNT_DECL(fpstore); 111 FPU_EMU_EVCNT_DECL(fpload); 112 FPU_EMU_EVCNT_DECL(fcmpu); 113 FPU_EMU_EVCNT_DECL(frsp); 114 FPU_EMU_EVCNT_DECL(fctiw); 115 FPU_EMU_EVCNT_DECL(fcmpo); 116 FPU_EMU_EVCNT_DECL(mtfsb1); 117 FPU_EMU_EVCNT_DECL(fnegabs); 118 FPU_EMU_EVCNT_DECL(mcrfs); 119 FPU_EMU_EVCNT_DECL(mtfsb0); 120 FPU_EMU_EVCNT_DECL(fmr); 121 FPU_EMU_EVCNT_DECL(mtfsfi); 122 FPU_EMU_EVCNT_DECL(fnabs); 123 FPU_EMU_EVCNT_DECL(fabs); 124 FPU_EMU_EVCNT_DECL(mffs); 125 FPU_EMU_EVCNT_DECL(mtfsf); 126 FPU_EMU_EVCNT_DECL(fctid); 127 FPU_EMU_EVCNT_DECL(fcfid); 128 FPU_EMU_EVCNT_DECL(fdiv); 129 FPU_EMU_EVCNT_DECL(fsub); 130 FPU_EMU_EVCNT_DECL(fadd); 131 FPU_EMU_EVCNT_DECL(fsqrt); 132 FPU_EMU_EVCNT_DECL(fsel); 133 FPU_EMU_EVCNT_DECL(fpres); 134 FPU_EMU_EVCNT_DECL(fmul); 135 FPU_EMU_EVCNT_DECL(frsqrte); 136 FPU_EMU_EVCNT_DECL(fmulsub); 137 FPU_EMU_EVCNT_DECL(fmuladd); 138 FPU_EMU_EVCNT_DECL(fnmsub); 139 FPU_EMU_EVCNT_DECL(fnmadd); 140 141 /* FPSR exception masks */ 142 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 143 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 144 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 145 FPSCR_VXSQRT|FPSCR_VXCVI) 146 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 147 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 148 149 int fpe_debug = 0; 150 151 #ifdef DEBUG 152 vm_offset_t opc_disasm(vm_offset_t, int); 153 154 /* 155 * Dump a `fpn' structure. 156 */ 157 void 158 fpu_dumpfpn(struct fpn *fp) 159 { 160 static const char *class[] = { 161 "SNAN", "QNAN", "ZERO", "NUM", "INF" 162 }; 163 164 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 165 fp->fp_sign ? '-' : ' ', 166 fp->fp_mant[0], fp->fp_mant[1], 167 fp->fp_mant[2], fp->fp_mant[3], 168 fp->fp_exp); 169 } 170 #endif 171 172 /* 173 * fpu_execute returns the following error numbers (0 = no error): 174 */ 175 #define FPE 1 /* take a floating point exception */ 176 #define NOTFPU 2 /* not an FPU instruction */ 177 #define FAULT 3 178 179 /* 180 * Emulate a floating-point instruction. 181 * Return zero for success, else signal number. 182 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 183 */ 184 int 185 fpu_emulate(struct trapframe *frame, struct fpu *fpf) 186 { 187 union instr insn; 188 struct fpemu fe; 189 int sig; 190 191 /* initialize insn.is_datasize to tell it is *not* initialized */ 192 fe.fe_fpstate = fpf; 193 fe.fe_cx = 0; 194 195 /* always set this (to avoid a warning) */ 196 197 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 198 #ifdef DEBUG 199 printf("fpu_emulate: fault reading opcode\n"); 200 #endif 201 return SIGSEGV; 202 } 203 204 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 205 insn.i_int, (void *)frame->srr0)); 206 207 if ((insn.i_any.i_opcd == OPC_TWI) || 208 ((insn.i_any.i_opcd == OPC_integer_31) && 209 (insn.i_x.i_xo == OPC31_TW))) { 210 /* Check for the two trap insns. */ 211 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 212 return (SIGTRAP); 213 } 214 sig = 0; 215 switch (fpu_execute(frame, &fe, &insn)) { 216 case 0: 217 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 218 frame->srr0 += 4; 219 break; 220 221 case FPE: 222 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 223 sig = SIGFPE; 224 break; 225 226 case FAULT: 227 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 228 sig = SIGSEGV; 229 break; 230 231 case NOTFPU: 232 default: 233 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 234 #ifdef DEBUG 235 if (fpe_debug & FPE_EX) { 236 printf("fpu_emulate: illegal insn %x at %p:", 237 insn.i_int, (void *) (frame->srr0)); 238 opc_disasm(frame->srr0, insn.i_int); 239 } 240 #endif 241 sig = SIGILL; 242 #ifdef DEBUG 243 if (fpe_debug & FPE_EX) 244 kdb_enter(KDB_WHY_UNSET, "illegal instruction"); 245 #endif 246 break; 247 } 248 249 return (sig); 250 } 251 252 /* 253 * Execute an FPU instruction (one that runs entirely in the FPU; not 254 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 255 * modified to reflect the setting the hardware would have left. 256 * 257 * Note that we do not catch all illegal opcodes, so you can, for instance, 258 * multiply two integers this way. 259 */ 260 int 261 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 262 { 263 struct fpn *fp; 264 union instr instr = *insn; 265 int *a; 266 vm_offset_t addr; 267 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 268 unsigned int cond; 269 struct fpu *fs; 270 271 /* Setup work. */ 272 fp = NULL; 273 fs = fe->fe_fpstate; 274 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 275 276 /* 277 * On PowerPC all floating point values are stored in registers 278 * as doubles, even when used for single precision operations. 279 */ 280 type = FTYPE_DBL; 281 cond = instr.i_any.i_rc; 282 setcr = 0; 283 bf = 0; /* XXX gcc */ 284 285 #if defined(DDB) && defined(DEBUG) 286 if (fpe_debug & FPE_EX) { 287 vm_offset_t loc = tf->srr0; 288 289 printf("Trying to emulate: %p ", (void *)loc); 290 opc_disasm(loc, instr.i_int); 291 } 292 #endif 293 294 /* 295 * `Decode' and execute instruction. 296 */ 297 298 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 299 instr.i_any.i_opcd == OPC_integer_31) { 300 /* 301 * Handle load/store insns: 302 * 303 * Convert to/from single if needed, calculate addr, 304 * and update index reg if needed. 305 */ 306 double buf; 307 size_t size = sizeof(float); 308 int store, update; 309 310 cond = 0; /* ld/st never set condition codes */ 311 312 if (instr.i_any.i_opcd == OPC_integer_31) { 313 if (instr.i_x.i_xo == OPC31_STFIWX) { 314 FPU_EMU_EVCNT_INCR(stfiwx); 315 316 /* Store as integer */ 317 ra = instr.i_x.i_ra; 318 rb = instr.i_x.i_rb; 319 DPRINTF(FPE_INSN, 320 ("reg %d has %jx reg %d has %jx\n", 321 ra, (uintmax_t)tf->fixreg[ra], rb, 322 (uintmax_t)tf->fixreg[rb])); 323 324 addr = tf->fixreg[rb]; 325 if (ra != 0) 326 addr += tf->fixreg[ra]; 327 rt = instr.i_x.i_rt; 328 a = (int *)&fs->fpr[rt].fpr; 329 DPRINTF(FPE_INSN, 330 ("fpu_execute: Store INT %x at %p\n", 331 a[1], (void *)addr)); 332 if (copyout(&a[1], (void *)addr, sizeof(int))) 333 return (FAULT); 334 return (0); 335 } 336 337 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 338 /* Not an indexed FP load/store op */ 339 return (NOTFPU); 340 341 store = (instr.i_x.i_xo & 0x80); 342 if (instr.i_x.i_xo & 0x40) 343 size = sizeof(double); 344 else 345 type = FTYPE_SNG; 346 update = (instr.i_x.i_xo & 0x20); 347 348 /* calculate EA of load/store */ 349 ra = instr.i_x.i_ra; 350 rb = instr.i_x.i_rb; 351 DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n", 352 ra, (uintmax_t)tf->fixreg[ra], rb, 353 (uintmax_t)tf->fixreg[rb])); 354 addr = tf->fixreg[rb]; 355 if (ra != 0) 356 addr += tf->fixreg[ra]; 357 rt = instr.i_x.i_rt; 358 } else { 359 store = instr.i_d.i_opcd & 0x4; 360 if (instr.i_d.i_opcd & 0x2) 361 size = sizeof(double); 362 else 363 type = FTYPE_SNG; 364 update = instr.i_d.i_opcd & 0x1; 365 366 /* calculate EA of load/store */ 367 ra = instr.i_d.i_ra; 368 addr = instr.i_d.i_d; 369 DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n", 370 ra, (uintmax_t)tf->fixreg[ra], 371 (uintmax_t)addr)); 372 if (ra != 0) 373 addr += tf->fixreg[ra]; 374 rt = instr.i_d.i_rt; 375 } 376 377 if (update && ra == 0) 378 return (NOTFPU); 379 380 if (store) { 381 /* Store */ 382 FPU_EMU_EVCNT_INCR(fpstore); 383 if (type != FTYPE_DBL) { 384 DPRINTF(FPE_INSN, 385 ("fpu_execute: Store SNG at %p\n", 386 (void *)addr)); 387 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 388 fpu_implode(fe, fp, type, (void *)&buf); 389 if (copyout(&buf, (void *)addr, size)) 390 return (FAULT); 391 } else { 392 DPRINTF(FPE_INSN, 393 ("fpu_execute: Store DBL at %p\n", 394 (void *)addr)); 395 if (copyout(&fs->fpr[rt].fpr, (void *)addr, 396 size)) 397 return (FAULT); 398 } 399 } else { 400 /* Load */ 401 FPU_EMU_EVCNT_INCR(fpload); 402 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 403 (void *)addr)); 404 if (copyin((const void *)addr, &fs->fpr[rt].fpr, 405 size)) 406 return (FAULT); 407 if (type != FTYPE_DBL) { 408 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 409 fpu_implode(fe, fp, FTYPE_DBL, 410 (u_int *)&fs->fpr[rt].fpr); 411 } 412 } 413 if (update) 414 tf->fixreg[ra] = addr; 415 /* Complete. */ 416 return (0); 417 #ifdef notyet 418 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 419 /* These are 64-bit extensions */ 420 return (NOTFPU); 421 #endif 422 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 423 instr.i_any.i_opcd == OPC_dp_fp_63) { 424 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 425 !(instr.i_a.i_xo & OPC63M_MASK)) { 426 /* Format X */ 427 rt = instr.i_x.i_rt; 428 ra = instr.i_x.i_ra; 429 rb = instr.i_x.i_rb; 430 431 /* One of the special opcodes.... */ 432 switch (instr.i_x.i_xo) { 433 case OPC63_FCMPU: 434 FPU_EMU_EVCNT_INCR(fcmpu); 435 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 436 rt >>= 2; 437 fpu_explode(fe, &fe->fe_f1, type, ra); 438 fpu_explode(fe, &fe->fe_f2, type, rb); 439 fpu_compare(fe, 0); 440 /* Make sure we do the condition regs. */ 441 cond = 0; 442 /* N.B.: i_rs is already left shifted by two. */ 443 bf = instr.i_x.i_rs & 0xfc; 444 setcr = 1; 445 break; 446 447 case OPC63_FRSP: 448 /* 449 * Convert to single: 450 * 451 * PowerPC uses this to round a double 452 * precision value to single precision, 453 * but values in registers are always 454 * stored in double precision format. 455 */ 456 FPU_EMU_EVCNT_INCR(frsp); 457 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 458 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 459 fpu_implode(fe, fp, FTYPE_SNG, 460 (u_int *)&fs->fpr[rt].fpr); 461 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 462 type = FTYPE_DBL; 463 break; 464 case OPC63_FCTIW: 465 case OPC63_FCTIWZ: 466 FPU_EMU_EVCNT_INCR(fctiw); 467 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 468 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 469 type = FTYPE_INT; 470 break; 471 case OPC63_FCMPO: 472 FPU_EMU_EVCNT_INCR(fcmpo); 473 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 474 rt >>= 2; 475 fpu_explode(fe, &fe->fe_f1, type, ra); 476 fpu_explode(fe, &fe->fe_f2, type, rb); 477 fpu_compare(fe, 1); 478 /* Make sure we do the condition regs. */ 479 cond = 0; 480 /* N.B.: i_rs is already left shifted by two. */ 481 bf = instr.i_x.i_rs & 0xfc; 482 setcr = 1; 483 break; 484 case OPC63_MTFSB1: 485 FPU_EMU_EVCNT_INCR(mtfsb1); 486 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 487 fe->fe_fpscr |= 488 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 489 break; 490 case OPC63_FNEG: 491 FPU_EMU_EVCNT_INCR(fnegabs); 492 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 493 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 494 sizeof(double)); 495 a = (int *)&fs->fpr[rt].fpr; 496 *a ^= (1U << 31); 497 break; 498 case OPC63_MCRFS: 499 FPU_EMU_EVCNT_INCR(mcrfs); 500 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 501 cond = 0; 502 rt &= 0x1c; 503 ra &= 0x1c; 504 /* Extract the bits we want */ 505 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 506 /* Clear the bits we copied. */ 507 fe->fe_cx = 508 (FPSR_EX_MSK | (0xf << (28 - ra))); 509 fe->fe_fpscr &= fe->fe_cx; 510 /* Now shove them in the right part of cr */ 511 tf->cr &= ~(0xf << (28 - rt)); 512 tf->cr |= (mask << (28 - rt)); 513 break; 514 case OPC63_MTFSB0: 515 FPU_EMU_EVCNT_INCR(mtfsb0); 516 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 517 fe->fe_fpscr &= 518 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 519 break; 520 case OPC63_FMR: 521 FPU_EMU_EVCNT_INCR(fmr); 522 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 523 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 524 sizeof(double)); 525 break; 526 case OPC63_MTFSFI: 527 FPU_EMU_EVCNT_INCR(mtfsfi); 528 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 529 rb >>= 1; 530 rt &= 0x1c; /* Already left-shifted 4 */ 531 fe->fe_cx = rb << (28 - rt); 532 mask = 0xf<<(28 - rt); 533 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 534 fe->fe_cx; 535 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 536 break; 537 case OPC63_FNABS: 538 FPU_EMU_EVCNT_INCR(fnabs); 539 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 540 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 541 sizeof(double)); 542 a = (int *)&fs->fpr[rt].fpr; 543 *a |= (1U << 31); 544 break; 545 case OPC63_FABS: 546 FPU_EMU_EVCNT_INCR(fabs); 547 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 548 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 549 sizeof(double)); 550 a = (int *)&fs->fpr[rt].fpr; 551 *a &= ~(1U << 31); 552 break; 553 case OPC63_MFFS: 554 FPU_EMU_EVCNT_INCR(mffs); 555 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 556 memcpy(&fs->fpr[rt].fpr, &fs->fpscr, 557 sizeof(fs->fpscr)); 558 break; 559 case OPC63_MTFSF: 560 FPU_EMU_EVCNT_INCR(mtfsf); 561 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 562 if ((rt = instr.i_xfl.i_flm) == -1) 563 mask = -1; 564 else { 565 mask = 0; 566 /* Convert 1 bit -> 4 bits */ 567 for (ra = 0; ra < 8; ra ++) 568 if (rt & (1<<ra)) 569 mask |= (0xf<<(4*ra)); 570 } 571 a = (int *)&fs->fpr[rt].fpr; 572 fe->fe_cx = mask & a[1]; 573 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 574 (fe->fe_cx); 575 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 576 break; 577 case OPC63_FCTID: 578 case OPC63_FCTIDZ: 579 FPU_EMU_EVCNT_INCR(fctid); 580 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 581 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 582 type = FTYPE_LNG; 583 break; 584 case OPC63_FCFID: 585 FPU_EMU_EVCNT_INCR(fcfid); 586 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 587 type = FTYPE_LNG; 588 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 589 type = FTYPE_DBL; 590 break; 591 default: 592 return (NOTFPU); 593 break; 594 } 595 } else { 596 /* Format A */ 597 rt = instr.i_a.i_frt; 598 ra = instr.i_a.i_fra; 599 rb = instr.i_a.i_frb; 600 rc = instr.i_a.i_frc; 601 602 /* 603 * All arithmetic operations work on registers, which 604 * are stored as doubles. 605 */ 606 type = FTYPE_DBL; 607 switch ((unsigned int)instr.i_a.i_xo) { 608 case OPC59_FDIVS: 609 FPU_EMU_EVCNT_INCR(fdiv); 610 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 611 fpu_explode(fe, &fe->fe_f1, type, ra); 612 fpu_explode(fe, &fe->fe_f2, type, rb); 613 fp = fpu_div(fe); 614 break; 615 case OPC59_FSUBS: 616 FPU_EMU_EVCNT_INCR(fsub); 617 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 618 fpu_explode(fe, &fe->fe_f1, type, ra); 619 fpu_explode(fe, &fe->fe_f2, type, rb); 620 fp = fpu_sub(fe); 621 break; 622 case OPC59_FADDS: 623 FPU_EMU_EVCNT_INCR(fadd); 624 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 625 fpu_explode(fe, &fe->fe_f1, type, ra); 626 fpu_explode(fe, &fe->fe_f2, type, rb); 627 fp = fpu_add(fe); 628 break; 629 case OPC59_FSQRTS: 630 FPU_EMU_EVCNT_INCR(fsqrt); 631 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 632 fpu_explode(fe, &fe->fe_f1, type, rb); 633 fp = fpu_sqrt(fe); 634 break; 635 case OPC63M_FSEL: 636 FPU_EMU_EVCNT_INCR(fsel); 637 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 638 a = (int *)&fe->fe_fpstate->fpr[ra].fpr; 639 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 640 /* fra < 0 */ 641 rc = rb; 642 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 643 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr, 644 sizeof(double)); 645 break; 646 case OPC59_FRES: 647 FPU_EMU_EVCNT_INCR(fpres); 648 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 649 fpu_explode(fe, &fe->fe_f1, type, rb); 650 fp = fpu_sqrt(fe); 651 /* now we've gotta overwrite the dest reg */ 652 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 653 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 654 fpu_div(fe); 655 break; 656 case OPC59_FMULS: 657 FPU_EMU_EVCNT_INCR(fmul); 658 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 659 fpu_explode(fe, &fe->fe_f1, type, ra); 660 fpu_explode(fe, &fe->fe_f2, type, rc); 661 fp = fpu_mul(fe); 662 break; 663 case OPC63M_FRSQRTE: 664 /* Reciprocal sqrt() estimate */ 665 FPU_EMU_EVCNT_INCR(frsqrte); 666 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 667 fpu_explode(fe, &fe->fe_f1, type, rb); 668 fp = fpu_sqrt(fe); 669 fe->fe_f2 = *fp; 670 /* now we've gotta overwrite the dest reg */ 671 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 672 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 673 fpu_div(fe); 674 break; 675 case OPC59_FMSUBS: 676 FPU_EMU_EVCNT_INCR(fmulsub); 677 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 678 fpu_explode(fe, &fe->fe_f1, type, ra); 679 fpu_explode(fe, &fe->fe_f2, type, rc); 680 fp = fpu_mul(fe); 681 fe->fe_f1 = *fp; 682 fpu_explode(fe, &fe->fe_f2, type, rb); 683 fp = fpu_sub(fe); 684 break; 685 case OPC59_FMADDS: 686 FPU_EMU_EVCNT_INCR(fmuladd); 687 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 688 fpu_explode(fe, &fe->fe_f1, type, ra); 689 fpu_explode(fe, &fe->fe_f2, type, rc); 690 fp = fpu_mul(fe); 691 fe->fe_f1 = *fp; 692 fpu_explode(fe, &fe->fe_f2, type, rb); 693 fp = fpu_add(fe); 694 break; 695 case OPC59_FNMSUBS: 696 FPU_EMU_EVCNT_INCR(fnmsub); 697 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 698 fpu_explode(fe, &fe->fe_f1, type, ra); 699 fpu_explode(fe, &fe->fe_f2, type, rc); 700 fp = fpu_mul(fe); 701 fe->fe_f1 = *fp; 702 fpu_explode(fe, &fe->fe_f2, type, rb); 703 fp = fpu_sub(fe); 704 /* Negate */ 705 fp->fp_sign ^= 1; 706 break; 707 case OPC59_FNMADDS: 708 FPU_EMU_EVCNT_INCR(fnmadd); 709 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 710 fpu_explode(fe, &fe->fe_f1, type, ra); 711 fpu_explode(fe, &fe->fe_f2, type, rc); 712 fp = fpu_mul(fe); 713 fe->fe_f1 = *fp; 714 fpu_explode(fe, &fe->fe_f2, type, rb); 715 fp = fpu_add(fe); 716 /* Negate */ 717 fp->fp_sign ^= 1; 718 break; 719 default: 720 return (NOTFPU); 721 break; 722 } 723 724 /* If the instruction was single precision, round */ 725 if (!(instr.i_any.i_opcd & 0x4)) { 726 fpu_implode(fe, fp, FTYPE_SNG, 727 (u_int *)&fs->fpr[rt].fpr); 728 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 729 } 730 } 731 } else { 732 return (NOTFPU); 733 } 734 735 /* 736 * ALU operation is complete. Collapse the result and then check 737 * for exceptions. If we got any, and they are enabled, do not 738 * alter the destination register, just stop with an exception. 739 * Otherwise set new current exceptions and accrue. 740 */ 741 if (fp) 742 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr); 743 cx = fe->fe_cx; 744 fsr = fe->fe_fpscr; 745 if (cx != 0) { 746 fsr &= ~FPSCR_FX; 747 if ((cx^fsr)&FPSR_EX_MSK) 748 fsr |= FPSCR_FX; 749 mask = fsr & FPSR_EX; 750 mask <<= (25-3); 751 if (cx & mask) 752 fsr |= FPSCR_FEX; 753 if (cx & FPSCR_FPRF) { 754 /* Need to replace CC */ 755 fsr &= ~FPSCR_FPRF; 756 } 757 if (cx & (FPSR_EXOP)) 758 fsr |= FPSCR_VX; 759 fsr |= cx; 760 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 761 } 762 763 if (cond) { 764 cond = fsr & 0xf0000000; 765 /* Isolate condition codes */ 766 cond >>= 28; 767 /* Move fpu condition codes to cr[1] */ 768 tf->cr &= (0x0f000000); 769 tf->cr |= (cond<<24); 770 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 771 } 772 773 if (setcr) { 774 cond = fsr & FPSCR_FPCC; 775 /* Isolate condition codes */ 776 cond <<= 16; 777 /* Move fpu condition codes to cr[1] */ 778 tf->cr &= ~(0xf0000000>>bf); 779 tf->cr |= (cond>>bf); 780 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n", 781 bf/4, (uintmax_t)tf->cr, cond)); 782 } 783 784 ((int *)&fs->fpscr)[1] = fsr; 785 if (fsr & FPSCR_FEX) 786 return(FPE); 787 return (0); /* success */ 788 } 789