1 /* $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright 2001 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1992, 1993 42 * The Regents of the University of California. All rights reserved. 43 * 44 * This software was developed by the Computer Systems Engineering group 45 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 46 * contributed to Berkeley. 47 * 48 * All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the University of 51 * California, Lawrence Berkeley Laboratory. 52 * 53 * Redistribution and use in source and binary forms, with or without 54 * modification, are permitted provided that the following conditions 55 * are met: 56 * 1. Redistributions of source code must retain the above copyright 57 * notice, this list of conditions and the following disclaimer. 58 * 2. Redistributions in binary form must reproduce the above copyright 59 * notice, this list of conditions and the following disclaimer in the 60 * documentation and/or other materials provided with the distribution. 61 * 3. Neither the name of the University nor the names of its contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 75 * SUCH DAMAGE. 76 * 77 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 78 */ 79 80 #include <sys/cdefs.h> 81 __FBSDID("$FreeBSD$"); 82 83 #include "opt_ddb.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kdb.h> 88 #include <sys/kernel.h> 89 #include <sys/proc.h> 90 #include <sys/sysctl.h> 91 #include <sys/signal.h> 92 #include <sys/syslog.h> 93 #include <sys/signalvar.h> 94 95 #include <machine/fpu.h> 96 #include <machine/reg.h> 97 98 #include <powerpc/fpu/fpu_emu.h> 99 #include <powerpc/fpu/fpu_extern.h> 100 #include <powerpc/fpu/fpu_instr.h> 101 102 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW, 0, "FPU emulator"); 103 104 #define FPU_EMU_EVCNT_DECL(name) \ 105 static u_int fpu_emu_evcnt_##name; \ 106 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD, \ 107 &fpu_emu_evcnt_##name, 0, "") 108 109 #define FPU_EMU_EVCNT_INCR(name) fpu_emu_evcnt_##name++ 110 111 FPU_EMU_EVCNT_DECL(stfiwx); 112 FPU_EMU_EVCNT_DECL(fpstore); 113 FPU_EMU_EVCNT_DECL(fpload); 114 FPU_EMU_EVCNT_DECL(fcmpu); 115 FPU_EMU_EVCNT_DECL(frsp); 116 FPU_EMU_EVCNT_DECL(fctiw); 117 FPU_EMU_EVCNT_DECL(fcmpo); 118 FPU_EMU_EVCNT_DECL(mtfsb1); 119 FPU_EMU_EVCNT_DECL(fnegabs); 120 FPU_EMU_EVCNT_DECL(mcrfs); 121 FPU_EMU_EVCNT_DECL(mtfsb0); 122 FPU_EMU_EVCNT_DECL(fmr); 123 FPU_EMU_EVCNT_DECL(mtfsfi); 124 FPU_EMU_EVCNT_DECL(fnabs); 125 FPU_EMU_EVCNT_DECL(fabs); 126 FPU_EMU_EVCNT_DECL(mffs); 127 FPU_EMU_EVCNT_DECL(mtfsf); 128 FPU_EMU_EVCNT_DECL(fctid); 129 FPU_EMU_EVCNT_DECL(fcfid); 130 FPU_EMU_EVCNT_DECL(fdiv); 131 FPU_EMU_EVCNT_DECL(fsub); 132 FPU_EMU_EVCNT_DECL(fadd); 133 FPU_EMU_EVCNT_DECL(fsqrt); 134 FPU_EMU_EVCNT_DECL(fsel); 135 FPU_EMU_EVCNT_DECL(fpres); 136 FPU_EMU_EVCNT_DECL(fmul); 137 FPU_EMU_EVCNT_DECL(frsqrte); 138 FPU_EMU_EVCNT_DECL(fmulsub); 139 FPU_EMU_EVCNT_DECL(fmuladd); 140 FPU_EMU_EVCNT_DECL(fnmsub); 141 FPU_EMU_EVCNT_DECL(fnmadd); 142 143 /* FPSR exception masks */ 144 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 145 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 146 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 147 FPSCR_VXSQRT|FPSCR_VXCVI) 148 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 149 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 150 151 int fpe_debug = 0; 152 153 #ifdef DEBUG 154 vm_offset_t opc_disasm(vm_offset_t, int); 155 156 /* 157 * Dump a `fpn' structure. 158 */ 159 void 160 fpu_dumpfpn(struct fpn *fp) 161 { 162 static const char *class[] = { 163 "SNAN", "QNAN", "ZERO", "NUM", "INF" 164 }; 165 166 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 167 fp->fp_sign ? '-' : ' ', 168 fp->fp_mant[0], fp->fp_mant[1], 169 fp->fp_mant[2], fp->fp_mant[3], 170 fp->fp_exp); 171 } 172 #endif 173 174 /* 175 * fpu_execute returns the following error numbers (0 = no error): 176 */ 177 #define FPE 1 /* take a floating point exception */ 178 #define NOTFPU 2 /* not an FPU instruction */ 179 #define FAULT 3 180 181 182 /* 183 * Emulate a floating-point instruction. 184 * Return zero for success, else signal number. 185 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 186 */ 187 int 188 fpu_emulate(struct trapframe *frame, struct fpu *fpf) 189 { 190 union instr insn; 191 struct fpemu fe; 192 static int lastill = 0; 193 int sig; 194 195 /* initialize insn.is_datasize to tell it is *not* initialized */ 196 fe.fe_fpstate = fpf; 197 fe.fe_cx = 0; 198 199 /* always set this (to avoid a warning) */ 200 201 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 202 #ifdef DEBUG 203 printf("fpu_emulate: fault reading opcode\n"); 204 #endif 205 return SIGSEGV; 206 } 207 208 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 209 insn.i_int, (void *)frame->srr0)); 210 211 212 if ((insn.i_any.i_opcd == OPC_TWI) || 213 ((insn.i_any.i_opcd == OPC_integer_31) && 214 (insn.i_x.i_xo == OPC31_TW))) { 215 /* Check for the two trap insns. */ 216 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 217 return (SIGTRAP); 218 } 219 sig = 0; 220 switch (fpu_execute(frame, &fe, &insn)) { 221 case 0: 222 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 223 frame->srr0 += 4; 224 break; 225 226 case FPE: 227 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 228 sig = SIGFPE; 229 break; 230 231 case FAULT: 232 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 233 sig = SIGSEGV; 234 break; 235 236 case NOTFPU: 237 default: 238 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 239 #ifdef DEBUG 240 if (fpe_debug & FPE_EX) { 241 printf("fpu_emulate: illegal insn %x at %p:", 242 insn.i_int, (void *) (frame->srr0)); 243 opc_disasm(frame->srr0, insn.i_int); 244 } 245 #endif 246 /* 247 * XXXX retry an illegal insn once due to cache issues. 248 */ 249 if (lastill == frame->srr0) { 250 sig = SIGILL; 251 #ifdef DEBUG 252 if (fpe_debug & FPE_EX) 253 kdb_enter(KDB_WHY_UNSET, "illegal instruction"); 254 #endif 255 } 256 lastill = frame->srr0; 257 break; 258 } 259 260 return (sig); 261 } 262 263 /* 264 * Execute an FPU instruction (one that runs entirely in the FPU; not 265 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 266 * modified to reflect the setting the hardware would have left. 267 * 268 * Note that we do not catch all illegal opcodes, so you can, for instance, 269 * multiply two integers this way. 270 */ 271 int 272 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 273 { 274 struct fpn *fp; 275 union instr instr = *insn; 276 int *a; 277 vm_offset_t addr; 278 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 279 unsigned int cond; 280 struct fpu *fs; 281 282 /* Setup work. */ 283 fp = NULL; 284 fs = fe->fe_fpstate; 285 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 286 287 /* 288 * On PowerPC all floating point values are stored in registers 289 * as doubles, even when used for single precision operations. 290 */ 291 type = FTYPE_DBL; 292 cond = instr.i_any.i_rc; 293 setcr = 0; 294 bf = 0; /* XXX gcc */ 295 296 #if defined(DDB) && defined(DEBUG) 297 if (fpe_debug & FPE_EX) { 298 vm_offset_t loc = tf->srr0; 299 300 printf("Trying to emulate: %p ", (void *)loc); 301 opc_disasm(loc, instr.i_int); 302 } 303 #endif 304 305 /* 306 * `Decode' and execute instruction. 307 */ 308 309 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 310 instr.i_any.i_opcd == OPC_integer_31) { 311 /* 312 * Handle load/store insns: 313 * 314 * Convert to/from single if needed, calculate addr, 315 * and update index reg if needed. 316 */ 317 double buf; 318 size_t size = sizeof(float); 319 int store, update; 320 321 cond = 0; /* ld/st never set condition codes */ 322 323 324 if (instr.i_any.i_opcd == OPC_integer_31) { 325 if (instr.i_x.i_xo == OPC31_STFIWX) { 326 FPU_EMU_EVCNT_INCR(stfiwx); 327 328 /* Store as integer */ 329 ra = instr.i_x.i_ra; 330 rb = instr.i_x.i_rb; 331 DPRINTF(FPE_INSN, 332 ("reg %d has %jx reg %d has %jx\n", 333 ra, (uintmax_t)tf->fixreg[ra], rb, 334 (uintmax_t)tf->fixreg[rb])); 335 336 addr = tf->fixreg[rb]; 337 if (ra != 0) 338 addr += tf->fixreg[ra]; 339 rt = instr.i_x.i_rt; 340 a = (int *)&fs->fpr[rt].fpr; 341 DPRINTF(FPE_INSN, 342 ("fpu_execute: Store INT %x at %p\n", 343 a[1], (void *)addr)); 344 if (copyout(&a[1], (void *)addr, sizeof(int))) 345 return (FAULT); 346 return (0); 347 } 348 349 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 350 /* Not an indexed FP load/store op */ 351 return (NOTFPU); 352 353 store = (instr.i_x.i_xo & 0x80); 354 if (instr.i_x.i_xo & 0x40) 355 size = sizeof(double); 356 else 357 type = FTYPE_SNG; 358 update = (instr.i_x.i_xo & 0x20); 359 360 /* calculate EA of load/store */ 361 ra = instr.i_x.i_ra; 362 rb = instr.i_x.i_rb; 363 DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n", 364 ra, (uintmax_t)tf->fixreg[ra], rb, 365 (uintmax_t)tf->fixreg[rb])); 366 addr = tf->fixreg[rb]; 367 if (ra != 0) 368 addr += tf->fixreg[ra]; 369 rt = instr.i_x.i_rt; 370 } else { 371 store = instr.i_d.i_opcd & 0x4; 372 if (instr.i_d.i_opcd & 0x2) 373 size = sizeof(double); 374 else 375 type = FTYPE_SNG; 376 update = instr.i_d.i_opcd & 0x1; 377 378 /* calculate EA of load/store */ 379 ra = instr.i_d.i_ra; 380 addr = instr.i_d.i_d; 381 DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n", 382 ra, (uintmax_t)tf->fixreg[ra], 383 (uintmax_t)addr)); 384 if (ra != 0) 385 addr += tf->fixreg[ra]; 386 rt = instr.i_d.i_rt; 387 } 388 389 if (update && ra == 0) 390 return (NOTFPU); 391 392 if (store) { 393 /* Store */ 394 FPU_EMU_EVCNT_INCR(fpstore); 395 if (type != FTYPE_DBL) { 396 DPRINTF(FPE_INSN, 397 ("fpu_execute: Store SNG at %p\n", 398 (void *)addr)); 399 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 400 fpu_implode(fe, fp, type, (void *)&buf); 401 if (copyout(&buf, (void *)addr, size)) 402 return (FAULT); 403 } else { 404 DPRINTF(FPE_INSN, 405 ("fpu_execute: Store DBL at %p\n", 406 (void *)addr)); 407 if (copyout(&fs->fpr[rt].fpr, (void *)addr, 408 size)) 409 return (FAULT); 410 } 411 } else { 412 /* Load */ 413 FPU_EMU_EVCNT_INCR(fpload); 414 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 415 (void *)addr)); 416 if (copyin((const void *)addr, &fs->fpr[rt].fpr, 417 size)) 418 return (FAULT); 419 if (type != FTYPE_DBL) { 420 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 421 fpu_implode(fe, fp, FTYPE_DBL, 422 (u_int *)&fs->fpr[rt].fpr); 423 } 424 } 425 if (update) 426 tf->fixreg[ra] = addr; 427 /* Complete. */ 428 return (0); 429 #ifdef notyet 430 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 431 /* These are 64-bit extensions */ 432 return (NOTFPU); 433 #endif 434 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 435 instr.i_any.i_opcd == OPC_dp_fp_63) { 436 437 438 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 439 !(instr.i_a.i_xo & OPC63M_MASK)) { 440 /* Format X */ 441 rt = instr.i_x.i_rt; 442 ra = instr.i_x.i_ra; 443 rb = instr.i_x.i_rb; 444 445 446 /* One of the special opcodes.... */ 447 switch (instr.i_x.i_xo) { 448 case OPC63_FCMPU: 449 FPU_EMU_EVCNT_INCR(fcmpu); 450 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 451 rt >>= 2; 452 fpu_explode(fe, &fe->fe_f1, type, ra); 453 fpu_explode(fe, &fe->fe_f2, type, rb); 454 fpu_compare(fe, 0); 455 /* Make sure we do the condition regs. */ 456 cond = 0; 457 /* N.B.: i_rs is already left shifted by two. */ 458 bf = instr.i_x.i_rs & 0xfc; 459 setcr = 1; 460 break; 461 462 case OPC63_FRSP: 463 /* 464 * Convert to single: 465 * 466 * PowerPC uses this to round a double 467 * precision value to single precision, 468 * but values in registers are always 469 * stored in double precision format. 470 */ 471 FPU_EMU_EVCNT_INCR(frsp); 472 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 473 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 474 fpu_implode(fe, fp, FTYPE_SNG, 475 (u_int *)&fs->fpr[rt].fpr); 476 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 477 type = FTYPE_DBL; 478 break; 479 case OPC63_FCTIW: 480 case OPC63_FCTIWZ: 481 FPU_EMU_EVCNT_INCR(fctiw); 482 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 483 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 484 type = FTYPE_INT; 485 break; 486 case OPC63_FCMPO: 487 FPU_EMU_EVCNT_INCR(fcmpo); 488 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 489 rt >>= 2; 490 fpu_explode(fe, &fe->fe_f1, type, ra); 491 fpu_explode(fe, &fe->fe_f2, type, rb); 492 fpu_compare(fe, 1); 493 /* Make sure we do the condition regs. */ 494 cond = 0; 495 /* N.B.: i_rs is already left shifted by two. */ 496 bf = instr.i_x.i_rs & 0xfc; 497 setcr = 1; 498 break; 499 case OPC63_MTFSB1: 500 FPU_EMU_EVCNT_INCR(mtfsb1); 501 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 502 fe->fe_fpscr |= 503 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 504 break; 505 case OPC63_FNEG: 506 FPU_EMU_EVCNT_INCR(fnegabs); 507 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 508 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 509 sizeof(double)); 510 a = (int *)&fs->fpr[rt].fpr; 511 *a ^= (1U << 31); 512 break; 513 case OPC63_MCRFS: 514 FPU_EMU_EVCNT_INCR(mcrfs); 515 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 516 cond = 0; 517 rt &= 0x1c; 518 ra &= 0x1c; 519 /* Extract the bits we want */ 520 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 521 /* Clear the bits we copied. */ 522 fe->fe_cx = 523 (FPSR_EX_MSK | (0xf << (28 - ra))); 524 fe->fe_fpscr &= fe->fe_cx; 525 /* Now shove them in the right part of cr */ 526 tf->cr &= ~(0xf << (28 - rt)); 527 tf->cr |= (mask << (28 - rt)); 528 break; 529 case OPC63_MTFSB0: 530 FPU_EMU_EVCNT_INCR(mtfsb0); 531 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 532 fe->fe_fpscr &= 533 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 534 break; 535 case OPC63_FMR: 536 FPU_EMU_EVCNT_INCR(fmr); 537 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 538 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 539 sizeof(double)); 540 break; 541 case OPC63_MTFSFI: 542 FPU_EMU_EVCNT_INCR(mtfsfi); 543 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 544 rb >>= 1; 545 rt &= 0x1c; /* Already left-shifted 4 */ 546 fe->fe_cx = rb << (28 - rt); 547 mask = 0xf<<(28 - rt); 548 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 549 fe->fe_cx; 550 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 551 break; 552 case OPC63_FNABS: 553 FPU_EMU_EVCNT_INCR(fnabs); 554 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 555 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 556 sizeof(double)); 557 a = (int *)&fs->fpr[rt].fpr; 558 *a |= (1U << 31); 559 break; 560 case OPC63_FABS: 561 FPU_EMU_EVCNT_INCR(fabs); 562 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 563 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 564 sizeof(double)); 565 a = (int *)&fs->fpr[rt].fpr; 566 *a &= ~(1U << 31); 567 break; 568 case OPC63_MFFS: 569 FPU_EMU_EVCNT_INCR(mffs); 570 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 571 memcpy(&fs->fpr[rt].fpr, &fs->fpscr, 572 sizeof(fs->fpscr)); 573 break; 574 case OPC63_MTFSF: 575 FPU_EMU_EVCNT_INCR(mtfsf); 576 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 577 if ((rt = instr.i_xfl.i_flm) == -1) 578 mask = -1; 579 else { 580 mask = 0; 581 /* Convert 1 bit -> 4 bits */ 582 for (ra = 0; ra < 8; ra ++) 583 if (rt & (1<<ra)) 584 mask |= (0xf<<(4*ra)); 585 } 586 a = (int *)&fs->fpr[rt].fpr; 587 fe->fe_cx = mask & a[1]; 588 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 589 (fe->fe_cx); 590 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 591 break; 592 case OPC63_FCTID: 593 case OPC63_FCTIDZ: 594 FPU_EMU_EVCNT_INCR(fctid); 595 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 596 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 597 type = FTYPE_LNG; 598 break; 599 case OPC63_FCFID: 600 FPU_EMU_EVCNT_INCR(fcfid); 601 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 602 type = FTYPE_LNG; 603 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 604 type = FTYPE_DBL; 605 break; 606 default: 607 return (NOTFPU); 608 break; 609 } 610 } else { 611 /* Format A */ 612 rt = instr.i_a.i_frt; 613 ra = instr.i_a.i_fra; 614 rb = instr.i_a.i_frb; 615 rc = instr.i_a.i_frc; 616 617 /* 618 * All arithmetic operations work on registers, which 619 * are stored as doubles. 620 */ 621 type = FTYPE_DBL; 622 switch ((unsigned int)instr.i_a.i_xo) { 623 case OPC59_FDIVS: 624 FPU_EMU_EVCNT_INCR(fdiv); 625 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 626 fpu_explode(fe, &fe->fe_f1, type, ra); 627 fpu_explode(fe, &fe->fe_f2, type, rb); 628 fp = fpu_div(fe); 629 break; 630 case OPC59_FSUBS: 631 FPU_EMU_EVCNT_INCR(fsub); 632 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 633 fpu_explode(fe, &fe->fe_f1, type, ra); 634 fpu_explode(fe, &fe->fe_f2, type, rb); 635 fp = fpu_sub(fe); 636 break; 637 case OPC59_FADDS: 638 FPU_EMU_EVCNT_INCR(fadd); 639 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 640 fpu_explode(fe, &fe->fe_f1, type, ra); 641 fpu_explode(fe, &fe->fe_f2, type, rb); 642 fp = fpu_add(fe); 643 break; 644 case OPC59_FSQRTS: 645 FPU_EMU_EVCNT_INCR(fsqrt); 646 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 647 fpu_explode(fe, &fe->fe_f1, type, rb); 648 fp = fpu_sqrt(fe); 649 break; 650 case OPC63M_FSEL: 651 FPU_EMU_EVCNT_INCR(fsel); 652 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 653 a = (int *)&fe->fe_fpstate->fpr[ra].fpr; 654 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 655 /* fra < 0 */ 656 rc = rb; 657 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 658 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr, 659 sizeof(double)); 660 break; 661 case OPC59_FRES: 662 FPU_EMU_EVCNT_INCR(fpres); 663 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 664 fpu_explode(fe, &fe->fe_f1, type, rb); 665 fp = fpu_sqrt(fe); 666 /* now we've gotta overwrite the dest reg */ 667 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 668 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 669 fpu_div(fe); 670 break; 671 case OPC59_FMULS: 672 FPU_EMU_EVCNT_INCR(fmul); 673 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 674 fpu_explode(fe, &fe->fe_f1, type, ra); 675 fpu_explode(fe, &fe->fe_f2, type, rc); 676 fp = fpu_mul(fe); 677 break; 678 case OPC63M_FRSQRTE: 679 /* Reciprocal sqrt() estimate */ 680 FPU_EMU_EVCNT_INCR(frsqrte); 681 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 682 fpu_explode(fe, &fe->fe_f1, type, rb); 683 fp = fpu_sqrt(fe); 684 fe->fe_f2 = *fp; 685 /* now we've gotta overwrite the dest reg */ 686 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 687 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 688 fpu_div(fe); 689 break; 690 case OPC59_FMSUBS: 691 FPU_EMU_EVCNT_INCR(fmulsub); 692 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 693 fpu_explode(fe, &fe->fe_f1, type, ra); 694 fpu_explode(fe, &fe->fe_f2, type, rc); 695 fp = fpu_mul(fe); 696 fe->fe_f1 = *fp; 697 fpu_explode(fe, &fe->fe_f2, type, rb); 698 fp = fpu_sub(fe); 699 break; 700 case OPC59_FMADDS: 701 FPU_EMU_EVCNT_INCR(fmuladd); 702 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 703 fpu_explode(fe, &fe->fe_f1, type, ra); 704 fpu_explode(fe, &fe->fe_f2, type, rc); 705 fp = fpu_mul(fe); 706 fe->fe_f1 = *fp; 707 fpu_explode(fe, &fe->fe_f2, type, rb); 708 fp = fpu_add(fe); 709 break; 710 case OPC59_FNMSUBS: 711 FPU_EMU_EVCNT_INCR(fnmsub); 712 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 713 fpu_explode(fe, &fe->fe_f1, type, ra); 714 fpu_explode(fe, &fe->fe_f2, type, rc); 715 fp = fpu_mul(fe); 716 fe->fe_f1 = *fp; 717 fpu_explode(fe, &fe->fe_f2, type, rb); 718 fp = fpu_sub(fe); 719 /* Negate */ 720 fp->fp_sign ^= 1; 721 break; 722 case OPC59_FNMADDS: 723 FPU_EMU_EVCNT_INCR(fnmadd); 724 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 725 fpu_explode(fe, &fe->fe_f1, type, ra); 726 fpu_explode(fe, &fe->fe_f2, type, rc); 727 fp = fpu_mul(fe); 728 fe->fe_f1 = *fp; 729 fpu_explode(fe, &fe->fe_f2, type, rb); 730 fp = fpu_add(fe); 731 /* Negate */ 732 fp->fp_sign ^= 1; 733 break; 734 default: 735 return (NOTFPU); 736 break; 737 } 738 739 /* If the instruction was single precision, round */ 740 if (!(instr.i_any.i_opcd & 0x4)) { 741 fpu_implode(fe, fp, FTYPE_SNG, 742 (u_int *)&fs->fpr[rt].fpr); 743 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 744 } 745 } 746 } else { 747 return (NOTFPU); 748 } 749 750 /* 751 * ALU operation is complete. Collapse the result and then check 752 * for exceptions. If we got any, and they are enabled, do not 753 * alter the destination register, just stop with an exception. 754 * Otherwise set new current exceptions and accrue. 755 */ 756 if (fp) 757 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr); 758 cx = fe->fe_cx; 759 fsr = fe->fe_fpscr; 760 if (cx != 0) { 761 fsr &= ~FPSCR_FX; 762 if ((cx^fsr)&FPSR_EX_MSK) 763 fsr |= FPSCR_FX; 764 mask = fsr & FPSR_EX; 765 mask <<= (25-3); 766 if (cx & mask) 767 fsr |= FPSCR_FEX; 768 if (cx & FPSCR_FPRF) { 769 /* Need to replace CC */ 770 fsr &= ~FPSCR_FPRF; 771 } 772 if (cx & (FPSR_EXOP)) 773 fsr |= FPSCR_VX; 774 fsr |= cx; 775 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 776 } 777 778 if (cond) { 779 cond = fsr & 0xf0000000; 780 /* Isolate condition codes */ 781 cond >>= 28; 782 /* Move fpu condition codes to cr[1] */ 783 tf->cr &= (0x0f000000); 784 tf->cr |= (cond<<24); 785 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 786 } 787 788 if (setcr) { 789 cond = fsr & FPSCR_FPCC; 790 /* Isolate condition codes */ 791 cond <<= 16; 792 /* Move fpu condition codes to cr[1] */ 793 tf->cr &= ~(0xf0000000>>bf); 794 tf->cr |= (cond>>bf); 795 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n", 796 bf/4, (uintmax_t)tf->cr, cond)); 797 } 798 799 ((int *)&fs->fpscr)[1] = fsr; 800 if (fsr & FPSCR_FEX) 801 return(FPE); 802 return (0); /* success */ 803 } 804