1 /* $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright 2001 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1992, 1993 42 * The Regents of the University of California. All rights reserved. 43 * 44 * This software was developed by the Computer Systems Engineering group 45 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 46 * contributed to Berkeley. 47 * 48 * All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the University of 51 * California, Lawrence Berkeley Laboratory. 52 * 53 * Redistribution and use in source and binary forms, with or without 54 * modification, are permitted provided that the following conditions 55 * are met: 56 * 1. Redistributions of source code must retain the above copyright 57 * notice, this list of conditions and the following disclaimer. 58 * 2. Redistributions in binary form must reproduce the above copyright 59 * notice, this list of conditions and the following disclaimer in the 60 * documentation and/or other materials provided with the distribution. 61 * 3. Neither the name of the University nor the names of its contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 75 * SUCH DAMAGE. 76 * 77 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 78 */ 79 80 #include <sys/cdefs.h> 81 __FBSDID("$FreeBSD$"); 82 83 #include "opt_ddb.h" 84 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/kdb.h> 88 #include <sys/kernel.h> 89 #include <sys/proc.h> 90 #include <sys/sysctl.h> 91 #include <sys/signal.h> 92 #include <sys/syslog.h> 93 #include <sys/signalvar.h> 94 95 #include <machine/fpu.h> 96 #include <machine/reg.h> 97 98 #include <powerpc/fpu/fpu_emu.h> 99 #include <powerpc/fpu/fpu_extern.h> 100 #include <powerpc/fpu/fpu_instr.h> 101 102 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 103 "FPU emulator"); 104 105 #define FPU_EMU_EVCNT_DECL(name) \ 106 static u_int fpu_emu_evcnt_##name; \ 107 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD, \ 108 &fpu_emu_evcnt_##name, 0, "") 109 110 #define FPU_EMU_EVCNT_INCR(name) fpu_emu_evcnt_##name++ 111 112 FPU_EMU_EVCNT_DECL(stfiwx); 113 FPU_EMU_EVCNT_DECL(fpstore); 114 FPU_EMU_EVCNT_DECL(fpload); 115 FPU_EMU_EVCNT_DECL(fcmpu); 116 FPU_EMU_EVCNT_DECL(frsp); 117 FPU_EMU_EVCNT_DECL(fctiw); 118 FPU_EMU_EVCNT_DECL(fcmpo); 119 FPU_EMU_EVCNT_DECL(mtfsb1); 120 FPU_EMU_EVCNT_DECL(fnegabs); 121 FPU_EMU_EVCNT_DECL(mcrfs); 122 FPU_EMU_EVCNT_DECL(mtfsb0); 123 FPU_EMU_EVCNT_DECL(fmr); 124 FPU_EMU_EVCNT_DECL(mtfsfi); 125 FPU_EMU_EVCNT_DECL(fnabs); 126 FPU_EMU_EVCNT_DECL(fabs); 127 FPU_EMU_EVCNT_DECL(mffs); 128 FPU_EMU_EVCNT_DECL(mtfsf); 129 FPU_EMU_EVCNT_DECL(fctid); 130 FPU_EMU_EVCNT_DECL(fcfid); 131 FPU_EMU_EVCNT_DECL(fdiv); 132 FPU_EMU_EVCNT_DECL(fsub); 133 FPU_EMU_EVCNT_DECL(fadd); 134 FPU_EMU_EVCNT_DECL(fsqrt); 135 FPU_EMU_EVCNT_DECL(fsel); 136 FPU_EMU_EVCNT_DECL(fpres); 137 FPU_EMU_EVCNT_DECL(fmul); 138 FPU_EMU_EVCNT_DECL(frsqrte); 139 FPU_EMU_EVCNT_DECL(fmulsub); 140 FPU_EMU_EVCNT_DECL(fmuladd); 141 FPU_EMU_EVCNT_DECL(fnmsub); 142 FPU_EMU_EVCNT_DECL(fnmadd); 143 144 /* FPSR exception masks */ 145 #define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 146 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 147 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 148 FPSCR_VXSQRT|FPSCR_VXCVI) 149 #define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 150 #define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 151 152 int fpe_debug = 0; 153 154 #ifdef DEBUG 155 vm_offset_t opc_disasm(vm_offset_t, int); 156 157 /* 158 * Dump a `fpn' structure. 159 */ 160 void 161 fpu_dumpfpn(struct fpn *fp) 162 { 163 static const char *class[] = { 164 "SNAN", "QNAN", "ZERO", "NUM", "INF" 165 }; 166 167 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 168 fp->fp_sign ? '-' : ' ', 169 fp->fp_mant[0], fp->fp_mant[1], 170 fp->fp_mant[2], fp->fp_mant[3], 171 fp->fp_exp); 172 } 173 #endif 174 175 /* 176 * fpu_execute returns the following error numbers (0 = no error): 177 */ 178 #define FPE 1 /* take a floating point exception */ 179 #define NOTFPU 2 /* not an FPU instruction */ 180 #define FAULT 3 181 182 183 /* 184 * Emulate a floating-point instruction. 185 * Return zero for success, else signal number. 186 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 187 */ 188 int 189 fpu_emulate(struct trapframe *frame, struct fpu *fpf) 190 { 191 union instr insn; 192 struct fpemu fe; 193 int sig; 194 195 /* initialize insn.is_datasize to tell it is *not* initialized */ 196 fe.fe_fpstate = fpf; 197 fe.fe_cx = 0; 198 199 /* always set this (to avoid a warning) */ 200 201 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 202 #ifdef DEBUG 203 printf("fpu_emulate: fault reading opcode\n"); 204 #endif 205 return SIGSEGV; 206 } 207 208 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 209 insn.i_int, (void *)frame->srr0)); 210 211 212 if ((insn.i_any.i_opcd == OPC_TWI) || 213 ((insn.i_any.i_opcd == OPC_integer_31) && 214 (insn.i_x.i_xo == OPC31_TW))) { 215 /* Check for the two trap insns. */ 216 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 217 return (SIGTRAP); 218 } 219 sig = 0; 220 switch (fpu_execute(frame, &fe, &insn)) { 221 case 0: 222 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 223 frame->srr0 += 4; 224 break; 225 226 case FPE: 227 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 228 sig = SIGFPE; 229 break; 230 231 case FAULT: 232 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 233 sig = SIGSEGV; 234 break; 235 236 case NOTFPU: 237 default: 238 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 239 #ifdef DEBUG 240 if (fpe_debug & FPE_EX) { 241 printf("fpu_emulate: illegal insn %x at %p:", 242 insn.i_int, (void *) (frame->srr0)); 243 opc_disasm(frame->srr0, insn.i_int); 244 } 245 #endif 246 sig = SIGILL; 247 #ifdef DEBUG 248 if (fpe_debug & FPE_EX) 249 kdb_enter(KDB_WHY_UNSET, "illegal instruction"); 250 #endif 251 break; 252 } 253 254 return (sig); 255 } 256 257 /* 258 * Execute an FPU instruction (one that runs entirely in the FPU; not 259 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 260 * modified to reflect the setting the hardware would have left. 261 * 262 * Note that we do not catch all illegal opcodes, so you can, for instance, 263 * multiply two integers this way. 264 */ 265 int 266 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 267 { 268 struct fpn *fp; 269 union instr instr = *insn; 270 int *a; 271 vm_offset_t addr; 272 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 273 unsigned int cond; 274 struct fpu *fs; 275 276 /* Setup work. */ 277 fp = NULL; 278 fs = fe->fe_fpstate; 279 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 280 281 /* 282 * On PowerPC all floating point values are stored in registers 283 * as doubles, even when used for single precision operations. 284 */ 285 type = FTYPE_DBL; 286 cond = instr.i_any.i_rc; 287 setcr = 0; 288 bf = 0; /* XXX gcc */ 289 290 #if defined(DDB) && defined(DEBUG) 291 if (fpe_debug & FPE_EX) { 292 vm_offset_t loc = tf->srr0; 293 294 printf("Trying to emulate: %p ", (void *)loc); 295 opc_disasm(loc, instr.i_int); 296 } 297 #endif 298 299 /* 300 * `Decode' and execute instruction. 301 */ 302 303 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 304 instr.i_any.i_opcd == OPC_integer_31) { 305 /* 306 * Handle load/store insns: 307 * 308 * Convert to/from single if needed, calculate addr, 309 * and update index reg if needed. 310 */ 311 double buf; 312 size_t size = sizeof(float); 313 int store, update; 314 315 cond = 0; /* ld/st never set condition codes */ 316 317 318 if (instr.i_any.i_opcd == OPC_integer_31) { 319 if (instr.i_x.i_xo == OPC31_STFIWX) { 320 FPU_EMU_EVCNT_INCR(stfiwx); 321 322 /* Store as integer */ 323 ra = instr.i_x.i_ra; 324 rb = instr.i_x.i_rb; 325 DPRINTF(FPE_INSN, 326 ("reg %d has %jx reg %d has %jx\n", 327 ra, (uintmax_t)tf->fixreg[ra], rb, 328 (uintmax_t)tf->fixreg[rb])); 329 330 addr = tf->fixreg[rb]; 331 if (ra != 0) 332 addr += tf->fixreg[ra]; 333 rt = instr.i_x.i_rt; 334 a = (int *)&fs->fpr[rt].fpr; 335 DPRINTF(FPE_INSN, 336 ("fpu_execute: Store INT %x at %p\n", 337 a[1], (void *)addr)); 338 if (copyout(&a[1], (void *)addr, sizeof(int))) 339 return (FAULT); 340 return (0); 341 } 342 343 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 344 /* Not an indexed FP load/store op */ 345 return (NOTFPU); 346 347 store = (instr.i_x.i_xo & 0x80); 348 if (instr.i_x.i_xo & 0x40) 349 size = sizeof(double); 350 else 351 type = FTYPE_SNG; 352 update = (instr.i_x.i_xo & 0x20); 353 354 /* calculate EA of load/store */ 355 ra = instr.i_x.i_ra; 356 rb = instr.i_x.i_rb; 357 DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n", 358 ra, (uintmax_t)tf->fixreg[ra], rb, 359 (uintmax_t)tf->fixreg[rb])); 360 addr = tf->fixreg[rb]; 361 if (ra != 0) 362 addr += tf->fixreg[ra]; 363 rt = instr.i_x.i_rt; 364 } else { 365 store = instr.i_d.i_opcd & 0x4; 366 if (instr.i_d.i_opcd & 0x2) 367 size = sizeof(double); 368 else 369 type = FTYPE_SNG; 370 update = instr.i_d.i_opcd & 0x1; 371 372 /* calculate EA of load/store */ 373 ra = instr.i_d.i_ra; 374 addr = instr.i_d.i_d; 375 DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n", 376 ra, (uintmax_t)tf->fixreg[ra], 377 (uintmax_t)addr)); 378 if (ra != 0) 379 addr += tf->fixreg[ra]; 380 rt = instr.i_d.i_rt; 381 } 382 383 if (update && ra == 0) 384 return (NOTFPU); 385 386 if (store) { 387 /* Store */ 388 FPU_EMU_EVCNT_INCR(fpstore); 389 if (type != FTYPE_DBL) { 390 DPRINTF(FPE_INSN, 391 ("fpu_execute: Store SNG at %p\n", 392 (void *)addr)); 393 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 394 fpu_implode(fe, fp, type, (void *)&buf); 395 if (copyout(&buf, (void *)addr, size)) 396 return (FAULT); 397 } else { 398 DPRINTF(FPE_INSN, 399 ("fpu_execute: Store DBL at %p\n", 400 (void *)addr)); 401 if (copyout(&fs->fpr[rt].fpr, (void *)addr, 402 size)) 403 return (FAULT); 404 } 405 } else { 406 /* Load */ 407 FPU_EMU_EVCNT_INCR(fpload); 408 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 409 (void *)addr)); 410 if (copyin((const void *)addr, &fs->fpr[rt].fpr, 411 size)) 412 return (FAULT); 413 if (type != FTYPE_DBL) { 414 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 415 fpu_implode(fe, fp, FTYPE_DBL, 416 (u_int *)&fs->fpr[rt].fpr); 417 } 418 } 419 if (update) 420 tf->fixreg[ra] = addr; 421 /* Complete. */ 422 return (0); 423 #ifdef notyet 424 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 425 /* These are 64-bit extensions */ 426 return (NOTFPU); 427 #endif 428 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 429 instr.i_any.i_opcd == OPC_dp_fp_63) { 430 431 432 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 433 !(instr.i_a.i_xo & OPC63M_MASK)) { 434 /* Format X */ 435 rt = instr.i_x.i_rt; 436 ra = instr.i_x.i_ra; 437 rb = instr.i_x.i_rb; 438 439 440 /* One of the special opcodes.... */ 441 switch (instr.i_x.i_xo) { 442 case OPC63_FCMPU: 443 FPU_EMU_EVCNT_INCR(fcmpu); 444 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 445 rt >>= 2; 446 fpu_explode(fe, &fe->fe_f1, type, ra); 447 fpu_explode(fe, &fe->fe_f2, type, rb); 448 fpu_compare(fe, 0); 449 /* Make sure we do the condition regs. */ 450 cond = 0; 451 /* N.B.: i_rs is already left shifted by two. */ 452 bf = instr.i_x.i_rs & 0xfc; 453 setcr = 1; 454 break; 455 456 case OPC63_FRSP: 457 /* 458 * Convert to single: 459 * 460 * PowerPC uses this to round a double 461 * precision value to single precision, 462 * but values in registers are always 463 * stored in double precision format. 464 */ 465 FPU_EMU_EVCNT_INCR(frsp); 466 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 467 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 468 fpu_implode(fe, fp, FTYPE_SNG, 469 (u_int *)&fs->fpr[rt].fpr); 470 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 471 type = FTYPE_DBL; 472 break; 473 case OPC63_FCTIW: 474 case OPC63_FCTIWZ: 475 FPU_EMU_EVCNT_INCR(fctiw); 476 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 477 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 478 type = FTYPE_INT; 479 break; 480 case OPC63_FCMPO: 481 FPU_EMU_EVCNT_INCR(fcmpo); 482 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 483 rt >>= 2; 484 fpu_explode(fe, &fe->fe_f1, type, ra); 485 fpu_explode(fe, &fe->fe_f2, type, rb); 486 fpu_compare(fe, 1); 487 /* Make sure we do the condition regs. */ 488 cond = 0; 489 /* N.B.: i_rs is already left shifted by two. */ 490 bf = instr.i_x.i_rs & 0xfc; 491 setcr = 1; 492 break; 493 case OPC63_MTFSB1: 494 FPU_EMU_EVCNT_INCR(mtfsb1); 495 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 496 fe->fe_fpscr |= 497 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 498 break; 499 case OPC63_FNEG: 500 FPU_EMU_EVCNT_INCR(fnegabs); 501 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 502 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 503 sizeof(double)); 504 a = (int *)&fs->fpr[rt].fpr; 505 *a ^= (1U << 31); 506 break; 507 case OPC63_MCRFS: 508 FPU_EMU_EVCNT_INCR(mcrfs); 509 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 510 cond = 0; 511 rt &= 0x1c; 512 ra &= 0x1c; 513 /* Extract the bits we want */ 514 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 515 /* Clear the bits we copied. */ 516 fe->fe_cx = 517 (FPSR_EX_MSK | (0xf << (28 - ra))); 518 fe->fe_fpscr &= fe->fe_cx; 519 /* Now shove them in the right part of cr */ 520 tf->cr &= ~(0xf << (28 - rt)); 521 tf->cr |= (mask << (28 - rt)); 522 break; 523 case OPC63_MTFSB0: 524 FPU_EMU_EVCNT_INCR(mtfsb0); 525 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 526 fe->fe_fpscr &= 527 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 528 break; 529 case OPC63_FMR: 530 FPU_EMU_EVCNT_INCR(fmr); 531 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 532 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 533 sizeof(double)); 534 break; 535 case OPC63_MTFSFI: 536 FPU_EMU_EVCNT_INCR(mtfsfi); 537 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 538 rb >>= 1; 539 rt &= 0x1c; /* Already left-shifted 4 */ 540 fe->fe_cx = rb << (28 - rt); 541 mask = 0xf<<(28 - rt); 542 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 543 fe->fe_cx; 544 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 545 break; 546 case OPC63_FNABS: 547 FPU_EMU_EVCNT_INCR(fnabs); 548 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 549 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 550 sizeof(double)); 551 a = (int *)&fs->fpr[rt].fpr; 552 *a |= (1U << 31); 553 break; 554 case OPC63_FABS: 555 FPU_EMU_EVCNT_INCR(fabs); 556 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 557 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr, 558 sizeof(double)); 559 a = (int *)&fs->fpr[rt].fpr; 560 *a &= ~(1U << 31); 561 break; 562 case OPC63_MFFS: 563 FPU_EMU_EVCNT_INCR(mffs); 564 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 565 memcpy(&fs->fpr[rt].fpr, &fs->fpscr, 566 sizeof(fs->fpscr)); 567 break; 568 case OPC63_MTFSF: 569 FPU_EMU_EVCNT_INCR(mtfsf); 570 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 571 if ((rt = instr.i_xfl.i_flm) == -1) 572 mask = -1; 573 else { 574 mask = 0; 575 /* Convert 1 bit -> 4 bits */ 576 for (ra = 0; ra < 8; ra ++) 577 if (rt & (1<<ra)) 578 mask |= (0xf<<(4*ra)); 579 } 580 a = (int *)&fs->fpr[rt].fpr; 581 fe->fe_cx = mask & a[1]; 582 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 583 (fe->fe_cx); 584 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 585 break; 586 case OPC63_FCTID: 587 case OPC63_FCTIDZ: 588 FPU_EMU_EVCNT_INCR(fctid); 589 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 590 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 591 type = FTYPE_LNG; 592 break; 593 case OPC63_FCFID: 594 FPU_EMU_EVCNT_INCR(fcfid); 595 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 596 type = FTYPE_LNG; 597 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 598 type = FTYPE_DBL; 599 break; 600 default: 601 return (NOTFPU); 602 break; 603 } 604 } else { 605 /* Format A */ 606 rt = instr.i_a.i_frt; 607 ra = instr.i_a.i_fra; 608 rb = instr.i_a.i_frb; 609 rc = instr.i_a.i_frc; 610 611 /* 612 * All arithmetic operations work on registers, which 613 * are stored as doubles. 614 */ 615 type = FTYPE_DBL; 616 switch ((unsigned int)instr.i_a.i_xo) { 617 case OPC59_FDIVS: 618 FPU_EMU_EVCNT_INCR(fdiv); 619 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 620 fpu_explode(fe, &fe->fe_f1, type, ra); 621 fpu_explode(fe, &fe->fe_f2, type, rb); 622 fp = fpu_div(fe); 623 break; 624 case OPC59_FSUBS: 625 FPU_EMU_EVCNT_INCR(fsub); 626 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 627 fpu_explode(fe, &fe->fe_f1, type, ra); 628 fpu_explode(fe, &fe->fe_f2, type, rb); 629 fp = fpu_sub(fe); 630 break; 631 case OPC59_FADDS: 632 FPU_EMU_EVCNT_INCR(fadd); 633 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 634 fpu_explode(fe, &fe->fe_f1, type, ra); 635 fpu_explode(fe, &fe->fe_f2, type, rb); 636 fp = fpu_add(fe); 637 break; 638 case OPC59_FSQRTS: 639 FPU_EMU_EVCNT_INCR(fsqrt); 640 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 641 fpu_explode(fe, &fe->fe_f1, type, rb); 642 fp = fpu_sqrt(fe); 643 break; 644 case OPC63M_FSEL: 645 FPU_EMU_EVCNT_INCR(fsel); 646 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 647 a = (int *)&fe->fe_fpstate->fpr[ra].fpr; 648 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 649 /* fra < 0 */ 650 rc = rb; 651 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 652 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr, 653 sizeof(double)); 654 break; 655 case OPC59_FRES: 656 FPU_EMU_EVCNT_INCR(fpres); 657 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 658 fpu_explode(fe, &fe->fe_f1, type, rb); 659 fp = fpu_sqrt(fe); 660 /* now we've gotta overwrite the dest reg */ 661 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 662 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 663 fpu_div(fe); 664 break; 665 case OPC59_FMULS: 666 FPU_EMU_EVCNT_INCR(fmul); 667 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 668 fpu_explode(fe, &fe->fe_f1, type, ra); 669 fpu_explode(fe, &fe->fe_f2, type, rc); 670 fp = fpu_mul(fe); 671 break; 672 case OPC63M_FRSQRTE: 673 /* Reciprocal sqrt() estimate */ 674 FPU_EMU_EVCNT_INCR(frsqrte); 675 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 676 fpu_explode(fe, &fe->fe_f1, type, rb); 677 fp = fpu_sqrt(fe); 678 fe->fe_f2 = *fp; 679 /* now we've gotta overwrite the dest reg */ 680 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1; 681 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 682 fpu_div(fe); 683 break; 684 case OPC59_FMSUBS: 685 FPU_EMU_EVCNT_INCR(fmulsub); 686 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 687 fpu_explode(fe, &fe->fe_f1, type, ra); 688 fpu_explode(fe, &fe->fe_f2, type, rc); 689 fp = fpu_mul(fe); 690 fe->fe_f1 = *fp; 691 fpu_explode(fe, &fe->fe_f2, type, rb); 692 fp = fpu_sub(fe); 693 break; 694 case OPC59_FMADDS: 695 FPU_EMU_EVCNT_INCR(fmuladd); 696 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 697 fpu_explode(fe, &fe->fe_f1, type, ra); 698 fpu_explode(fe, &fe->fe_f2, type, rc); 699 fp = fpu_mul(fe); 700 fe->fe_f1 = *fp; 701 fpu_explode(fe, &fe->fe_f2, type, rb); 702 fp = fpu_add(fe); 703 break; 704 case OPC59_FNMSUBS: 705 FPU_EMU_EVCNT_INCR(fnmsub); 706 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 707 fpu_explode(fe, &fe->fe_f1, type, ra); 708 fpu_explode(fe, &fe->fe_f2, type, rc); 709 fp = fpu_mul(fe); 710 fe->fe_f1 = *fp; 711 fpu_explode(fe, &fe->fe_f2, type, rb); 712 fp = fpu_sub(fe); 713 /* Negate */ 714 fp->fp_sign ^= 1; 715 break; 716 case OPC59_FNMADDS: 717 FPU_EMU_EVCNT_INCR(fnmadd); 718 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 719 fpu_explode(fe, &fe->fe_f1, type, ra); 720 fpu_explode(fe, &fe->fe_f2, type, rc); 721 fp = fpu_mul(fe); 722 fe->fe_f1 = *fp; 723 fpu_explode(fe, &fe->fe_f2, type, rb); 724 fp = fpu_add(fe); 725 /* Negate */ 726 fp->fp_sign ^= 1; 727 break; 728 default: 729 return (NOTFPU); 730 break; 731 } 732 733 /* If the instruction was single precision, round */ 734 if (!(instr.i_any.i_opcd & 0x4)) { 735 fpu_implode(fe, fp, FTYPE_SNG, 736 (u_int *)&fs->fpr[rt].fpr); 737 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 738 } 739 } 740 } else { 741 return (NOTFPU); 742 } 743 744 /* 745 * ALU operation is complete. Collapse the result and then check 746 * for exceptions. If we got any, and they are enabled, do not 747 * alter the destination register, just stop with an exception. 748 * Otherwise set new current exceptions and accrue. 749 */ 750 if (fp) 751 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr); 752 cx = fe->fe_cx; 753 fsr = fe->fe_fpscr; 754 if (cx != 0) { 755 fsr &= ~FPSCR_FX; 756 if ((cx^fsr)&FPSR_EX_MSK) 757 fsr |= FPSCR_FX; 758 mask = fsr & FPSR_EX; 759 mask <<= (25-3); 760 if (cx & mask) 761 fsr |= FPSCR_FEX; 762 if (cx & FPSCR_FPRF) { 763 /* Need to replace CC */ 764 fsr &= ~FPSCR_FPRF; 765 } 766 if (cx & (FPSR_EXOP)) 767 fsr |= FPSCR_VX; 768 fsr |= cx; 769 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 770 } 771 772 if (cond) { 773 cond = fsr & 0xf0000000; 774 /* Isolate condition codes */ 775 cond >>= 28; 776 /* Move fpu condition codes to cr[1] */ 777 tf->cr &= (0x0f000000); 778 tf->cr |= (cond<<24); 779 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 780 } 781 782 if (setcr) { 783 cond = fsr & FPSCR_FPCC; 784 /* Isolate condition codes */ 785 cond <<= 16; 786 /* Move fpu condition codes to cr[1] */ 787 tf->cr &= ~(0xf0000000>>bf); 788 tf->cr |= (cond>>bf); 789 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n", 790 bf/4, (uintmax_t)tf->cr, cond)); 791 } 792 793 ((int *)&fs->fpscr)[1] = fsr; 794 if (fsr & FPSCR_FEX) 795 return(FPE); 796 return (0); /* success */ 797 } 798