1 /* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_div.c 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * Perform an FPU divide (return x / y). 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/fpu.h> 56 #include <machine/reg.h> 57 58 #include <powerpc/fpu/fpu_arith.h> 59 #include <powerpc/fpu/fpu_emu.h> 60 61 /* 62 * Division of normal numbers is done as follows: 63 * 64 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e. 65 * If X and Y are the mantissas (1.bbbb's), the quotient is then: 66 * 67 * q = (X / Y) * 2^((x exponent) - (y exponent)) 68 * 69 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y) 70 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only 71 * if X < Y. In that case, it will have to be shifted left one bit to 72 * become a normal number, and the exponent decremented. Thus, the 73 * desired exponent is: 74 * 75 * left_shift = x->fp_mant < y->fp_mant; 76 * result_exp = x->fp_exp - y->fp_exp - left_shift; 77 * 78 * The quotient mantissa X/Y can then be computed one bit at a time 79 * using the following algorithm: 80 * 81 * Q = 0; -- Initial quotient. 82 * R = X; -- Initial remainder, 83 * if (left_shift) -- but fixed up in advance. 84 * R *= 2; 85 * for (bit = FP_NMANT; --bit >= 0; R *= 2) { 86 * if (R >= Y) { 87 * Q |= 1 << bit; 88 * R -= Y; 89 * } 90 * } 91 * 92 * The subtraction R -= Y always removes the uppermost bit from R (and 93 * can sometimes remove additional lower-order 1 bits); this proof is 94 * left to the reader. 95 * 96 * This loop correctly calculates the guard and round bits since they are 97 * included in the expanded internal representation. The sticky bit 98 * is to be set if and only if any other bits beyond guard and round 99 * would be set. From the above it is obvious that this is true if and 100 * only if the remainder R is nonzero when the loop terminates. 101 * 102 * Examining the loop above, we can see that the quotient Q is built 103 * one bit at a time ``from the top down''. This means that we can 104 * dispense with the multi-word arithmetic and just build it one word 105 * at a time, writing each result word when it is done. 106 * 107 * Furthermore, since X and Y are both in [1.0,2.0), we know that, 108 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and 109 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1 110 * set, and R can be set initially to either X - Y (when X >= Y) or 111 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult, 112 * so we will simply calculate R - Y and see if that underflows. 113 * This leads to the following revised version of the algorithm: 114 * 115 * R = X; 116 * bit = FP_1; 117 * D = R - Y; 118 * if (D >= 0) { 119 * result_exp = x->fp_exp - y->fp_exp; 120 * R = D; 121 * q = bit; 122 * bit >>= 1; 123 * } else { 124 * result_exp = x->fp_exp - y->fp_exp - 1; 125 * q = 0; 126 * } 127 * R <<= 1; 128 * do { 129 * D = R - Y; 130 * if (D >= 0) { 131 * q |= bit; 132 * R = D; 133 * } 134 * R <<= 1; 135 * } while ((bit >>= 1) != 0); 136 * Q[0] = q; 137 * for (i = 1; i < 4; i++) { 138 * q = 0, bit = 1 << 31; 139 * do { 140 * D = R - Y; 141 * if (D >= 0) { 142 * q |= bit; 143 * R = D; 144 * } 145 * R <<= 1; 146 * } while ((bit >>= 1) != 0); 147 * Q[i] = q; 148 * } 149 * 150 * This can be refined just a bit further by moving the `R <<= 1' 151 * calculations to the front of the do-loops and eliding the first one. 152 * The process can be terminated immediately whenever R becomes 0, but 153 * this is relatively rare, and we do not bother. 154 */ 155 156 struct fpn * 157 fpu_div(struct fpemu *fe) 158 { 159 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 160 u_int q, bit; 161 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3; 162 FPU_DECL_CARRY 163 164 /* 165 * Since divide is not commutative, we cannot just use ORDER. 166 * Check either operand for NaN first; if there is at least one, 167 * order the signalling one (if only one) onto the right, then 168 * return it. Otherwise we have the following cases: 169 * 170 * Inf / Inf = NaN, plus NV exception 171 * Inf / num = Inf [i.e., return x] 172 * Inf / 0 = Inf [i.e., return x] 173 * 0 / Inf = 0 [i.e., return x] 174 * 0 / num = 0 [i.e., return x] 175 * 0 / 0 = NaN, plus NV exception 176 * num / Inf = 0 177 * num / num = num (do the divide) 178 * num / 0 = Inf, plus DZ exception 179 */ 180 DPRINTF(FPE_REG, ("fpu_div:\n")); 181 DUMPFPN(FPE_REG, x); 182 DUMPFPN(FPE_REG, y); 183 DPRINTF(FPE_REG, ("=>\n")); 184 if (ISNAN(x) || ISNAN(y)) { 185 ORDER(x, y); 186 fe->fe_cx |= FPSCR_VXSNAN; 187 DUMPFPN(FPE_REG, y); 188 return (y); 189 } 190 /* 191 * Need to split the following out cause they generate different 192 * exceptions. 193 */ 194 if (ISINF(x)) { 195 if (x->fp_class == y->fp_class) { 196 fe->fe_cx |= FPSCR_VXIDI; 197 return (fpu_newnan(fe)); 198 } 199 DUMPFPN(FPE_REG, x); 200 return (x); 201 } 202 if (ISZERO(x)) { 203 fe->fe_cx |= FPSCR_ZX; 204 if (x->fp_class == y->fp_class) { 205 fe->fe_cx |= FPSCR_VXZDZ; 206 return (fpu_newnan(fe)); 207 } 208 DUMPFPN(FPE_REG, x); 209 return (x); 210 } 211 212 /* all results at this point use XOR of operand signs */ 213 x->fp_sign ^= y->fp_sign; 214 if (ISINF(y)) { 215 x->fp_class = FPC_ZERO; 216 DUMPFPN(FPE_REG, x); 217 return (x); 218 } 219 if (ISZERO(y)) { 220 fe->fe_cx = FPSCR_ZX; 221 x->fp_class = FPC_INF; 222 DUMPFPN(FPE_REG, x); 223 return (x); 224 } 225 226 /* 227 * Macros for the divide. See comments at top for algorithm. 228 * Note that we expand R, D, and Y here. 229 */ 230 231 #define SUBTRACT /* D = R - Y */ \ 232 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \ 233 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0) 234 235 #define NONNEGATIVE /* D >= 0 */ \ 236 ((int)d0 >= 0) 237 238 #ifdef FPU_SHL1_BY_ADD 239 #define SHL1 /* R <<= 1 */ \ 240 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \ 241 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0) 242 #else 243 #define SHL1 \ 244 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \ 245 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1 246 #endif 247 248 #define LOOP /* do ... while (bit >>= 1) */ \ 249 do { \ 250 SHL1; \ 251 SUBTRACT; \ 252 if (NONNEGATIVE) { \ 253 q |= bit; \ 254 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \ 255 } \ 256 } while ((bit >>= 1) != 0) 257 258 #define WORD(r, i) /* calculate r->fp_mant[i] */ \ 259 q = 0; \ 260 bit = 1 << 31; \ 261 LOOP; \ 262 (x)->fp_mant[i] = q 263 264 /* Setup. Note that we put our result in x. */ 265 r0 = x->fp_mant[0]; 266 r1 = x->fp_mant[1]; 267 r2 = x->fp_mant[2]; 268 r3 = x->fp_mant[3]; 269 y0 = y->fp_mant[0]; 270 y1 = y->fp_mant[1]; 271 y2 = y->fp_mant[2]; 272 y3 = y->fp_mant[3]; 273 274 bit = FP_1; 275 SUBTRACT; 276 if (NONNEGATIVE) { 277 x->fp_exp -= y->fp_exp; 278 r0 = d0, r1 = d1, r2 = d2, r3 = d3; 279 q = bit; 280 bit >>= 1; 281 } else { 282 x->fp_exp -= y->fp_exp + 1; 283 q = 0; 284 } 285 LOOP; 286 x->fp_mant[0] = q; 287 WORD(x, 1); 288 WORD(x, 2); 289 WORD(x, 3); 290 x->fp_sticky = r0 | r1 | r2 | r3; 291 292 DUMPFPN(FPE_REG, x); 293 return (x); 294 } 295