1 /* $NetBSD: fpu_arith.h,v 1.4 2005/12/24 20:07:28 perry Exp $ */ 2 /* $FreeBSD$ */ 3 4 /*- 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Copyright (c) 1992, 1993 8 * The Regents of the University of California. All rights reserved. 9 * 10 * This software was developed by the Computer Systems Engineering group 11 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 12 * contributed to Berkeley. 13 * 14 * All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * @(#)fpu_arith.h 8.1 (Berkeley) 6/11/93 44 */ 45 46 /* 47 * Extended-precision arithmetic. 48 * 49 * We hold the notion of a `carry register', which may or may not be a 50 * machine carry bit or register. On the SPARC, it is just the machine's 51 * carry bit. 52 * 53 * In the worst case, you can compute the carry from x+y as 54 * (unsigned)(x + y) < (unsigned)x 55 * and from x+y+c as 56 * ((unsigned)(x + y + c) <= (unsigned)x && (y|c) != 0) 57 * for example. 58 */ 59 60 #ifndef FPE_USE_ASM 61 62 /* set up for extended-precision arithemtic */ 63 #define FPU_DECL_CARRY quad_t fpu_carry, fpu_tmp; 64 65 /* 66 * We have three kinds of add: 67 * add with carry: r = x + y + c 68 * add (ignoring current carry) and set carry: c'r = x + y + 0 69 * add with carry and set carry: c'r = x + y + c 70 * The macros use `C' for `use carry' and `S' for `set carry'. 71 * Note that the state of the carry is undefined after ADDC and SUBC, 72 * so if all you have for these is `add with carry and set carry', 73 * that is OK. 74 * 75 * The same goes for subtract, except that we compute x - y - c. 76 * 77 * Finally, we have a way to get the carry into a `regular' variable, 78 * or set it from a value. SET_CARRY turns 0 into no-carry, nonzero 79 * into carry; GET_CARRY sets its argument to 0 or 1. 80 */ 81 #define FPU_ADDC(r, x, y) \ 82 (r) = (x) + (y) + (!!fpu_carry) 83 #define FPU_ADDS(r, x, y) \ 84 { \ 85 fpu_tmp = (quad_t)(x) + (quad_t)(y); \ 86 (r) = (u_int)fpu_tmp; \ 87 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 88 } 89 #define FPU_ADDCS(r, x, y) \ 90 { \ 91 fpu_tmp = (quad_t)(x) + (quad_t)(y) + (!!fpu_carry); \ 92 (r) = (u_int)fpu_tmp; \ 93 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 94 } 95 #define FPU_SUBC(r, x, y) \ 96 (r) = (x) - (y) - (!!fpu_carry) 97 #define FPU_SUBS(r, x, y) \ 98 { \ 99 fpu_tmp = (quad_t)(x) - (quad_t)(y); \ 100 (r) = (u_int)fpu_tmp; \ 101 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 102 } 103 #define FPU_SUBCS(r, x, y) \ 104 { \ 105 fpu_tmp = (quad_t)(x) - (quad_t)(y) - (!!fpu_carry); \ 106 (r) = (u_int)fpu_tmp; \ 107 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 108 } 109 110 #define FPU_GET_CARRY(r) (r) = (!!fpu_carry) 111 #define FPU_SET_CARRY(v) fpu_carry = ((v) != 0) 112 113 #else 114 /* set up for extended-precision arithemtic */ 115 #define FPU_DECL_CARRY 116 117 /* 118 * We have three kinds of add: 119 * add with carry: r = x + y + c 120 * add (ignoring current carry) and set carry: c'r = x + y + 0 121 * add with carry and set carry: c'r = x + y + c 122 * The macros use `C' for `use carry' and `S' for `set carry'. 123 * Note that the state of the carry is undefined after ADDC and SUBC, 124 * so if all you have for these is `add with carry and set carry', 125 * that is OK. 126 * 127 * The same goes for subtract, except that we compute x - y - c. 128 * 129 * Finally, we have a way to get the carry into a `regular' variable, 130 * or set it from a value. SET_CARRY turns 0 into no-carry, nonzero 131 * into carry; GET_CARRY sets its argument to 0 or 1. 132 */ 133 #define FPU_ADDC(r, x, y) \ 134 __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y)) 135 #define FPU_ADDS(r, x, y) \ 136 __asm volatile("addc %0,%1,%2" : "=r"(r) : "r"(x), "r"(y)) 137 #define FPU_ADDCS(r, x, y) \ 138 __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y)) 139 #define FPU_SUBC(r, x, y) \ 140 __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y)) 141 #define FPU_SUBS(r, x, y) \ 142 __asm volatile("subfc %0,%2,%1" : "=r"(r) : "r"(x), "r"(y)) 143 #define FPU_SUBCS(r, x, y) \ 144 __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y)) 145 146 #define FPU_GET_CARRY(r) __asm volatile("li %0,0; addie %0,%0,0" : "=r"(r)) 147 /* This one needs to destroy a temp register. */ 148 #define FPU_SET_CARRY(v) do { int __tmp; \ 149 __asm volatile("addic %0,%0,-1" : "r"(__tmp) : "r"(v)); \ 150 } while (0) 151 152 #define FPU_SHL1_BY_ADD /* shift left 1 faster by ADDC than (a<<1)|(b>>31) */ 153 #endif 154