1 /* $NetBSD: fpu_arith.h,v 1.4 2005/12/24 20:07:28 perry Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 */ 42 43 /* 44 * Extended-precision arithmetic. 45 * 46 * We hold the notion of a `carry register', which may or may not be a 47 * machine carry bit or register. On the SPARC, it is just the machine's 48 * carry bit. 49 * 50 * In the worst case, you can compute the carry from x+y as 51 * (unsigned)(x + y) < (unsigned)x 52 * and from x+y+c as 53 * ((unsigned)(x + y + c) <= (unsigned)x && (y|c) != 0) 54 * for example. 55 */ 56 57 #ifndef FPE_USE_ASM 58 59 /* set up for extended-precision arithemtic */ 60 #define FPU_DECL_CARRY quad_t fpu_carry, fpu_tmp; 61 62 /* 63 * We have three kinds of add: 64 * add with carry: r = x + y + c 65 * add (ignoring current carry) and set carry: c'r = x + y + 0 66 * add with carry and set carry: c'r = x + y + c 67 * The macros use `C' for `use carry' and `S' for `set carry'. 68 * Note that the state of the carry is undefined after ADDC and SUBC, 69 * so if all you have for these is `add with carry and set carry', 70 * that is OK. 71 * 72 * The same goes for subtract, except that we compute x - y - c. 73 * 74 * Finally, we have a way to get the carry into a `regular' variable, 75 * or set it from a value. SET_CARRY turns 0 into no-carry, nonzero 76 * into carry; GET_CARRY sets its argument to 0 or 1. 77 */ 78 #define FPU_ADDC(r, x, y) \ 79 (r) = (x) + (y) + (!!fpu_carry) 80 #define FPU_ADDS(r, x, y) \ 81 { \ 82 fpu_tmp = (quad_t)(x) + (quad_t)(y); \ 83 (r) = (u_int)fpu_tmp; \ 84 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 85 } 86 #define FPU_ADDCS(r, x, y) \ 87 { \ 88 fpu_tmp = (quad_t)(x) + (quad_t)(y) + (!!fpu_carry); \ 89 (r) = (u_int)fpu_tmp; \ 90 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 91 } 92 #define FPU_SUBC(r, x, y) \ 93 (r) = (x) - (y) - (!!fpu_carry) 94 #define FPU_SUBS(r, x, y) \ 95 { \ 96 fpu_tmp = (quad_t)(x) - (quad_t)(y); \ 97 (r) = (u_int)fpu_tmp; \ 98 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 99 } 100 #define FPU_SUBCS(r, x, y) \ 101 { \ 102 fpu_tmp = (quad_t)(x) - (quad_t)(y) - (!!fpu_carry); \ 103 (r) = (u_int)fpu_tmp; \ 104 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \ 105 } 106 107 #define FPU_GET_CARRY(r) (r) = (!!fpu_carry) 108 #define FPU_SET_CARRY(v) fpu_carry = ((v) != 0) 109 110 #else 111 /* set up for extended-precision arithemtic */ 112 #define FPU_DECL_CARRY 113 114 /* 115 * We have three kinds of add: 116 * add with carry: r = x + y + c 117 * add (ignoring current carry) and set carry: c'r = x + y + 0 118 * add with carry and set carry: c'r = x + y + c 119 * The macros use `C' for `use carry' and `S' for `set carry'. 120 * Note that the state of the carry is undefined after ADDC and SUBC, 121 * so if all you have for these is `add with carry and set carry', 122 * that is OK. 123 * 124 * The same goes for subtract, except that we compute x - y - c. 125 * 126 * Finally, we have a way to get the carry into a `regular' variable, 127 * or set it from a value. SET_CARRY turns 0 into no-carry, nonzero 128 * into carry; GET_CARRY sets its argument to 0 or 1. 129 */ 130 #define FPU_ADDC(r, x, y) \ 131 __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y)) 132 #define FPU_ADDS(r, x, y) \ 133 __asm volatile("addc %0,%1,%2" : "=r"(r) : "r"(x), "r"(y)) 134 #define FPU_ADDCS(r, x, y) \ 135 __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y)) 136 #define FPU_SUBC(r, x, y) \ 137 __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y)) 138 #define FPU_SUBS(r, x, y) \ 139 __asm volatile("subfc %0,%2,%1" : "=r"(r) : "r"(x), "r"(y)) 140 #define FPU_SUBCS(r, x, y) \ 141 __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y)) 142 143 #define FPU_GET_CARRY(r) __asm volatile("li %0,0; addie %0,%0,0" : "=r"(r)) 144 /* This one needs to destroy a temp register. */ 145 #define FPU_SET_CARRY(v) do { int __tmp; \ 146 __asm volatile("addic %0,%0,-1" : "r"(__tmp) : "r"(v)); \ 147 } while (0) 148 149 #define FPU_SHL1_BY_ADD /* shift left 1 faster by ADDC than (a<<1)|(b>>31) */ 150 #endif 151