1 /*- 2 * Copyright (c) 2017 Justin Hibbits 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/cpu.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/smp.h> 35 36 #include <dev/ofw/ofw_bus.h> 37 #include <dev/ofw/ofw_bus_subr.h> 38 39 #include <machine/cpu.h> 40 41 #include <powerpc/mpc85xx/mpc85xx.h> 42 43 #include "cpufreq_if.h" 44 45 /* No worries about uint32_t math overflow in here, because the highest 46 * multiplier supported is 4, and the highest speed part is still well below 47 * 2GHz. 48 */ 49 50 #define GUTS_PORPLLSR (CCSRBAR_VA + 0xe0000) 51 #define GUTS_PMJCR (CCSRBAR_VA + 0xe007c) 52 #define PMJCR_RATIO_M 0x3f 53 #define PMJCR_CORE_MULT(x,y) ((x) << (16 + ((y) * 8))) 54 #define PMJCR_GET_CORE_MULT(x,y) (((x) >> (16 + ((y) * 8))) & 0x3f) 55 #define GUTS_POWMGTCSR (CCSRBAR_VA + 0xe0080) 56 #define POWMGTCSR_JOG 0x00200000 57 #define POWMGTCSR_INT_MASK 0x00000f00 58 59 #define MHZ 1000000 60 61 struct mpc85xx_jog_softc { 62 device_t dev; 63 int cpu; 64 int low; 65 int high; 66 int min_freq; 67 }; 68 69 static struct ofw_compat_data *mpc85xx_jog_devcompat(void); 70 static void mpc85xx_jog_identify(driver_t *driver, device_t parent); 71 static int mpc85xx_jog_probe(device_t dev); 72 static int mpc85xx_jog_attach(device_t dev); 73 static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count); 74 static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set); 75 static int mpc85xx_jog_get(device_t dev, struct cf_setting *set); 76 static int mpc85xx_jog_type(device_t dev, int *type); 77 78 static device_method_t mpc85xx_jog_methods[] = { 79 /* Device interface */ 80 DEVMETHOD(device_identify, mpc85xx_jog_identify), 81 DEVMETHOD(device_probe, mpc85xx_jog_probe), 82 DEVMETHOD(device_attach, mpc85xx_jog_attach), 83 84 /* cpufreq interface */ 85 DEVMETHOD(cpufreq_drv_set, mpc85xx_jog_set), 86 DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get), 87 DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type), 88 DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings), 89 {0, 0} 90 }; 91 92 static driver_t mpc85xx_jog_driver = { 93 "jog", 94 mpc85xx_jog_methods, 95 sizeof(struct mpc85xx_jog_softc) 96 }; 97 98 DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, 0, 0); 99 100 struct mpc85xx_constraints { 101 int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */ 102 int min_mult; /* Minimum PLL multiplier. */ 103 }; 104 105 static struct mpc85xx_constraints mpc8536_constraints = { 106 800, 107 3 108 }; 109 110 static struct mpc85xx_constraints p1022_constraints = { 111 500, 112 2 113 }; 114 115 static struct ofw_compat_data jog_compat[] = { 116 {"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints}, 117 {"fsl,p1022-guts", (uintptr_t)&p1022_constraints}, 118 {NULL, 0} 119 }; 120 121 static struct ofw_compat_data * 122 mpc85xx_jog_devcompat(void) 123 { 124 phandle_t node; 125 int i; 126 127 node = OF_finddevice("/soc"); 128 if (node == -1) 129 return (NULL); 130 131 for (i = 0; jog_compat[i].ocd_str != NULL; i++) 132 if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0) 133 break; 134 135 if (jog_compat[i].ocd_str == NULL) 136 return (NULL); 137 138 return (&jog_compat[i]); 139 } 140 141 static void 142 mpc85xx_jog_identify(driver_t *driver, device_t parent) 143 { 144 struct ofw_compat_data *compat; 145 146 /* Make sure we're not being doubly invoked. */ 147 if (device_find_child(parent, "mpc85xx_jog", -1) != NULL) 148 return; 149 150 compat = mpc85xx_jog_devcompat(); 151 if (compat == NULL) 152 return; 153 154 /* 155 * We attach a child for every CPU since settings need to 156 * be performed on every CPU in the SMP case. 157 */ 158 if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL) 159 device_printf(parent, "add jog child failed\n"); 160 } 161 162 static int 163 mpc85xx_jog_probe(device_t dev) 164 { 165 struct ofw_compat_data *compat; 166 167 compat = mpc85xx_jog_devcompat(); 168 if (compat == NULL || compat->ocd_str == NULL) 169 return (ENXIO); 170 171 device_set_desc(dev, "Freescale CPU Jogger"); 172 return (0); 173 } 174 175 static int 176 mpc85xx_jog_attach(device_t dev) 177 { 178 struct ofw_compat_data *compat; 179 struct mpc85xx_jog_softc *sc; 180 struct mpc85xx_constraints *constraints; 181 phandle_t cpu; 182 uint32_t reg; 183 184 sc = device_get_softc(dev); 185 sc->dev = dev; 186 187 compat = mpc85xx_jog_devcompat(); 188 constraints = (struct mpc85xx_constraints *)compat->ocd_data; 189 cpu = ofw_bus_get_node(device_get_parent(dev)); 190 191 if (cpu <= 0) { 192 device_printf(dev,"No CPU device tree node!\n"); 193 return (ENXIO); 194 } 195 196 OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu)); 197 198 reg = ccsr_read4(GUTS_PORPLLSR); 199 200 /* 201 * Assume power-on PLL is the highest PLL config supported on the 202 * board. 203 */ 204 sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu); 205 sc->min_freq = constraints->threshold; 206 sc->low = constraints->min_mult; 207 208 cpufreq_register(dev); 209 return (0); 210 } 211 212 static int 213 mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count) 214 { 215 struct mpc85xx_jog_softc *sc; 216 uint32_t sysclk; 217 int i; 218 219 sc = device_get_softc(dev); 220 if (sets == NULL || count == NULL) 221 return (EINVAL); 222 if (*count < sc->high - 1) 223 return (E2BIG); 224 225 sysclk = mpc85xx_get_system_clock(); 226 /* Return a list of valid settings for this driver. */ 227 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high); 228 229 for (i = sc->high; i >= sc->low; --i) { 230 sets[sc->high - i].freq = sysclk * i / MHZ; 231 sets[sc->high - i].dev = dev; 232 sets[sc->high - i].spec[0] = i; 233 } 234 *count = sc->high - sc->low + 1; 235 236 return (0); 237 } 238 239 struct jog_rv_args { 240 int cpu; 241 int mult; 242 int slow; 243 volatile int inprogress; 244 }; 245 246 static void 247 mpc85xx_jog_set_int(void *arg) 248 { 249 struct jog_rv_args *args = arg; 250 uint32_t reg; 251 252 if (PCPU_GET(cpuid) == args->cpu) { 253 reg = ccsr_read4(GUTS_PMJCR); 254 reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu); 255 reg |= PMJCR_CORE_MULT(args->mult, args->cpu); 256 if (args->slow) 257 reg &= ~(1 << (12 + args->cpu)); 258 else 259 reg |= (1 << (12 + args->cpu)); 260 261 ccsr_write4(GUTS_PMJCR, reg); 262 263 reg = ccsr_read4(GUTS_POWMGTCSR); 264 reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK; 265 ccsr_write4(GUTS_POWMGTCSR, reg); 266 267 /* Wait for completion */ 268 do { 269 DELAY(100); 270 reg = ccsr_read4(GUTS_POWMGTCSR); 271 } while (reg & POWMGTCSR_JOG); 272 273 reg = ccsr_read4(GUTS_POWMGTCSR); 274 ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK); 275 ccsr_read4(GUTS_POWMGTCSR); 276 277 args->inprogress = 0; 278 } else { 279 while (args->inprogress) 280 cpu_spinwait(); 281 } 282 } 283 284 static int 285 mpc85xx_jog_set(device_t dev, const struct cf_setting *set) 286 { 287 struct mpc85xx_jog_softc *sc; 288 struct jog_rv_args args; 289 290 if (set == NULL) 291 return (EINVAL); 292 293 sc = device_get_softc(dev); 294 295 args.slow = (set->freq <= sc->min_freq); 296 args.mult = set->spec[0]; 297 args.cpu = PCPU_GET(cpuid); 298 args.inprogress = 1; 299 smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int, 300 smp_no_rendezvous_barrier, &args); 301 302 return (0); 303 } 304 305 static int 306 mpc85xx_jog_get(device_t dev, struct cf_setting *set) 307 { 308 struct mpc85xx_jog_softc *sc; 309 uint32_t pmjcr; 310 uint32_t freq; 311 312 if (set == NULL) 313 return (EINVAL); 314 315 sc = device_get_softc(dev); 316 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 317 318 pmjcr = ccsr_read4(GUTS_PORPLLSR); 319 freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu); 320 freq *= mpc85xx_get_system_clock(); 321 freq /= MHZ; 322 323 set->freq = freq; 324 set->dev = dev; 325 326 return (0); 327 } 328 329 static int 330 mpc85xx_jog_type(device_t dev, int *type) 331 { 332 333 if (type == NULL) 334 return (EINVAL); 335 336 *type = CPUFREQ_TYPE_ABSOLUTE; 337 return (0); 338 } 339