1/*- 2 * Copyright (C) 2006-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * Copyright (C) 2006 Juniper Networks, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31/*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * from: $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ 62 */ 63 64/* 65 * NOTICE: This is not a standalone file. to use it, #include it in 66 * your port's locore.S, like so: 67 * 68 * #include <powerpc/booke/trap_subr.S> 69 */ 70 71/* 72 * SPRG usage notes 73 * 74 * SPRG0 - pcpu pointer 75 * SPRG1 - all interrupts except TLB miss, critical, machine check 76 * SPRG2 - critical 77 * SPRG3 - machine check 78 * 79 */ 80 81/* Get the per-CPU data structure */ 82#define GET_CPUINFO(r) mfsprg0 r 83 84/* 85 * Standard interrupt prolog 86 * 87 * sprg_sp - SPRG{1-3} reg used to temporarily store the SP 88 * savearea - temp save area (pc_{tempsave, disisave, critsave, mchksave}) 89 * isrr0-1 - save restore registers with CPU state at interrupt time (may be 90 * SRR0-1, CSRR0-1, MCSRR0-1 91 * 92 * 1. saves in the given savearea: 93 * - R30-31 94 * - DEAR, ESR 95 * - xSRR0-1 96 * 97 * 2. saves CR -> R30 98 * 99 * 3. switches to kstack if needed 100 * 101 * 4. notes: 102 * - R31 can be used as scratch register until a new frame is layed on 103 * the stack with FRAME_SETUP 104 * 105 * - potential TLB miss: NO. Saveareas are always acessible via TLB1 106 * permanent entries, and within this prolog we do not dereference any 107 * locations potentially not in the TLB 108 */ 109#define STANDARD_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 110 mtspr sprg_sp, %r1; /* Save SP */ \ 111 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 112 stw %r30, (savearea+CPUSAVE_R30)(%r1); \ 113 stw %r31, (savearea+CPUSAVE_R31)(%r1); \ 114 mfdear %r30; \ 115 mfesr %r31; \ 116 stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 117 stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 118 mfspr %r30, isrr0; \ 119 mfspr %r31, isrr1; /* MSR at interrupt time */ \ 120 stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 121 stw %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 122 isync; \ 123 mfspr %r1, sprg_sp; /* Restore SP */ \ 124 mfcr %r30; /* Save CR */ \ 125 /* switch to per-thread kstack if intr taken in user mode */ \ 126 mtcr %r31; /* MSR at interrupt time */ \ 127 bf 17, 1f; \ 128 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 129 lwz %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 1301: 131 132#define STANDARD_CRIT_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 133 mtspr sprg_sp, %r1; /* Save SP */ \ 134 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 135 stw %r30, (savearea+CPUSAVE_R30)(%r1); \ 136 stw %r31, (savearea+CPUSAVE_R31)(%r1); \ 137 mfdear %r30; \ 138 mfesr %r31; \ 139 stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 140 stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 141 mfspr %r30, isrr0; \ 142 mfspr %r31, isrr1; /* MSR at interrupt time */ \ 143 stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 144 stw %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 145 mfspr %r30, SPR_SRR0; \ 146 mfspr %r31, SPR_SRR1; /* MSR at interrupt time */ \ 147 stw %r30, (savearea+CPUSAVE_SRR0+8)(%r1); \ 148 stw %r31, (savearea+CPUSAVE_SRR1+8)(%r1); \ 149 isync; \ 150 mfspr %r1, sprg_sp; /* Restore SP */ \ 151 mfcr %r30; /* Save CR */ \ 152 /* switch to per-thread kstack if intr taken in user mode */ \ 153 mtcr %r31; /* MSR at interrupt time */ \ 154 bf 17, 1f; \ 155 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 156 lwz %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 1571: 158 159/* 160 * FRAME_SETUP assumes: 161 * SPRG{1-3} SP at the time interrupt occured 162 * savearea r30-r31, DEAR, ESR, xSRR0-1 163 * r30 CR 164 * r31 scratch 165 * r1 kernel stack 166 * 167 * sprg_sp - SPRG reg containing SP at the time interrupt occured 168 * savearea - temp save 169 * exc - exception number (EXC_xxx) 170 * 171 * 1. sets a new frame 172 * 2. saves in the frame: 173 * - R0, R1 (SP at the time of interrupt), R2, LR, CR 174 * - R3-31 (R30-31 first restored from savearea) 175 * - XER, CTR, DEAR, ESR (from savearea), xSRR0-1 176 * 177 * Notes: 178 * - potential TLB miss: YES, since we make dereferences to kstack, which 179 * can happen not covered (we can have up to two DTLB misses if fortunate 180 * enough i.e. when kstack crosses page boundary and both pages are 181 * untranslated) 182 */ 183#define FRAME_SETUP(sprg_sp, savearea, exc) \ 184 mfspr %r31, sprg_sp; /* get saved SP */ \ 185 /* establish a new stack frame and put everything on it */ \ 186 stwu %r31, -FRAMELEN(%r1); \ 187 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 188 stw %r31, FRAME_1+8(%r1); /* save SP " " */ \ 189 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 190 mflr %r31; \ 191 stw %r31, FRAME_LR+8(%r1); /* save LR " " */ \ 192 stw %r30, FRAME_CR+8(%r1); /* save CR " " */ \ 193 GET_CPUINFO(%r2); \ 194 lwz %r30, (savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 195 lwz %r31, (savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 196 /* save R3-31 */ \ 197 stmw %r3, FRAME_3+8(%r1) ; \ 198 /* save DEAR, ESR */ \ 199 lwz %r28, (savearea+CPUSAVE_BOOKE_DEAR)(%r2); \ 200 lwz %r29, (savearea+CPUSAVE_BOOKE_ESR)(%r2); \ 201 stw %r28, FRAME_BOOKE_DEAR+8(1); \ 202 stw %r29, FRAME_BOOKE_ESR+8(1); \ 203 /* save XER, CTR, exc number */ \ 204 mfxer %r3; \ 205 mfctr %r4; \ 206 stw %r3, FRAME_XER+8(1); \ 207 stw %r4, FRAME_CTR+8(1); \ 208 li %r5, exc; \ 209 stw %r5, FRAME_EXC+8(1); \ 210 /* save xSSR0-1 */ \ 211 lwz %r30, (savearea+CPUSAVE_SRR0)(%r2); \ 212 lwz %r31, (savearea+CPUSAVE_SRR1)(%r2); \ 213 stw %r30, FRAME_SRR0+8(1); \ 214 stw %r31, FRAME_SRR1+8(1) 215 216/* 217 * 218 * isrr0-1 - save restore registers to restore CPU state to (may be 219 * SRR0-1, CSRR0-1, MCSRR0-1 220 * 221 * Notes: 222 * - potential TLB miss: YES. The deref'd kstack may be not covered 223 */ 224#define FRAME_LEAVE(isrr0, isrr1) \ 225 /* restore CTR, XER, LR, CR */ \ 226 lwz %r4, FRAME_CTR+8(%r1); \ 227 lwz %r5, FRAME_XER+8(%r1); \ 228 lwz %r6, FRAME_LR+8(%r1); \ 229 lwz %r7, FRAME_CR+8(%r1); \ 230 mtctr %r4; \ 231 mtxer %r5; \ 232 mtlr %r6; \ 233 mtcr %r7; \ 234 /* restore xSRR0-1 */ \ 235 lwz %r30, FRAME_SRR0+8(%r1); \ 236 lwz %r31, FRAME_SRR1+8(%r1); \ 237 mtspr isrr0, %r30; \ 238 mtspr isrr1, %r31; \ 239 /* restore R2-31, SP */ \ 240 lmw %r2, FRAME_2+8(%r1) ; \ 241 lwz %r0, FRAME_0+8(%r1); \ 242 lwz %r1, FRAME_1+8(%r1); \ 243 isync 244 245/* 246 * TLB miss prolog 247 * 248 * saves LR, CR, SRR0-1, R20-31 in the TLBSAVE area 249 * 250 * Notes: 251 * - potential TLB miss: NO. It is crucial that we do not generate a TLB 252 * miss within the TLB prolog itself! 253 * - TLBSAVE is always translated 254 */ 255#define TLB_PROLOG \ 256 mtsprg4 %r1; /* Save SP */ \ 257 mtsprg5 %r28; \ 258 mtsprg6 %r29; \ 259 /* calculate TLB nesting level and TLBSAVE instance address */ \ 260 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 261 lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 262 rlwinm %r29, %r28, 6, 24, 25; /* 4 x TLBSAVE_LEN */ \ 263 addi %r28, %r28, 1; \ 264 stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 265 addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 266 add %r1, %r1, %r29; /* current TLBSAVE ptr */ \ 267 \ 268 /* save R20-31 */ \ 269 mfsprg5 %r28; \ 270 mfsprg6 %r29; \ 271 stmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \ 272 /* save LR, CR */ \ 273 mflr %r30; \ 274 mfcr %r31; \ 275 stw %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 276 stw %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 277 /* save SRR0-1 */ \ 278 mfsrr0 %r30; /* execution addr at interrupt time */ \ 279 mfsrr1 %r31; /* MSR at interrupt time*/ \ 280 stw %r30, (TLBSAVE_BOOKE_SRR0)(%r1); /* save SRR0 */ \ 281 stw %r31, (TLBSAVE_BOOKE_SRR1)(%r1); /* save SRR1 */ \ 282 isync; \ 283 mfsprg4 %r1 284 285/* 286 * restores LR, CR, SRR0-1, R20-31 from the TLBSAVE area 287 * 288 * same notes as for the TLB_PROLOG 289 */ 290#define TLB_RESTORE \ 291 mtsprg4 %r1; /* Save SP */ \ 292 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 293 /* calculate TLB nesting level and TLBSAVE instance addr */ \ 294 lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 295 subi %r28, %r28, 1; \ 296 stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 297 rlwinm %r29, %r28, 6, 24, 25; /* 4 x TLBSAVE_LEN */ \ 298 addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 299 add %r1, %r1, %r29; \ 300 \ 301 /* restore LR, CR */ \ 302 lwz %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 303 lwz %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 304 mtlr %r30; \ 305 mtcr %r31; \ 306 /* restore SRR0-1 */ \ 307 lwz %r30, (TLBSAVE_BOOKE_SRR0)(%r1); \ 308 lwz %r31, (TLBSAVE_BOOKE_SRR1)(%r1); \ 309 mtsrr0 %r30; \ 310 mtsrr1 %r31; \ 311 /* restore R20-31 */ \ 312 lmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \ 313 mfsprg4 %r1 314 315 316#define INTERRUPT(label) \ 317 .globl label; \ 318 .align 5; \ 319 CNAME(label): 320 321/* 322 * Interrupt handling routines in BookE can be flexibly placed and do not have 323 * to live in pre-defined vectors location. Note they need to be TLB-mapped at 324 * all times in order to be able to handle exceptions. We thus arrange for 325 * them to be part of kernel text which is always TLB-accessible. 326 * 327 * The interrupt handling routines have to be 16 bytes aligned: we align them 328 * to 32 bytes (cache line length) which supposedly performs better. 329 * 330 */ 331 .text 332 .globl CNAME(interrupt_vector_base) 333 .align 5 334interrupt_vector_base: 335 336/***************************************************************************** 337 * Critical input interrupt 338 ****************************************************************************/ 339INTERRUPT(int_critical_input) 340 STANDARD_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 341 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_CRIT) 342 addi %r3, %r1, 8 343 bl CNAME(powerpc_crit_interrupt) 344 FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 345 rfci 346 347 348/***************************************************************************** 349 * Machine check interrupt 350 ****************************************************************************/ 351INTERRUPT(int_machine_check) 352 STANDARD_PROLOG(SPR_SPRG3, PC_BOOKE_MCHKSAVE, SPR_MCSRR0, SPR_MCSRR1) 353 FRAME_SETUP(SPR_SPRG3, PC_BOOKE_MCHKSAVE, EXC_MCHK) 354 addi %r3, %r1, 8 355 bl CNAME(powerpc_mchk_interrupt) 356 FRAME_LEAVE(SPR_MCSRR0, SPR_MCSRR1) 357 rfmci 358 359 360/***************************************************************************** 361 * Data storage interrupt 362 ****************************************************************************/ 363INTERRUPT(int_data_storage) 364 STANDARD_PROLOG(SPR_SPRG1, PC_DISISAVE, SPR_SRR0, SPR_SRR1) 365 FRAME_SETUP(SPR_SPRG1, PC_DISISAVE, EXC_DSI) 366 b trap_common 367 368 369/***************************************************************************** 370 * Instruction storage interrupt 371 ****************************************************************************/ 372INTERRUPT(int_instr_storage) 373 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 374 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ISI) 375 b trap_common 376 377 378/***************************************************************************** 379 * External input interrupt 380 ****************************************************************************/ 381INTERRUPT(int_external_input) 382 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 383 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_EXI) 384 bl CNAME(powerpc_extr_interrupt) 385 b trapexit 386 387 388INTERRUPT(int_alignment) 389 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 390 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ALI) 391 b trap_common 392 393 394INTERRUPT(int_program) 395 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 396 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_PGM) 397 b trap_common 398 399 400/***************************************************************************** 401 * System call 402 ****************************************************************************/ 403INTERRUPT(int_syscall) 404 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 405 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_SC) 406 b trap_common 407 408 409/***************************************************************************** 410 * Decrementer interrupt 411 ****************************************************************************/ 412INTERRUPT(int_decrementer) 413 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 414 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_DECR) 415 addi %r3, %r1, 8 416 bl CNAME(powerpc_decr_interrupt) 417 b trapexit 418 419 420/***************************************************************************** 421 * Fixed interval timer 422 ****************************************************************************/ 423INTERRUPT(int_fixed_interval_timer) 424 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 425 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_FIT) 426 b trap_common 427 428 429/***************************************************************************** 430 * Watchdog interrupt 431 ****************************************************************************/ 432INTERRUPT(int_watchdog) 433 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 434 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_WDOG) 435 b trap_common 436 437 438/***************************************************************************** 439 * Data TLB miss interrupt 440 * 441 * There can be nested TLB misses - while handling a TLB miss we reference 442 * data structures that may be not covered by translations. We support up to 443 * TLB_NESTED_MAX-1 nested misses. 444 * 445 * Registers use: 446 * r31 - dear 447 * r30 - unused 448 * r29 - saved mas0 449 * r28 - saved mas1 450 * r27 - saved mas2 451 * r26 - pmap address 452 * r25 - pte address 453 * 454 * r20:r23 - scratch registers 455 ****************************************************************************/ 456INTERRUPT(int_data_tlb_error) 457 TLB_PROLOG 458 459 mfdear %r31 460 461 /* 462 * Save MAS0-MAS2 registers. There might be another tlb miss during 463 * pte lookup overwriting current contents (which was hw filled). 464 */ 465 mfspr %r29, SPR_MAS0 466 mfspr %r28, SPR_MAS1 467 mfspr %r27, SPR_MAS2 468 469 /* Check faulting address. */ 470 lis %r21, VM_MAXUSER_ADDRESS@h 471 ori %r21, %r21, VM_MAXUSER_ADDRESS@l 472 cmplw cr0, %r31, %r21 473 blt search_user_pmap 474 475 /* If it's kernel address, allow only supervisor mode misses. */ 476 mfsrr1 %r21 477 mtcr %r21 478 bt 17, search_failed /* check MSR[PR] */ 479 480search_kernel_pmap: 481 /* Load r26 with kernel_pmap address */ 482 lis %r26, kernel_pmap_store@h 483 ori %r26, %r26, kernel_pmap_store@l 484 485 /* Force kernel tid, set TID to 0 in MAS1. */ 486 li %r21, 0 487 rlwimi %r28, %r21, 0, 8, 15 /* clear TID bits */ 488 489tlb_miss_handle: 490 /* This may result in nested tlb miss. */ 491 bl pte_lookup /* returns PTE address in R25 */ 492 493 cmpwi %r25, 0 /* pte found? */ 494 beq search_failed 495 496 /* Finish up, write TLB entry. */ 497 bl tlb_fill_entry 498 499tlb_miss_return: 500 TLB_RESTORE 501 rfi 502 503search_user_pmap: 504 /* Load r26 with current user space process pmap */ 505 GET_CPUINFO(%r26) 506 lwz %r26, PC_CURPMAP(%r26) 507 508 b tlb_miss_handle 509 510search_failed: 511 /* 512 * Whenever we don't find a TLB mapping in PT, set a TLB0 entry with 513 * the faulting virtual address anyway, but put a fake RPN and no 514 * access rights. This should cause a following {D,I}SI exception. 515 */ 516 lis %r23, 0xffff0000@h /* revoke all permissions */ 517 518 /* Load MAS registers. */ 519 mtspr SPR_MAS0, %r29 520 isync 521 mtspr SPR_MAS1, %r28 522 isync 523 mtspr SPR_MAS2, %r27 524 isync 525 mtspr SPR_MAS3, %r23 526 isync 527 528 tlbwe 529 msync 530 isync 531 b tlb_miss_return 532 533/***************************************************************************** 534 * 535 * Return pte address that corresponds to given pmap/va. If there is no valid 536 * entry return 0. 537 * 538 * input: r26 - pmap 539 * input: r31 - dear 540 * output: r25 - pte address 541 * 542 * scratch regs used: r21 543 * 544 ****************************************************************************/ 545pte_lookup: 546 cmpwi %r26, 0 547 beq 1f /* fail quickly if pmap is invalid */ 548 549 srwi %r21, %r31, PDIR_SHIFT /* pdir offset */ 550 slwi %r21, %r21, PDIR_ENTRY_SHIFT /* multiply by pdir entry size */ 551 552 addi %r25, %r26, PM_PDIR /* pmap pm_dir[] address */ 553 add %r25, %r25, %r21 /* offset within pm_pdir[] table */ 554 /* 555 * Get ptbl address, i.e. pmap->pm_pdir[pdir_idx] 556 * This load may cause a Data TLB miss for non-kernel pmap! 557 */ 558 lwz %r25, 0(%r25) 559 cmpwi %r25, 0 560 beq 2f 561 562 lis %r21, PTBL_MASK@h 563 ori %r21, %r21, PTBL_MASK@l 564 and %r21, %r21, %r31 565 566 /* ptbl offset, multiply by ptbl entry size */ 567 srwi %r21, %r21, (PTBL_SHIFT - PTBL_ENTRY_SHIFT) 568 569 add %r25, %r25, %r21 /* address of pte entry */ 570 /* 571 * Get pte->flags 572 * This load may cause a Data TLB miss for non-kernel pmap! 573 */ 574 lwz %r21, PTE_FLAGS(%r25) 575 andis. %r21, %r21, PTE_VALID@h 576 bne 2f 5771: 578 li %r25, 0 5792: 580 blr 581 582/***************************************************************************** 583 * 584 * Load MAS1-MAS3 registers with data, write TLB entry 585 * 586 * input: 587 * r29 - mas0 588 * r28 - mas1 589 * r27 - mas2 590 * r25 - pte 591 * 592 * output: none 593 * 594 * scratch regs: r21-r23 595 * 596 ****************************************************************************/ 597tlb_fill_entry: 598 /* 599 * Update PTE flags: we have to do it atomically, as pmap_protect() 600 * running on other CPUs could attempt to update the flags at the same 601 * time. 602 */ 603 li %r23, PTE_FLAGS 6041: 605 lwarx %r21, %r23, %r25 /* get pte->flags */ 606 oris %r21, %r21, PTE_REFERENCED@h /* set referenced bit */ 607 608 andi. %r22, %r21, (PTE_UW | PTE_UW)@l /* check if writable */ 609 beq 2f 610 oris %r21, %r21, PTE_MODIFIED@h /* set modified bit */ 6112: 612 stwcx. %r21, %r23, %r25 /* write it back */ 613 bne- 1b 614 615 /* Update MAS2. */ 616 rlwimi %r27, %r21, 0, 27, 30 /* insert WIMG bits from pte */ 617 618 /* Setup MAS3 value in r23. */ 619 lwz %r23, PTE_RPN(%r25) /* get pte->rpn */ 620 621 rlwimi %r23, %r21, 24, 26, 31 /* insert protection bits from pte */ 622 623 /* Load MAS registers. */ 624 mtspr SPR_MAS0, %r29 625 isync 626 mtspr SPR_MAS1, %r28 627 isync 628 mtspr SPR_MAS2, %r27 629 isync 630 mtspr SPR_MAS3, %r23 631 isync 632 633 tlbwe 634 isync 635 msync 636 blr 637 638/***************************************************************************** 639 * Instruction TLB miss interrupt 640 * 641 * Same notes as for the Data TLB miss 642 ****************************************************************************/ 643INTERRUPT(int_inst_tlb_error) 644 TLB_PROLOG 645 646 mfsrr0 %r31 /* faulting address */ 647 648 /* 649 * Save MAS0-MAS2 registers. There might be another tlb miss during pte 650 * lookup overwriting current contents (which was hw filled). 651 */ 652 mfspr %r29, SPR_MAS0 653 mfspr %r28, SPR_MAS1 654 mfspr %r27, SPR_MAS2 655 656 mfsrr1 %r21 657 mtcr %r21 658 659 /* check MSR[PR] */ 660 bt 17, search_user_pmap 661 b search_kernel_pmap 662 663 664 .globl interrupt_vector_top 665interrupt_vector_top: 666 667/***************************************************************************** 668 * Debug interrupt 669 ****************************************************************************/ 670INTERRUPT(int_debug) 671 STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 672 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG) 673 lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r2); 674 lis %r4, interrupt_vector_base@ha 675 addi %r4, %r4, interrupt_vector_base@l 676 cmplw cr0, %r3, %r4 677 blt 1f 678 lis %r4, interrupt_vector_top@ha 679 addi %r4, %r4, interrupt_vector_top@l 680 cmplw cr0, %r3, %r4 681 bge 1f 682 /* Disable single-stepping for the interrupt handlers. */ 683 lwz %r3, FRAME_SRR1+8(%r1); 684 rlwinm %r3, %r3, 0, 23, 21 685 stw %r3, FRAME_SRR1+8(%r1); 686 /* Restore srr0 and srr1 as they could have been clobbered. */ 687 lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0+8)(%r2); 688 mtspr SPR_SRR0, %r3 689 lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r2); 690 mtspr SPR_SRR1, %r4 691 b 9f 6921: 693 addi %r3, %r1, 8 694 bl CNAME(trap) 695 /* 696 * Handle ASTs, needed for proper support of single-stepping. 697 * We actually need to return to the process with an rfi. 698 */ 699 b trapexit 7009: 701 FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 702 rfci 703 704 705/***************************************************************************** 706 * Common trap code 707 ****************************************************************************/ 708trap_common: 709 /* Call C trap dispatcher */ 710 addi %r3, %r1, 8 711 bl CNAME(trap) 712 713 .globl CNAME(trapexit) /* exported for db_backtrace use */ 714CNAME(trapexit): 715 /* disable interrupts */ 716 wrteei 0 717 718 /* Test AST pending - makes sense for user process only */ 719 lwz %r5, FRAME_SRR1+8(%r1) 720 mtcr %r5 721 bf 17, 1f 722 723 GET_CPUINFO(%r3) 724 lwz %r4, PC_CURTHREAD(%r3) 725 lwz %r4, TD_FLAGS(%r4) 726 lis %r5, (TDF_ASTPENDING | TDF_NEEDRESCHED)@h 727 ori %r5, %r5, (TDF_ASTPENDING | TDF_NEEDRESCHED)@l 728 and. %r4, %r4, %r5 729 beq 1f 730 731 /* re-enable interrupts before calling ast() */ 732 wrteei 1 733 734 addi %r3, %r1, 8 735 bl CNAME(ast) 736 .globl CNAME(asttrapexit) /* db_backtrace code sentinel #2 */ 737CNAME(asttrapexit): 738 b trapexit /* test ast ret value ? */ 7391: 740 FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 741 rfi 742 743 744#if defined(KDB) 745/* 746 * Deliberate entry to dbtrap 747 */ 748 .globl CNAME(breakpoint) 749CNAME(breakpoint): 750 mtsprg1 %r1 751 mfmsr %r3 752 mtsrr1 %r3 753 andi. %r3, %r3, ~(PSL_EE | PSL_ME)@l 754 mtmsr %r3 /* disable interrupts */ 755 isync 756 GET_CPUINFO(%r3) 757 stw %r30, (PC_DBSAVE+CPUSAVE_R30)(%r3) 758 stw %r31, (PC_DBSAVE+CPUSAVE_R31)(%r3) 759 760 mflr %r31 761 mtsrr0 %r31 762 763 mfdear %r30 764 mfesr %r31 765 stw %r30, (PC_DBSAVE+CPUSAVE_BOOKE_DEAR)(%r3) 766 stw %r31, (PC_DBSAVE+CPUSAVE_BOOKE_ESR)(%r3) 767 768 mfsrr0 %r30 769 mfsrr1 %r31 770 stw %r30, (PC_DBSAVE+CPUSAVE_SRR0)(%r3) 771 stw %r31, (PC_DBSAVE+CPUSAVE_SRR1)(%r3) 772 isync 773 774 mfcr %r30 775 776/* 777 * Now the kdb trap catching code. 778 */ 779dbtrap: 780 FRAME_SETUP(SPR_SPRG1, PC_DBSAVE, EXC_DEBUG) 781/* Call C trap code: */ 782 addi %r3, %r1, 8 783 bl CNAME(db_trap_glue) 784 or. %r3, %r3, %r3 785 bne dbleave 786/* This wasn't for KDB, so switch to real trap: */ 787 b trap_common 788 789dbleave: 790 FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 791 rfi 792#endif /* KDB */ 793