1/*- 2 * Copyright (C) 2006-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * Copyright (C) 2006 Juniper Networks, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31/*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * from: $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ 62 */ 63 64/* 65 * NOTICE: This is not a standalone file. to use it, #include it in 66 * your port's locore.S, like so: 67 * 68 * #include <powerpc/booke/trap_subr.S> 69 */ 70 71/* 72 * SPRG usage notes 73 * 74 * SPRG0 - pcpu pointer 75 * SPRG1 - all interrupts except TLB miss, critical, machine check 76 * SPRG2 - critical 77 * SPRG3 - machine check 78 * 79 */ 80 81/* Get the per-CPU data structure */ 82#define GET_CPUINFO(r) mfsprg0 r 83 84/* 85 * Standard interrupt prolog 86 * 87 * sprg_sp - SPRG{1-3} reg used to temporarily store the SP 88 * savearea - temp save area (pc_{tempsave, disisave, critsave, mchksave}) 89 * isrr0-1 - save restore registers with CPU state at interrupt time (may be 90 * SRR0-1, CSRR0-1, MCSRR0-1 91 * 92 * 1. saves in the given savearea: 93 * - R30-31 94 * - DEAR, ESR 95 * - xSRR0-1 96 * 97 * 2. saves CR -> R30 98 * 99 * 3. switches to kstack if needed 100 * 101 * 4. notes: 102 * - R31 can be used as scratch register until a new frame is layed on 103 * the stack with FRAME_SETUP 104 * 105 * - potential TLB miss: NO. Saveareas are always acessible via TLB1 106 * permanent entries, and within this prolog we do not dereference any 107 * locations potentially not in the TLB 108 */ 109#define STANDARD_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 110 mtspr sprg_sp, %r1; /* Save SP */ \ 111 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 112 stw %r30, (savearea+CPUSAVE_R30)(%r1); \ 113 stw %r31, (savearea+CPUSAVE_R31)(%r1); \ 114 mfdear %r30; \ 115 mfesr %r31; \ 116 stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 117 stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 118 mfspr %r30, isrr0; \ 119 mfspr %r31, isrr1; /* MSR at interrupt time */ \ 120 stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 121 stw %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 122 isync; \ 123 mfspr %r1, sprg_sp; /* Restore SP */ \ 124 mfcr %r30; /* Save CR */ \ 125 /* switch to per-thread kstack if intr taken in user mode */ \ 126 mtcr %r31; /* MSR at interrupt time */ \ 127 bf 17, 1f; \ 128 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 129 lwz %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 1301: 131 132#define STANDARD_CRIT_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 133 mtspr sprg_sp, %r1; /* Save SP */ \ 134 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 135 stw %r30, (savearea+CPUSAVE_R30)(%r1); \ 136 stw %r31, (savearea+CPUSAVE_R31)(%r1); \ 137 mfdear %r30; \ 138 mfesr %r31; \ 139 stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 140 stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 141 mfspr %r30, isrr0; \ 142 mfspr %r31, isrr1; /* MSR at interrupt time */ \ 143 stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 144 stw %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 145 mfspr %r30, SPR_SRR0; \ 146 mfspr %r31, SPR_SRR1; /* MSR at interrupt time */ \ 147 stw %r30, (savearea+CPUSAVE_SRR0+8)(%r1); \ 148 stw %r31, (savearea+CPUSAVE_SRR1+8)(%r1); \ 149 isync; \ 150 mfspr %r1, sprg_sp; /* Restore SP */ \ 151 mfcr %r30; /* Save CR */ \ 152 /* switch to per-thread kstack if intr taken in user mode */ \ 153 mtcr %r31; /* MSR at interrupt time */ \ 154 bf 17, 1f; \ 155 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 156 lwz %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 1571: 158 159/* 160 * FRAME_SETUP assumes: 161 * SPRG{1-3} SP at the time interrupt occured 162 * savearea r30-r31, DEAR, ESR, xSRR0-1 163 * r30 CR 164 * r31 scratch 165 * r1 kernel stack 166 * 167 * sprg_sp - SPRG reg containing SP at the time interrupt occured 168 * savearea - temp save 169 * exc - exception number (EXC_xxx) 170 * 171 * 1. sets a new frame 172 * 2. saves in the frame: 173 * - R0, R1 (SP at the time of interrupt), R2, LR, CR 174 * - R3-31 (R30-31 first restored from savearea) 175 * - XER, CTR, DEAR, ESR (from savearea), xSRR0-1 176 * 177 * Notes: 178 * - potential TLB miss: YES, since we make dereferences to kstack, which 179 * can happen not covered (we can have up to two DTLB misses if fortunate 180 * enough i.e. when kstack crosses page boundary and both pages are 181 * untranslated) 182 */ 183#define FRAME_SETUP(sprg_sp, savearea, exc) \ 184 mfspr %r31, sprg_sp; /* get saved SP */ \ 185 /* establish a new stack frame and put everything on it */ \ 186 stwu %r31, -FRAMELEN(%r1); \ 187 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 188 stw %r31, FRAME_1+8(%r1); /* save SP " " */ \ 189 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 190 mflr %r31; \ 191 stw %r31, FRAME_LR+8(%r1); /* save LR " " */ \ 192 stw %r30, FRAME_CR+8(%r1); /* save CR " " */ \ 193 GET_CPUINFO(%r2); \ 194 lwz %r30, (savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 195 lwz %r31, (savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 196 /* save R3-31 */ \ 197 stmw %r3, FRAME_3+8(%r1) ; \ 198 /* save DEAR, ESR */ \ 199 lwz %r28, (savearea+CPUSAVE_BOOKE_DEAR)(%r2); \ 200 lwz %r29, (savearea+CPUSAVE_BOOKE_ESR)(%r2); \ 201 stw %r28, FRAME_BOOKE_DEAR+8(%r1); \ 202 stw %r29, FRAME_BOOKE_ESR+8(%r1); \ 203 /* save XER, CTR, exc number */ \ 204 mfxer %r3; \ 205 mfctr %r4; \ 206 stw %r3, FRAME_XER+8(%r1); \ 207 stw %r4, FRAME_CTR+8(%r1); \ 208 li %r5, exc; \ 209 stw %r5, FRAME_EXC+8(%r1); \ 210 /* save DBCR0 */ \ 211 mfspr %r3, SPR_DBCR0; \ 212 stw %r3, FRAME_BOOKE_DBCR0+8(%r1); \ 213 /* save xSSR0-1 */ \ 214 lwz %r30, (savearea+CPUSAVE_SRR0)(%r2); \ 215 lwz %r31, (savearea+CPUSAVE_SRR1)(%r2); \ 216 stw %r30, FRAME_SRR0+8(%r1); \ 217 stw %r31, FRAME_SRR1+8(%r1) 218 219/* 220 * 221 * isrr0-1 - save restore registers to restore CPU state to (may be 222 * SRR0-1, CSRR0-1, MCSRR0-1 223 * 224 * Notes: 225 * - potential TLB miss: YES. The deref'd kstack may be not covered 226 */ 227#define FRAME_LEAVE(isrr0, isrr1) \ 228 /* restore CTR, XER, LR, CR */ \ 229 lwz %r4, FRAME_CTR+8(%r1); \ 230 lwz %r5, FRAME_XER+8(%r1); \ 231 lwz %r6, FRAME_LR+8(%r1); \ 232 lwz %r7, FRAME_CR+8(%r1); \ 233 mtctr %r4; \ 234 mtxer %r5; \ 235 mtlr %r6; \ 236 mtcr %r7; \ 237 /* restore DBCR0 */ \ 238 lwz %r4, FRAME_BOOKE_DBCR0+8(%r1); \ 239 mtspr SPR_DBCR0, %r4; \ 240 /* restore xSRR0-1 */ \ 241 lwz %r30, FRAME_SRR0+8(%r1); \ 242 lwz %r31, FRAME_SRR1+8(%r1); \ 243 mtspr isrr0, %r30; \ 244 mtspr isrr1, %r31; \ 245 /* restore R2-31, SP */ \ 246 lmw %r2, FRAME_2+8(%r1) ; \ 247 lwz %r0, FRAME_0+8(%r1); \ 248 lwz %r1, FRAME_1+8(%r1); \ 249 isync 250 251/* 252 * TLB miss prolog 253 * 254 * saves LR, CR, SRR0-1, R20-31 in the TLBSAVE area 255 * 256 * Notes: 257 * - potential TLB miss: NO. It is crucial that we do not generate a TLB 258 * miss within the TLB prolog itself! 259 * - TLBSAVE is always translated 260 */ 261#define TLB_PROLOG \ 262 mtsprg4 %r1; /* Save SP */ \ 263 mtsprg5 %r28; \ 264 mtsprg6 %r29; \ 265 /* calculate TLB nesting level and TLBSAVE instance address */ \ 266 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 267 lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 268 rlwinm %r29, %r28, 6, 24, 25; /* 4 x TLBSAVE_LEN */ \ 269 addi %r28, %r28, 1; \ 270 stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 271 addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 272 add %r1, %r1, %r29; /* current TLBSAVE ptr */ \ 273 \ 274 /* save R20-31 */ \ 275 mfsprg5 %r28; \ 276 mfsprg6 %r29; \ 277 stmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \ 278 /* save LR, CR */ \ 279 mflr %r30; \ 280 mfcr %r31; \ 281 stw %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 282 stw %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 283 /* save SRR0-1 */ \ 284 mfsrr0 %r30; /* execution addr at interrupt time */ \ 285 mfsrr1 %r31; /* MSR at interrupt time*/ \ 286 stw %r30, (TLBSAVE_BOOKE_SRR0)(%r1); /* save SRR0 */ \ 287 stw %r31, (TLBSAVE_BOOKE_SRR1)(%r1); /* save SRR1 */ \ 288 isync; \ 289 mfsprg4 %r1 290 291/* 292 * restores LR, CR, SRR0-1, R20-31 from the TLBSAVE area 293 * 294 * same notes as for the TLB_PROLOG 295 */ 296#define TLB_RESTORE \ 297 mtsprg4 %r1; /* Save SP */ \ 298 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 299 /* calculate TLB nesting level and TLBSAVE instance addr */ \ 300 lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 301 subi %r28, %r28, 1; \ 302 stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 303 rlwinm %r29, %r28, 6, 24, 25; /* 4 x TLBSAVE_LEN */ \ 304 addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 305 add %r1, %r1, %r29; \ 306 \ 307 /* restore LR, CR */ \ 308 lwz %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 309 lwz %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 310 mtlr %r30; \ 311 mtcr %r31; \ 312 /* restore SRR0-1 */ \ 313 lwz %r30, (TLBSAVE_BOOKE_SRR0)(%r1); \ 314 lwz %r31, (TLBSAVE_BOOKE_SRR1)(%r1); \ 315 mtsrr0 %r30; \ 316 mtsrr1 %r31; \ 317 /* restore R20-31 */ \ 318 lmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \ 319 mfsprg4 %r1 320 321 322#define INTERRUPT(label) \ 323 .globl label; \ 324 .align 5; \ 325 CNAME(label): 326 327/* 328 * Interrupt handling routines in BookE can be flexibly placed and do not have 329 * to live in pre-defined vectors location. Note they need to be TLB-mapped at 330 * all times in order to be able to handle exceptions. We thus arrange for 331 * them to be part of kernel text which is always TLB-accessible. 332 * 333 * The interrupt handling routines have to be 16 bytes aligned: we align them 334 * to 32 bytes (cache line length) which supposedly performs better. 335 * 336 */ 337 .text 338 .globl CNAME(interrupt_vector_base) 339 .align 5 340interrupt_vector_base: 341 342/***************************************************************************** 343 * Critical input interrupt 344 ****************************************************************************/ 345INTERRUPT(int_critical_input) 346 STANDARD_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 347 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_CRIT) 348 addi %r3, %r1, 8 349 bl CNAME(powerpc_crit_interrupt) 350 FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 351 rfci 352 353 354/***************************************************************************** 355 * Machine check interrupt 356 ****************************************************************************/ 357INTERRUPT(int_machine_check) 358 STANDARD_PROLOG(SPR_SPRG3, PC_BOOKE_MCHKSAVE, SPR_MCSRR0, SPR_MCSRR1) 359 FRAME_SETUP(SPR_SPRG3, PC_BOOKE_MCHKSAVE, EXC_MCHK) 360 addi %r3, %r1, 8 361 bl CNAME(powerpc_mchk_interrupt) 362 FRAME_LEAVE(SPR_MCSRR0, SPR_MCSRR1) 363 rfmci 364 365 366/***************************************************************************** 367 * Data storage interrupt 368 ****************************************************************************/ 369INTERRUPT(int_data_storage) 370 STANDARD_PROLOG(SPR_SPRG1, PC_DISISAVE, SPR_SRR0, SPR_SRR1) 371 FRAME_SETUP(SPR_SPRG1, PC_DISISAVE, EXC_DSI) 372 b trap_common 373 374 375/***************************************************************************** 376 * Instruction storage interrupt 377 ****************************************************************************/ 378INTERRUPT(int_instr_storage) 379 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 380 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ISI) 381 b trap_common 382 383 384/***************************************************************************** 385 * External input interrupt 386 ****************************************************************************/ 387INTERRUPT(int_external_input) 388 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 389 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_EXI) 390 bl CNAME(powerpc_extr_interrupt) 391 b trapexit 392 393 394INTERRUPT(int_alignment) 395 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 396 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ALI) 397 b trap_common 398 399 400INTERRUPT(int_program) 401 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 402 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_PGM) 403 b trap_common 404 405 406/***************************************************************************** 407 * System call 408 ****************************************************************************/ 409INTERRUPT(int_syscall) 410 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 411 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_SC) 412 b trap_common 413 414 415/***************************************************************************** 416 * Decrementer interrupt 417 ****************************************************************************/ 418INTERRUPT(int_decrementer) 419 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 420 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_DECR) 421 addi %r3, %r1, 8 422 bl CNAME(powerpc_decr_interrupt) 423 b trapexit 424 425 426/***************************************************************************** 427 * Fixed interval timer 428 ****************************************************************************/ 429INTERRUPT(int_fixed_interval_timer) 430 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 431 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_FIT) 432 b trap_common 433 434 435/***************************************************************************** 436 * Watchdog interrupt 437 ****************************************************************************/ 438INTERRUPT(int_watchdog) 439 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 440 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_WDOG) 441 b trap_common 442 443 444/***************************************************************************** 445 * Data TLB miss interrupt 446 * 447 * There can be nested TLB misses - while handling a TLB miss we reference 448 * data structures that may be not covered by translations. We support up to 449 * TLB_NESTED_MAX-1 nested misses. 450 * 451 * Registers use: 452 * r31 - dear 453 * r30 - unused 454 * r29 - saved mas0 455 * r28 - saved mas1 456 * r27 - saved mas2 457 * r26 - pmap address 458 * r25 - pte address 459 * 460 * r20:r23 - scratch registers 461 ****************************************************************************/ 462INTERRUPT(int_data_tlb_error) 463 TLB_PROLOG 464 465 mfdear %r31 466 467 /* 468 * Save MAS0-MAS2 registers. There might be another tlb miss during 469 * pte lookup overwriting current contents (which was hw filled). 470 */ 471 mfspr %r29, SPR_MAS0 472 mfspr %r28, SPR_MAS1 473 mfspr %r27, SPR_MAS2 474 475 /* Check faulting address. */ 476 lis %r21, VM_MAXUSER_ADDRESS@h 477 ori %r21, %r21, VM_MAXUSER_ADDRESS@l 478 cmplw cr0, %r31, %r21 479 blt search_user_pmap 480 481 /* If it's kernel address, allow only supervisor mode misses. */ 482 mfsrr1 %r21 483 mtcr %r21 484 bt 17, search_failed /* check MSR[PR] */ 485 486search_kernel_pmap: 487 /* Load r26 with kernel_pmap address */ 488 lis %r26, kernel_pmap_store@h 489 ori %r26, %r26, kernel_pmap_store@l 490 491 /* Force kernel tid, set TID to 0 in MAS1. */ 492 li %r21, 0 493 rlwimi %r28, %r21, 0, 8, 15 /* clear TID bits */ 494 495tlb_miss_handle: 496 /* This may result in nested tlb miss. */ 497 bl pte_lookup /* returns PTE address in R25 */ 498 499 cmpwi %r25, 0 /* pte found? */ 500 beq search_failed 501 502 /* Finish up, write TLB entry. */ 503 bl tlb_fill_entry 504 505tlb_miss_return: 506 TLB_RESTORE 507 rfi 508 509search_user_pmap: 510 /* Load r26 with current user space process pmap */ 511 GET_CPUINFO(%r26) 512 lwz %r26, PC_CURPMAP(%r26) 513 514 b tlb_miss_handle 515 516search_failed: 517 /* 518 * Whenever we don't find a TLB mapping in PT, set a TLB0 entry with 519 * the faulting virtual address anyway, but put a fake RPN and no 520 * access rights. This should cause a following {D,I}SI exception. 521 */ 522 lis %r23, 0xffff0000@h /* revoke all permissions */ 523 524 /* Load MAS registers. */ 525 mtspr SPR_MAS0, %r29 526 isync 527 mtspr SPR_MAS1, %r28 528 isync 529 mtspr SPR_MAS2, %r27 530 isync 531 mtspr SPR_MAS3, %r23 532 isync 533 534 tlbwe 535 msync 536 isync 537 b tlb_miss_return 538 539/***************************************************************************** 540 * 541 * Return pte address that corresponds to given pmap/va. If there is no valid 542 * entry return 0. 543 * 544 * input: r26 - pmap 545 * input: r31 - dear 546 * output: r25 - pte address 547 * 548 * scratch regs used: r21 549 * 550 ****************************************************************************/ 551pte_lookup: 552 cmpwi %r26, 0 553 beq 1f /* fail quickly if pmap is invalid */ 554 555 srwi %r21, %r31, PDIR_SHIFT /* pdir offset */ 556 slwi %r21, %r21, PDIR_ENTRY_SHIFT /* multiply by pdir entry size */ 557 558 addi %r25, %r26, PM_PDIR /* pmap pm_dir[] address */ 559 add %r25, %r25, %r21 /* offset within pm_pdir[] table */ 560 /* 561 * Get ptbl address, i.e. pmap->pm_pdir[pdir_idx] 562 * This load may cause a Data TLB miss for non-kernel pmap! 563 */ 564 lwz %r25, 0(%r25) 565 cmpwi %r25, 0 566 beq 2f 567 568 lis %r21, PTBL_MASK@h 569 ori %r21, %r21, PTBL_MASK@l 570 and %r21, %r21, %r31 571 572 /* ptbl offset, multiply by ptbl entry size */ 573 srwi %r21, %r21, (PTBL_SHIFT - PTBL_ENTRY_SHIFT) 574 575 add %r25, %r25, %r21 /* address of pte entry */ 576 /* 577 * Get pte->flags 578 * This load may cause a Data TLB miss for non-kernel pmap! 579 */ 580 lwz %r21, PTE_FLAGS(%r25) 581 andis. %r21, %r21, PTE_VALID@h 582 bne 2f 5831: 584 li %r25, 0 5852: 586 blr 587 588/***************************************************************************** 589 * 590 * Load MAS1-MAS3 registers with data, write TLB entry 591 * 592 * input: 593 * r29 - mas0 594 * r28 - mas1 595 * r27 - mas2 596 * r25 - pte 597 * 598 * output: none 599 * 600 * scratch regs: r21-r23 601 * 602 ****************************************************************************/ 603tlb_fill_entry: 604 /* 605 * Update PTE flags: we have to do it atomically, as pmap_protect() 606 * running on other CPUs could attempt to update the flags at the same 607 * time. 608 */ 609 li %r23, PTE_FLAGS 6101: 611 lwarx %r21, %r23, %r25 /* get pte->flags */ 612 oris %r21, %r21, PTE_REFERENCED@h /* set referenced bit */ 613 614 andi. %r22, %r21, (PTE_UW | PTE_UW)@l /* check if writable */ 615 beq 2f 616 oris %r21, %r21, PTE_MODIFIED@h /* set modified bit */ 6172: 618 stwcx. %r21, %r23, %r25 /* write it back */ 619 bne- 1b 620 621 /* Update MAS2. */ 622 rlwimi %r27, %r21, 0, 27, 30 /* insert WIMG bits from pte */ 623 624 /* Setup MAS3 value in r23. */ 625 lwz %r23, PTE_RPN(%r25) /* get pte->rpn */ 626 627 rlwimi %r23, %r21, 24, 26, 31 /* insert protection bits from pte */ 628 629 /* Load MAS registers. */ 630 mtspr SPR_MAS0, %r29 631 isync 632 mtspr SPR_MAS1, %r28 633 isync 634 mtspr SPR_MAS2, %r27 635 isync 636 mtspr SPR_MAS3, %r23 637 isync 638 639 tlbwe 640 isync 641 msync 642 blr 643 644/***************************************************************************** 645 * Instruction TLB miss interrupt 646 * 647 * Same notes as for the Data TLB miss 648 ****************************************************************************/ 649INTERRUPT(int_inst_tlb_error) 650 TLB_PROLOG 651 652 mfsrr0 %r31 /* faulting address */ 653 654 /* 655 * Save MAS0-MAS2 registers. There might be another tlb miss during pte 656 * lookup overwriting current contents (which was hw filled). 657 */ 658 mfspr %r29, SPR_MAS0 659 mfspr %r28, SPR_MAS1 660 mfspr %r27, SPR_MAS2 661 662 mfsrr1 %r21 663 mtcr %r21 664 665 /* check MSR[PR] */ 666 bt 17, search_user_pmap 667 b search_kernel_pmap 668 669 670 .globl interrupt_vector_top 671interrupt_vector_top: 672 673/***************************************************************************** 674 * Debug interrupt 675 ****************************************************************************/ 676INTERRUPT(int_debug) 677 STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 678 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG) 679 lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r2); 680 lis %r4, interrupt_vector_base@ha 681 addi %r4, %r4, interrupt_vector_base@l 682 cmplw cr0, %r3, %r4 683 blt 1f 684 lis %r4, interrupt_vector_top@ha 685 addi %r4, %r4, interrupt_vector_top@l 686 cmplw cr0, %r3, %r4 687 bge 1f 688 /* Disable single-stepping for the interrupt handlers. */ 689 lwz %r3, FRAME_SRR1+8(%r1); 690 rlwinm %r3, %r3, 0, 23, 21 691 stw %r3, FRAME_SRR1+8(%r1); 692 /* Restore srr0 and srr1 as they could have been clobbered. */ 693 lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0+8)(%r2); 694 mtspr SPR_SRR0, %r3 695 lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r2); 696 mtspr SPR_SRR1, %r4 697 b 9f 6981: 699 addi %r3, %r1, 8 700 bl CNAME(trap) 701 /* 702 * Handle ASTs, needed for proper support of single-stepping. 703 * We actually need to return to the process with an rfi. 704 */ 705 b trapexit 7069: 707 FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 708 rfci 709 710 711/***************************************************************************** 712 * Common trap code 713 ****************************************************************************/ 714trap_common: 715 /* Call C trap dispatcher */ 716 addi %r3, %r1, 8 717 bl CNAME(trap) 718 719 .globl CNAME(trapexit) /* exported for db_backtrace use */ 720CNAME(trapexit): 721 /* disable interrupts */ 722 wrteei 0 723 724 /* Test AST pending - makes sense for user process only */ 725 lwz %r5, FRAME_SRR1+8(%r1) 726 mtcr %r5 727 bf 17, 1f 728 729 GET_CPUINFO(%r3) 730 lwz %r4, PC_CURTHREAD(%r3) 731 lwz %r4, TD_FLAGS(%r4) 732 lis %r5, (TDF_ASTPENDING | TDF_NEEDRESCHED)@h 733 ori %r5, %r5, (TDF_ASTPENDING | TDF_NEEDRESCHED)@l 734 and. %r4, %r4, %r5 735 beq 1f 736 737 /* re-enable interrupts before calling ast() */ 738 wrteei 1 739 740 addi %r3, %r1, 8 741 bl CNAME(ast) 742 .globl CNAME(asttrapexit) /* db_backtrace code sentinel #2 */ 743CNAME(asttrapexit): 744 b trapexit /* test ast ret value ? */ 7451: 746 FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 747 rfi 748 749 750#if defined(KDB) 751/* 752 * Deliberate entry to dbtrap 753 */ 754 .globl CNAME(breakpoint) 755CNAME(breakpoint): 756 mtsprg1 %r1 757 mfmsr %r3 758 mtsrr1 %r3 759 andi. %r3, %r3, ~(PSL_EE | PSL_ME)@l 760 mtmsr %r3 /* disable interrupts */ 761 isync 762 GET_CPUINFO(%r3) 763 stw %r30, (PC_DBSAVE+CPUSAVE_R30)(%r3) 764 stw %r31, (PC_DBSAVE+CPUSAVE_R31)(%r3) 765 766 mflr %r31 767 mtsrr0 %r31 768 769 mfdear %r30 770 mfesr %r31 771 stw %r30, (PC_DBSAVE+CPUSAVE_BOOKE_DEAR)(%r3) 772 stw %r31, (PC_DBSAVE+CPUSAVE_BOOKE_ESR)(%r3) 773 774 mfsrr0 %r30 775 mfsrr1 %r31 776 stw %r30, (PC_DBSAVE+CPUSAVE_SRR0)(%r3) 777 stw %r31, (PC_DBSAVE+CPUSAVE_SRR1)(%r3) 778 isync 779 780 mfcr %r30 781 782/* 783 * Now the kdb trap catching code. 784 */ 785dbtrap: 786 FRAME_SETUP(SPR_SPRG1, PC_DBSAVE, EXC_DEBUG) 787/* Call C trap code: */ 788 addi %r3, %r1, 8 789 bl CNAME(db_trap_glue) 790 or. %r3, %r3, %r3 791 bne dbleave 792/* This wasn't for KDB, so switch to real trap: */ 793 b trap_common 794 795dbleave: 796 FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 797 rfi 798#endif /* KDB */ 799