1 /*- 2 * Copyright (C) 2007 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Some hw specific parts of this pmap were derived or influenced 29 * by NetBSD's ibm4xx pmap module. More generic code is shared with 30 * a few other pmap modules from the FreeBSD tree. 31 */ 32 33 /* 34 * VM layout notes: 35 * 36 * Kernel and user threads run within one common virtual address space 37 * defined by AS=0. 38 * 39 * Virtual address space layout: 40 * ----------------------------- 41 * 0x0000_0000 - 0xbfff_efff : user process 42 * 0xc000_0000 - 0xc1ff_ffff : kernel reserved 43 * 0xc000_0000 - kernelend : kernel code &data 44 * 0xc1ff_c000 - 0xc200_0000 : kstack0 45 * 0xc200_0000 - 0xffef_ffff : KVA 46 * 0xc200_0000 - 0xc200_3fff : reserved for page zero/copy 47 * 0xc200_4000 - ptbl buf end: reserved for ptbl bufs 48 * ptbl buf end- 0xffef_ffff : actual free KVA space 49 * 0xfff0_0000 - 0xffff_ffff : I/O devices region 50 */ 51 52 #include <sys/cdefs.h> 53 __FBSDID("$FreeBSD$"); 54 55 #include <sys/types.h> 56 #include <sys/param.h> 57 #include <sys/malloc.h> 58 #include <sys/proc.h> 59 #include <sys/user.h> 60 #include <sys/queue.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/msgbuf.h> 64 #include <sys/lock.h> 65 #include <sys/mutex.h> 66 #include <sys/vmmeter.h> 67 68 #include <vm/vm.h> 69 #include <vm/vm_page.h> 70 #include <vm/vm_kern.h> 71 #include <vm/vm_pageout.h> 72 #include <vm/vm_extern.h> 73 #include <vm/vm_object.h> 74 #include <vm/vm_param.h> 75 #include <vm/vm_map.h> 76 #include <vm/vm_pager.h> 77 #include <vm/uma.h> 78 79 #include <machine/cpu.h> 80 #include <machine/pcb.h> 81 #include <machine/powerpc.h> 82 83 #include <machine/tlb.h> 84 #include <machine/spr.h> 85 #include <machine/vmparam.h> 86 #include <machine/md_var.h> 87 #include <machine/mmuvar.h> 88 #include <machine/pmap.h> 89 #include <machine/pte.h> 90 91 #include "mmu_if.h" 92 93 #define DEBUG 94 #undef DEBUG 95 96 #ifdef DEBUG 97 #define debugf(fmt, args...) printf(fmt, ##args) 98 #else 99 #define debugf(fmt, args...) 100 #endif 101 102 #define TODO panic("%s: not implemented", __func__); 103 #define memmove(d, s, l) bcopy(s, d, l) 104 105 #include "opt_sched.h" 106 #ifndef SCHED_4BSD 107 #error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 108 #endif 109 extern struct mtx sched_lock; 110 111 /* Kernel physical load address. */ 112 extern uint32_t kernload; 113 114 struct mem_region availmem_regions[MEM_REGIONS]; 115 int availmem_regions_sz; 116 117 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 118 static vm_offset_t zero_page_va; 119 static struct mtx zero_page_mutex; 120 121 /* 122 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 123 * by idle thred only, no lock required. 124 */ 125 static vm_offset_t zero_page_idle_va; 126 127 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 128 static vm_offset_t copy_page_src_va; 129 static vm_offset_t copy_page_dst_va; 130 static struct mtx copy_page_mutex; 131 132 /**************************************************************************/ 133 /* PMAP */ 134 /**************************************************************************/ 135 136 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 137 vm_prot_t, boolean_t); 138 139 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 140 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 141 142 static int pagedaemon_waken; 143 144 /* 145 * If user pmap is processed with mmu_booke_remove and the resident count 146 * drops to 0, there are no more pages to remove, so we need not continue. 147 */ 148 #define PMAP_REMOVE_DONE(pmap) \ 149 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 150 151 extern void load_pid0(tlbtid_t); 152 153 /**************************************************************************/ 154 /* TLB and TID handling */ 155 /**************************************************************************/ 156 157 /* Translation ID busy table */ 158 static volatile pmap_t tidbusy[TID_MAX + 1]; 159 160 /* 161 * Actual maximum number of TLB0 entries. 162 * This number differs between e500 core revisions. 163 */ 164 u_int32_t tlb0_size; 165 u_int32_t tlb0_nways; 166 u_int32_t tlb0_nentries_per_way; 167 168 #define TLB0_SIZE (tlb0_size) 169 #define TLB0_NWAYS (tlb0_nways) 170 #define TLB0_ENTRIES_PER_WAY (tlb0_nentries_per_way) 171 172 /* Pointer to kernel tlb0 table, allocated in mmu_booke_bootstrap() */ 173 tlb_entry_t *tlb0; 174 175 /* 176 * Spinlock to assure proper locking between threads and 177 * between tlb miss handler and kernel. 178 */ 179 static struct mtx tlb0_mutex; 180 181 #define TLB1_SIZE 16 182 183 /* In-ram copy of the TLB1 */ 184 static tlb_entry_t tlb1[TLB1_SIZE]; 185 186 /* Next free entry in the TLB1 */ 187 static unsigned int tlb1_idx; 188 189 static tlbtid_t tid_alloc(struct pmap *); 190 static void tid_flush(tlbtid_t); 191 192 extern void tlb1_inval_va(vm_offset_t); 193 extern void tlb0_inval_va(vm_offset_t); 194 195 static void tlb_print_entry(int, u_int32_t, u_int32_t, u_int32_t, u_int32_t); 196 197 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, u_int32_t); 198 static void __tlb1_set_entry(unsigned int, vm_offset_t, vm_offset_t, 199 vm_size_t, u_int32_t, unsigned int, unsigned int); 200 static void tlb1_write_entry(unsigned int); 201 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 202 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 203 204 static vm_size_t tsize2size(unsigned int); 205 static unsigned int size2tsize(vm_size_t); 206 static unsigned int ilog2(unsigned int); 207 208 static void set_mas4_defaults(void); 209 210 static void tlb0_inval_entry(vm_offset_t, unsigned int); 211 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 212 static void tlb0_write_entry(unsigned int, unsigned int); 213 static void tlb0_flush_entry(pmap_t, vm_offset_t); 214 static void tlb0_init(void); 215 216 /**************************************************************************/ 217 /* Page table management */ 218 /**************************************************************************/ 219 220 /* Data for the pv entry allocation mechanism */ 221 static uma_zone_t pvzone; 222 static struct vm_object pvzone_obj; 223 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227 #ifndef PMAP_SHPGPERPROC 228 #define PMAP_SHPGPERPROC 200 229 #endif 230 231 static void ptbl_init(void); 232 static struct ptbl_buf *ptbl_buf_alloc(void); 233 static void ptbl_buf_free(struct ptbl_buf *); 234 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236 static void ptbl_alloc(mmu_t, pmap_t, unsigned int); 237 static void ptbl_free(mmu_t, pmap_t, unsigned int); 238 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243 void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, u_int32_t); 244 static int pte_remove(mmu_t, pmap_t, vm_offset_t, u_int8_t); 245 246 pv_entry_t pv_alloc(void); 247 static void pv_free(pv_entry_t); 248 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 249 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 250 251 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 252 #define PTBL_BUFS (128 * 16) 253 254 struct ptbl_buf { 255 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 256 vm_offset_t kva; /* va of mapping */ 257 }; 258 259 /* ptbl free list and a lock used for access synchronization. */ 260 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 261 static struct mtx ptbl_buf_freelist_lock; 262 263 /* Base address of kva space allocated fot ptbl bufs. */ 264 static vm_offset_t ptbl_buf_pool_vabase; 265 266 /* Pointer to ptbl_buf structures. */ 267 static struct ptbl_buf *ptbl_bufs; 268 269 /* 270 * Kernel MMU interface 271 */ 272 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 273 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 274 static void mmu_booke_clear_reference(mmu_t, vm_page_t); 275 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, vm_size_t, 276 vm_offset_t); 277 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 278 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 279 vm_prot_t, boolean_t); 280 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 281 vm_page_t, vm_prot_t); 282 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 283 vm_prot_t); 284 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 285 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 286 vm_prot_t); 287 static void mmu_booke_init(mmu_t); 288 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 289 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290 static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 291 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 292 int); 293 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t); 294 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 295 vm_object_t, vm_pindex_t, vm_size_t); 296 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297 static void mmu_booke_page_init(mmu_t, vm_page_t); 298 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 299 static void mmu_booke_pinit(mmu_t, pmap_t); 300 static void mmu_booke_pinit0(mmu_t, pmap_t); 301 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 302 vm_prot_t); 303 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 305 static void mmu_booke_release(mmu_t, pmap_t); 306 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307 static void mmu_booke_remove_all(mmu_t, vm_page_t); 308 static void mmu_booke_remove_write(mmu_t, vm_page_t); 309 static void mmu_booke_zero_page(mmu_t, vm_page_t); 310 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 311 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 312 static void mmu_booke_activate(mmu_t, struct thread *); 313 static void mmu_booke_deactivate(mmu_t, struct thread *); 314 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 315 static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 316 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 317 static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 318 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 319 static void mmu_booke_kremove(mmu_t, vm_offset_t); 320 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 321 static boolean_t mmu_booke_page_executable(mmu_t, vm_page_t); 322 323 static mmu_method_t mmu_booke_methods[] = { 324 /* pmap dispatcher interface */ 325 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 326 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 327 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 328 MMUMETHOD(mmu_copy, mmu_booke_copy), 329 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 330 MMUMETHOD(mmu_enter, mmu_booke_enter), 331 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 332 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 333 MMUMETHOD(mmu_extract, mmu_booke_extract), 334 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 335 MMUMETHOD(mmu_init, mmu_booke_init), 336 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 337 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 338 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 339 MMUMETHOD(mmu_map, mmu_booke_map), 340 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 341 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 342 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 343 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 344 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 345 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 346 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 347 MMUMETHOD(mmu_protect, mmu_booke_protect), 348 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 349 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 350 MMUMETHOD(mmu_release, mmu_booke_release), 351 MMUMETHOD(mmu_remove, mmu_booke_remove), 352 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 353 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 354 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 355 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 356 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 357 MMUMETHOD(mmu_activate, mmu_booke_activate), 358 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 359 360 /* Internal interfaces */ 361 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 362 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 363 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 364 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 365 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 366 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 367 MMUMETHOD(mmu_page_executable, mmu_booke_page_executable), 368 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 369 370 { 0, 0 } 371 }; 372 373 static mmu_def_t booke_mmu = { 374 MMU_TYPE_BOOKE, 375 mmu_booke_methods, 376 0 377 }; 378 MMU_DEF(booke_mmu); 379 380 /* Return number of entries in TLB0. */ 381 static __inline void 382 tlb0_get_tlbconf(void) 383 { 384 uint32_t tlb0_cfg; 385 386 tlb0_cfg = mfspr(SPR_TLB0CFG); 387 tlb0_size = tlb0_cfg & TLBCFG_NENTRY_MASK; 388 tlb0_nways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 389 tlb0_nentries_per_way = tlb0_size/tlb0_nways; 390 } 391 392 /* Initialize pool of kva ptbl buffers. */ 393 static void 394 ptbl_init(void) 395 { 396 int i; 397 398 //debugf("ptbl_init: s (ptbl_bufs = 0x%08x size 0x%08x)\n", 399 // (u_int32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 400 //debugf("ptbl_init: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)\n", 401 // ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 402 403 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 404 TAILQ_INIT(&ptbl_buf_freelist); 405 406 for (i = 0; i < PTBL_BUFS; i++) { 407 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 408 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 409 } 410 411 //debugf("ptbl_init: e\n"); 412 } 413 414 /* Get an sf_buf from the freelist. */ 415 static struct ptbl_buf * 416 ptbl_buf_alloc(void) 417 { 418 struct ptbl_buf *buf; 419 420 //debugf("ptbl_buf_alloc: s\n"); 421 422 mtx_lock(&ptbl_buf_freelist_lock); 423 buf = TAILQ_FIRST(&ptbl_buf_freelist); 424 if (buf != NULL) 425 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 426 mtx_unlock(&ptbl_buf_freelist_lock); 427 428 //debugf("ptbl_buf_alloc: e (buf = 0x%08x)\n", (u_int32_t)buf); 429 return (buf); 430 } 431 432 /* Return ptbl buff to free pool. */ 433 static void 434 ptbl_buf_free(struct ptbl_buf *buf) 435 { 436 437 //debugf("ptbl_buf_free: s (buf = 0x%08x)\n", (u_int32_t)buf); 438 439 mtx_lock(&ptbl_buf_freelist_lock); 440 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 441 mtx_unlock(&ptbl_buf_freelist_lock); 442 443 //debugf("ptbl_buf_free: e\n"); 444 } 445 446 /* 447 * Search the list of allocated ptbl bufs and find 448 * on list of allocated ptbls 449 */ 450 static void 451 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 452 { 453 struct ptbl_buf *pbuf; 454 455 //debugf("ptbl_free_pmap_ptbl: s (pmap = 0x%08x ptbl = 0x%08x)\n", 456 // (u_int32_t)pmap, (u_int32_t)ptbl); 457 458 TAILQ_FOREACH(pbuf, &pmap->ptbl_list, link) { 459 if (pbuf->kva == (vm_offset_t)ptbl) { 460 /* Remove from pmap ptbl buf list. */ 461 TAILQ_REMOVE(&pmap->ptbl_list, pbuf, link); 462 463 /* Free correspondig ptbl buf. */ 464 ptbl_buf_free(pbuf); 465 466 break; 467 } 468 } 469 470 //debugf("ptbl_free_pmap_ptbl: e\n"); 471 } 472 473 /* Allocate page table. */ 474 static void 475 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 476 { 477 vm_page_t mtbl[PTBL_PAGES]; 478 vm_page_t m; 479 struct ptbl_buf *pbuf; 480 unsigned int pidx; 481 int i; 482 483 //int su = (pmap == kernel_pmap); 484 //debugf("ptbl_alloc: s (pmap = 0x%08x su = %d pdir_idx = %d)\n", (u_int32_t)pmap, su, pdir_idx); 485 486 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 487 ("ptbl_alloc: invalid pdir_idx")); 488 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 489 ("pte_alloc: valid ptbl entry exists!")); 490 491 pbuf = ptbl_buf_alloc(); 492 if (pbuf == NULL) 493 panic("pte_alloc: couldn't alloc kernel virtual memory"); 494 pmap->pm_pdir[pdir_idx] = (pte_t *)pbuf->kva; 495 //debugf("ptbl_alloc: kva = 0x%08x\n", (u_int32_t)pmap->pm_pdir[pdir_idx]); 496 497 /* Allocate ptbl pages, this will sleep! */ 498 for (i = 0; i < PTBL_PAGES; i++) { 499 pidx = (PTBL_PAGES * pdir_idx) + i; 500 while ((m = vm_page_alloc(NULL, pidx, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 501 PMAP_UNLOCK(pmap); 502 vm_page_unlock_queues(); 503 VM_WAIT; 504 vm_page_lock_queues(); 505 PMAP_LOCK(pmap); 506 } 507 mtbl[i] = m; 508 } 509 510 /* Map in allocated pages into kernel_pmap. */ 511 mmu_booke_qenter(mmu, (vm_offset_t)pmap->pm_pdir[pdir_idx], mtbl, PTBL_PAGES); 512 513 /* Zero whole ptbl. */ 514 bzero((caddr_t)pmap->pm_pdir[pdir_idx], PTBL_PAGES * PAGE_SIZE); 515 516 /* Add pbuf to the pmap ptbl bufs list. */ 517 TAILQ_INSERT_TAIL(&pmap->ptbl_list, pbuf, link); 518 519 //debugf("ptbl_alloc: e\n"); 520 } 521 522 /* Free ptbl pages and invalidate pdir entry. */ 523 static void 524 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 525 { 526 pte_t *ptbl; 527 vm_paddr_t pa; 528 vm_offset_t va; 529 vm_page_t m; 530 int i; 531 532 //int su = (pmap == kernel_pmap); 533 //debugf("ptbl_free: s (pmap = 0x%08x su = %d pdir_idx = %d)\n", (u_int32_t)pmap, su, pdir_idx); 534 535 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 536 ("ptbl_free: invalid pdir_idx")); 537 538 ptbl = pmap->pm_pdir[pdir_idx]; 539 540 //debugf("ptbl_free: ptbl = 0x%08x\n", (u_int32_t)ptbl); 541 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 542 543 for (i = 0; i < PTBL_PAGES; i++) { 544 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 545 pa = pte_vatopa(mmu, kernel_pmap, va); 546 m = PHYS_TO_VM_PAGE(pa); 547 vm_page_free_zero(m); 548 atomic_subtract_int(&cnt.v_wire_count, 1); 549 mmu_booke_kremove(mmu, va); 550 } 551 552 ptbl_free_pmap_ptbl(pmap, ptbl); 553 pmap->pm_pdir[pdir_idx] = NULL; 554 555 //debugf("ptbl_free: e\n"); 556 } 557 558 /* 559 * Decrement ptbl pages hold count and attempt to free ptbl pages. 560 * Called when removing pte entry from ptbl. 561 * 562 * Return 1 if ptbl pages were freed. 563 */ 564 static int 565 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 566 { 567 pte_t *ptbl; 568 vm_paddr_t pa; 569 vm_page_t m; 570 int i; 571 572 //int su = (pmap == kernel_pmap); 573 //debugf("ptbl_unhold: s (pmap = %08x su = %d pdir_idx = %d)\n", 574 // (u_int32_t)pmap, su, pdir_idx); 575 576 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 577 ("ptbl_unhold: invalid pdir_idx")); 578 KASSERT((pmap != kernel_pmap), 579 ("ptbl_unhold: unholding kernel ptbl!")); 580 581 ptbl = pmap->pm_pdir[pdir_idx]; 582 583 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 584 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 585 ("ptbl_unhold: non kva ptbl")); 586 587 /* decrement hold count */ 588 for (i = 0; i < PTBL_PAGES; i++) { 589 pa = pte_vatopa(mmu, kernel_pmap, (vm_offset_t)ptbl + (i * PAGE_SIZE)); 590 m = PHYS_TO_VM_PAGE(pa); 591 m->wire_count--; 592 } 593 594 /* 595 * Free ptbl pages if there are no pte etries in this ptbl. 596 * wire_count has the same value for all ptbl pages, so check 597 * the last page. 598 */ 599 if (m->wire_count == 0) { 600 ptbl_free(mmu, pmap, pdir_idx); 601 602 //debugf("ptbl_unhold: e (freed ptbl)\n"); 603 return (1); 604 } 605 606 //debugf("ptbl_unhold: e\n"); 607 return (0); 608 } 609 610 /* 611 * Increment hold count for ptbl pages. This routine is used when 612 * new pte entry is being inserted into ptbl. 613 */ 614 static void 615 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 616 { 617 vm_paddr_t pa; 618 pte_t *ptbl; 619 vm_page_t m; 620 int i; 621 622 //debugf("ptbl_hold: s (pmap = 0x%08x pdir_idx = %d)\n", (u_int32_t)pmap, pdir_idx); 623 624 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 625 ("ptbl_hold: invalid pdir_idx")); 626 KASSERT((pmap != kernel_pmap), 627 ("ptbl_hold: holding kernel ptbl!")); 628 629 ptbl = pmap->pm_pdir[pdir_idx]; 630 631 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 632 633 for (i = 0; i < PTBL_PAGES; i++) { 634 pa = pte_vatopa(mmu, kernel_pmap, (vm_offset_t)ptbl + (i * PAGE_SIZE)); 635 m = PHYS_TO_VM_PAGE(pa); 636 m->wire_count++; 637 } 638 639 //debugf("ptbl_hold: e\n"); 640 } 641 642 /* Allocate pv_entry structure. */ 643 pv_entry_t 644 pv_alloc(void) 645 { 646 pv_entry_t pv; 647 648 debugf("pv_alloc: s\n"); 649 650 pv_entry_count++; 651 if ((pv_entry_count > pv_entry_high_water) && (pagedaemon_waken == 0)) { 652 pagedaemon_waken = 1; 653 wakeup (&vm_pages_needed); 654 } 655 pv = uma_zalloc(pvzone, M_NOWAIT); 656 657 debugf("pv_alloc: e\n"); 658 return (pv); 659 } 660 661 /* Free pv_entry structure. */ 662 static __inline void 663 pv_free(pv_entry_t pve) 664 { 665 //debugf("pv_free: s\n"); 666 667 pv_entry_count--; 668 uma_zfree(pvzone, pve); 669 670 //debugf("pv_free: e\n"); 671 } 672 673 674 /* Allocate and initialize pv_entry structure. */ 675 static void 676 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 677 { 678 pv_entry_t pve; 679 680 //int su = (pmap == kernel_pmap); 681 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 682 // (u_int32_t)pmap, va, (u_int32_t)m); 683 684 pve = pv_alloc(); 685 if (pve == NULL) 686 panic("pv_insert: no pv entries!"); 687 688 pve->pv_pmap = pmap; 689 pve->pv_va = va; 690 691 /* add to pv_list */ 692 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 693 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 694 695 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 696 697 //debugf("pv_insert: e\n"); 698 } 699 700 /* Destroy pv entry. */ 701 static void 702 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 703 { 704 pv_entry_t pve; 705 706 //int su = (pmap == kernel_pmap); 707 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 708 709 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 710 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 711 712 /* find pv entry */ 713 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 714 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 715 /* remove from pv_list */ 716 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 717 if (TAILQ_EMPTY(&m->md.pv_list)) 718 vm_page_flag_clear(m, PG_WRITEABLE); 719 720 /* free pv entry struct */ 721 pv_free(pve); 722 723 break; 724 } 725 } 726 727 //debugf("pv_remove: e\n"); 728 } 729 730 /* 731 * Clean pte entry, try to free page table page if requested. 732 * 733 * Return 1 if ptbl pages were freed, otherwise return 0. 734 */ 735 static int 736 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags) 737 { 738 unsigned int pdir_idx = PDIR_IDX(va); 739 unsigned int ptbl_idx = PTBL_IDX(va); 740 vm_page_t m; 741 pte_t *ptbl; 742 pte_t *pte; 743 744 //int su = (pmap == kernel_pmap); 745 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 746 // su, (u_int32_t)pmap, va, flags); 747 748 ptbl = pmap->pm_pdir[pdir_idx]; 749 KASSERT(ptbl, ("pte_remove: null ptbl")); 750 751 pte = &ptbl[ptbl_idx]; 752 753 if (pte == NULL || !PTE_ISVALID(pte)) 754 return (0); 755 756 /* Get vm_page_t for mapped pte. */ 757 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 758 759 if (PTE_ISWIRED(pte)) 760 pmap->pm_stats.wired_count--; 761 762 if (!PTE_ISFAKE(pte)) { 763 /* Handle managed entry. */ 764 if (PTE_ISMANAGED(pte)) { 765 766 /* Handle modified pages. */ 767 if (PTE_ISMODIFIED(pte)) 768 vm_page_dirty(m); 769 770 /* Referenced pages. */ 771 if (PTE_ISREFERENCED(pte)) 772 vm_page_flag_set(m, PG_REFERENCED); 773 774 /* Remove pv_entry from pv_list. */ 775 pv_remove(pmap, va, m); 776 } 777 } 778 779 pte->flags = 0; 780 pte->rpn = 0; 781 pmap->pm_stats.resident_count--; 782 783 if (flags & PTBL_UNHOLD) { 784 //debugf("pte_remove: e (unhold)\n"); 785 return (ptbl_unhold(mmu, pmap, pdir_idx)); 786 } 787 788 //debugf("pte_remove: e\n"); 789 return (0); 790 } 791 792 /* 793 * Insert PTE for a given page and virtual address. 794 */ 795 void 796 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, u_int32_t flags) 797 { 798 unsigned int pdir_idx = PDIR_IDX(va); 799 unsigned int ptbl_idx = PTBL_IDX(va); 800 pte_t *ptbl; 801 pte_t *pte; 802 803 //int su = (pmap == kernel_pmap); 804 //debugf("pte_enter: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 805 806 /* Get the page table pointer. */ 807 ptbl = pmap->pm_pdir[pdir_idx]; 808 809 if (ptbl) { 810 /* 811 * Check if there is valid mapping for requested 812 * va, if there is, remove it. 813 */ 814 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 815 if (PTE_ISVALID(pte)) { 816 pte_remove(mmu, pmap, va, PTBL_HOLD); 817 } else { 818 /* 819 * pte is not used, increment hold count 820 * for ptbl pages. 821 */ 822 if (pmap != kernel_pmap) 823 ptbl_hold(mmu, pmap, pdir_idx); 824 } 825 } else { 826 /* Allocate page table pages. */ 827 ptbl_alloc(mmu, pmap, pdir_idx); 828 } 829 830 /* Flush entry from TLB. */ 831 tlb0_flush_entry(pmap, va); 832 833 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 834 835 /* 836 * Insert pv_entry into pv_list for mapped page 837 * if part of managed memory. 838 */ 839 if ((m->flags & PG_FICTITIOUS) == 0) { 840 if ((m->flags & PG_UNMANAGED) == 0) { 841 pte->flags |= PTE_MANAGED; 842 843 /* Create and insert pv entry. */ 844 pv_insert(pmap, va, m); 845 } 846 } else { 847 pte->flags |= PTE_FAKE; 848 } 849 850 pmap->pm_stats.resident_count++; 851 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 852 pte->flags |= (PTE_VALID | flags); 853 854 //debugf("pte_enter: e\n"); 855 } 856 857 /* Return the pa for the given pmap/va. */ 858 static vm_paddr_t 859 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 860 { 861 vm_paddr_t pa = 0; 862 pte_t *pte; 863 864 pte = pte_find(mmu, pmap, va); 865 if ((pte != NULL) && PTE_ISVALID(pte)) 866 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 867 return (pa); 868 } 869 870 /* Get a pointer to a PTE in a page table. */ 871 static pte_t * 872 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 873 { 874 unsigned int pdir_idx = PDIR_IDX(va); 875 unsigned int ptbl_idx = PTBL_IDX(va); 876 877 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 878 879 if (pmap->pm_pdir[pdir_idx]) 880 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 881 882 return (NULL); 883 } 884 885 /**************************************************************************/ 886 /* PMAP related */ 887 /**************************************************************************/ 888 889 /* 890 * This is called during e500_init, before the system is really initialized. 891 */ 892 static void 893 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t kernelstart, vm_offset_t kernelend) 894 { 895 vm_offset_t phys_kernelend; 896 struct mem_region *mp, *mp1; 897 int cnt, i, j; 898 u_int s, e, sz; 899 u_int phys_avail_count; 900 vm_size_t physsz, hwphyssz; 901 vm_offset_t kernel_pdir; 902 903 debugf("mmu_booke_bootstrap: entered\n"); 904 905 /* Align kernel start and end address (kernel image). */ 906 kernelstart = trunc_page(kernelstart); 907 kernelend = round_page(kernelend); 908 909 /* Allocate space for the message buffer. */ 910 msgbufp = (struct msgbuf *)kernelend; 911 kernelend += MSGBUF_SIZE; 912 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (u_int32_t)msgbufp, 913 kernelend); 914 915 kernelend = round_page(kernelend); 916 917 /* Allocate space for tlb0 table. */ 918 tlb0_get_tlbconf(); /* Read TLB0 size and associativity. */ 919 tlb0 = (tlb_entry_t *)kernelend; 920 kernelend += sizeof(tlb_entry_t) * tlb0_size; 921 memset((void *)tlb0, 0, sizeof(tlb_entry_t) * tlb0_size); 922 debugf(" tlb0 at 0x%08x end = 0x%08x\n", (u_int32_t)tlb0, kernelend); 923 924 kernelend = round_page(kernelend); 925 926 /* Allocate space for ptbl_bufs. */ 927 ptbl_bufs = (struct ptbl_buf *)kernelend; 928 kernelend += sizeof(struct ptbl_buf) * PTBL_BUFS; 929 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 930 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (u_int32_t)ptbl_bufs, 931 kernelend); 932 933 kernelend = round_page(kernelend); 934 935 /* Allocate PTE tables for kernel KVA. */ 936 kernel_pdir = kernelend; 937 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 938 PDIR_SIZE - 1) / PDIR_SIZE; 939 kernelend += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 940 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 941 debugf(" kernel ptbls: %d\n", kernel_ptbls); 942 debugf(" kernel pdir at 0x%08x\n", kernel_pdir); 943 944 if (kernelend - kernelstart > 0x1000000) { 945 kernelend = (kernelend + 0x3fffff) & ~0x3fffff; 946 tlb1_mapin_region(kernelstart + 0x1000000, 947 kernload + 0x1000000, kernelend - kernelstart - 0x1000000); 948 } else 949 kernelend = (kernelend + 0xffffff) & ~0xffffff; 950 951 /*******************************************************/ 952 /* Set the start and end of kva. */ 953 /*******************************************************/ 954 virtual_avail = kernelend; 955 virtual_end = VM_MAX_KERNEL_ADDRESS; 956 957 /* Allocate KVA space for page zero/copy operations. */ 958 zero_page_va = virtual_avail; 959 virtual_avail += PAGE_SIZE; 960 zero_page_idle_va = virtual_avail; 961 virtual_avail += PAGE_SIZE; 962 copy_page_src_va = virtual_avail; 963 virtual_avail += PAGE_SIZE; 964 copy_page_dst_va = virtual_avail; 965 virtual_avail += PAGE_SIZE; 966 967 /* Initialize page zero/copy mutexes. */ 968 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 969 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 970 971 /* Initialize tlb0 table mutex. */ 972 mtx_init(&tlb0_mutex, "tlb0", NULL, MTX_SPIN | MTX_RECURSE); 973 974 /* Allocate KVA space for ptbl bufs. */ 975 ptbl_buf_pool_vabase = virtual_avail; 976 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 977 978 debugf("ptbl_buf_pool_vabase = 0x%08x\n", ptbl_buf_pool_vabase); 979 debugf("virtual_avail = %08x\n", virtual_avail); 980 debugf("virtual_end = %08x\n", virtual_end); 981 982 /* Calculate corresponding physical addresses for the kernel region. */ 983 phys_kernelend = kernload + (kernelend - kernelstart); 984 985 debugf("kernel image and allocated data:\n"); 986 debugf(" kernload = 0x%08x\n", kernload); 987 debugf(" kernelstart = 0x%08x\n", kernelstart); 988 debugf(" kernelend = 0x%08x\n", kernelend); 989 debugf(" kernel size = 0x%08x\n", kernelend - kernelstart); 990 991 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 992 panic("mmu_booke_bootstrap: phys_avail too small"); 993 994 /* 995 * Removed kernel physical address range from avail 996 * regions list. Page align all regions. 997 * Non-page aligned memory isn't very interesting to us. 998 * Also, sort the entries for ascending addresses. 999 */ 1000 sz = 0; 1001 cnt = availmem_regions_sz; 1002 debugf("processing avail regions:\n"); 1003 for (mp = availmem_regions; mp->mr_size; mp++) { 1004 s = mp->mr_start; 1005 e = mp->mr_start + mp->mr_size; 1006 debugf(" %08x-%08x -> ", s, e); 1007 /* Check whether this region holds all of the kernel. */ 1008 if (s < kernload && e > phys_kernelend) { 1009 availmem_regions[cnt].mr_start = phys_kernelend; 1010 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1011 e = kernload; 1012 } 1013 /* Look whether this regions starts within the kernel. */ 1014 if (s >= kernload && s < phys_kernelend) { 1015 if (e <= phys_kernelend) 1016 goto empty; 1017 s = phys_kernelend; 1018 } 1019 /* Now look whether this region ends within the kernel. */ 1020 if (e > kernload && e <= phys_kernelend) { 1021 if (s >= kernload) 1022 goto empty; 1023 e = kernload; 1024 } 1025 /* Now page align the start and size of the region. */ 1026 s = round_page(s); 1027 e = trunc_page(e); 1028 if (e < s) 1029 e = s; 1030 sz = e - s; 1031 debugf("%08x-%08x = %x\n", s, e, sz); 1032 1033 /* Check whether some memory is left here. */ 1034 if (sz == 0) { 1035 empty: 1036 memmove(mp, mp + 1, 1037 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1038 cnt--; 1039 mp--; 1040 continue; 1041 } 1042 1043 /* Do an insertion sort. */ 1044 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1045 if (s < mp1->mr_start) 1046 break; 1047 if (mp1 < mp) { 1048 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1049 mp1->mr_start = s; 1050 mp1->mr_size = sz; 1051 } else { 1052 mp->mr_start = s; 1053 mp->mr_size = sz; 1054 } 1055 } 1056 availmem_regions_sz = cnt; 1057 1058 /*******************************************************/ 1059 /* Fill in phys_avail table, based on availmem_regions */ 1060 /*******************************************************/ 1061 phys_avail_count = 0; 1062 physsz = 0; 1063 hwphyssz = 0; 1064 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1065 1066 debugf("fill in phys_avail:\n"); 1067 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1068 1069 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1070 availmem_regions[i].mr_start, 1071 availmem_regions[i].mr_start + availmem_regions[i].mr_size, 1072 availmem_regions[i].mr_size); 1073 1074 if (hwphyssz != 0 && (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1075 debugf(" hw.physmem adjust\n"); 1076 if (physsz < hwphyssz) { 1077 phys_avail[j] = availmem_regions[i].mr_start; 1078 phys_avail[j + 1] = availmem_regions[i].mr_start + 1079 hwphyssz - physsz; 1080 physsz = hwphyssz; 1081 phys_avail_count++; 1082 } 1083 break; 1084 } 1085 1086 phys_avail[j] = availmem_regions[i].mr_start; 1087 phys_avail[j + 1] = availmem_regions[i].mr_start + 1088 availmem_regions[i].mr_size; 1089 phys_avail_count++; 1090 physsz += availmem_regions[i].mr_size; 1091 } 1092 physmem = btoc(physsz); 1093 1094 /* Calculate the last available physical address. */ 1095 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1096 ; 1097 Maxmem = powerpc_btop(phys_avail[i + 1]); 1098 1099 debugf("Maxmem = 0x%08lx\n", Maxmem); 1100 debugf("phys_avail_count = %d\n", phys_avail_count); 1101 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, physmem); 1102 1103 /*******************************************************/ 1104 /* Initialize (statically allocated) kernel pmap. */ 1105 /*******************************************************/ 1106 PMAP_LOCK_INIT(kernel_pmap); 1107 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1108 1109 debugf("kernel_pmap = 0x%08x\n", (u_int32_t)kernel_pmap); 1110 debugf("kptbl_min = %d, kernel_kptbls = %d\n", kptbl_min, kernel_ptbls); 1111 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1112 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1113 1114 /* Initialize kernel pdir */ 1115 for (i = 0; i < kernel_ptbls; i++) 1116 kernel_pmap->pm_pdir[kptbl_min + i] = 1117 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1118 1119 kernel_pmap->pm_tid = KERNEL_TID; 1120 kernel_pmap->pm_active = ~0; 1121 1122 /* Initialize tidbusy with kenel_pmap entry. */ 1123 tidbusy[0] = kernel_pmap; 1124 1125 /*******************************************************/ 1126 /* Final setup */ 1127 /*******************************************************/ 1128 /* Initialize TLB0 handling. */ 1129 tlb0_init(); 1130 1131 debugf("mmu_booke_bootstrap: exit\n"); 1132 } 1133 1134 /* 1135 * Get the physical page address for the given pmap/virtual address. 1136 */ 1137 static vm_paddr_t 1138 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1139 { 1140 vm_paddr_t pa; 1141 1142 PMAP_LOCK(pmap); 1143 pa = pte_vatopa(mmu, pmap, va); 1144 PMAP_UNLOCK(pmap); 1145 1146 return (pa); 1147 } 1148 1149 /* 1150 * Extract the physical page address associated with the given 1151 * kernel virtual address. 1152 */ 1153 static vm_paddr_t 1154 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1155 { 1156 1157 return (pte_vatopa(mmu, kernel_pmap, va)); 1158 } 1159 1160 /* 1161 * Initialize the pmap module. 1162 * Called by vm_init, to initialize any structures that the pmap 1163 * system needs to map virtual memory. 1164 */ 1165 static void 1166 mmu_booke_init(mmu_t mmu) 1167 { 1168 int shpgperproc = PMAP_SHPGPERPROC; 1169 1170 //debugf("mmu_booke_init: s\n"); 1171 1172 /* 1173 * Initialize the address space (zone) for the pv entries. Set a 1174 * high water mark so that the system can recover from excessive 1175 * numbers of pv entries. 1176 */ 1177 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1178 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1179 1180 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1181 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1182 1183 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1184 pv_entry_high_water = 9 * (pv_entry_max / 10); 1185 1186 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1187 1188 /* Pre-fill pvzone with initial number of pv entries. */ 1189 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1190 1191 /* Initialize ptbl allocation. */ 1192 ptbl_init(); 1193 1194 //debugf("mmu_booke_init: e\n"); 1195 } 1196 1197 /* 1198 * Map a list of wired pages into kernel virtual address space. This is 1199 * intended for temporary mappings which do not need page modification or 1200 * references recorded. Existing mappings in the region are overwritten. 1201 */ 1202 static void 1203 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1204 { 1205 vm_offset_t va; 1206 1207 //debugf("mmu_booke_qenter: s (sva = 0x%08x count = %d)\n", sva, count); 1208 1209 va = sva; 1210 while (count-- > 0) { 1211 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1212 va += PAGE_SIZE; 1213 m++; 1214 } 1215 1216 //debugf("mmu_booke_qenter: e\n"); 1217 } 1218 1219 /* 1220 * Remove page mappings from kernel virtual address space. Intended for 1221 * temporary mappings entered by mmu_booke_qenter. 1222 */ 1223 static void 1224 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1225 { 1226 vm_offset_t va; 1227 1228 //debugf("mmu_booke_qremove: s (sva = 0x%08x count = %d)\n", sva, count); 1229 1230 va = sva; 1231 while (count-- > 0) { 1232 mmu_booke_kremove(mmu, va); 1233 va += PAGE_SIZE; 1234 } 1235 1236 //debugf("mmu_booke_qremove: e\n"); 1237 } 1238 1239 /* 1240 * Map a wired page into kernel virtual address space. 1241 */ 1242 static void 1243 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1244 { 1245 unsigned int pdir_idx = PDIR_IDX(va); 1246 unsigned int ptbl_idx = PTBL_IDX(va); 1247 u_int32_t flags; 1248 pte_t *pte; 1249 1250 //debugf("mmu_booke_kenter: s (pdir_idx = %d ptbl_idx = %d va=0x%08x pa=0x%08x)\n", 1251 // pdir_idx, ptbl_idx, va, pa); 1252 1253 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)), 1254 ("mmu_booke_kenter: invalid va")); 1255 1256 #if 0 1257 /* assume IO mapping, set I, G bits */ 1258 flags = (PTE_G | PTE_I | PTE_FAKE); 1259 1260 /* if mapping is within system memory, do not set I, G bits */ 1261 for (i = 0; i < totalmem_regions_sz; i++) { 1262 if ((pa >= totalmem_regions[i].mr_start) && 1263 (pa < (totalmem_regions[i].mr_start + 1264 totalmem_regions[i].mr_size))) { 1265 flags &= ~(PTE_I | PTE_G | PTE_FAKE); 1266 break; 1267 } 1268 } 1269 #else 1270 flags = 0; 1271 #endif 1272 1273 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1274 1275 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1276 1277 if (PTE_ISVALID(pte)) { 1278 //debugf("mmu_booke_kenter: replacing entry!\n"); 1279 1280 /* Flush entry from TLB0 */ 1281 tlb0_flush_entry(kernel_pmap, va); 1282 } 1283 1284 pte->rpn = pa & ~PTE_PA_MASK; 1285 pte->flags = flags; 1286 1287 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1288 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1289 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1290 1291 /* Flush the real memory from the instruction cache. */ 1292 if ((flags & (PTE_I | PTE_G)) == 0) { 1293 __syncicache((void *)va, PAGE_SIZE); 1294 } 1295 1296 //debugf("mmu_booke_kenter: e\n"); 1297 } 1298 1299 /* 1300 * Remove a page from kernel page table. 1301 */ 1302 static void 1303 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1304 { 1305 unsigned int pdir_idx = PDIR_IDX(va); 1306 unsigned int ptbl_idx = PTBL_IDX(va); 1307 pte_t *pte; 1308 1309 //debugf("mmu_booke_kremove: s (va = 0x%08x)\n", va); 1310 1311 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)), 1312 ("mmu_booke_kremove: invalid va")); 1313 1314 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1315 1316 if (!PTE_ISVALID(pte)) { 1317 //debugf("mmu_booke_kremove: e (invalid pte)\n"); 1318 return; 1319 } 1320 1321 /* Invalidate entry in TLB0. */ 1322 tlb0_flush_entry(kernel_pmap, va); 1323 1324 pte->flags = 0; 1325 pte->rpn = 0; 1326 1327 //debugf("mmu_booke_kremove: e\n"); 1328 } 1329 1330 /* 1331 * Initialize pmap associated with process 0. 1332 */ 1333 static void 1334 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1335 { 1336 //debugf("mmu_booke_pinit0: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 1337 mmu_booke_pinit(mmu, pmap); 1338 PCPU_SET(curpmap, pmap); 1339 //debugf("mmu_booke_pinit0: e\n"); 1340 } 1341 1342 /* 1343 * Initialize a preallocated and zeroed pmap structure, 1344 * such as one in a vmspace structure. 1345 */ 1346 static void 1347 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1348 { 1349 1350 //struct thread *td; 1351 //struct proc *p; 1352 1353 //td = PCPU_GET(curthread); 1354 //p = td->td_proc; 1355 //debugf("mmu_booke_pinit: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 1356 //printf("mmu_booke_pinit: proc %d '%s'\n", p->p_pid, p->p_comm); 1357 1358 KASSERT((pmap != kernel_pmap), ("mmu_booke_pinit: initializing kernel_pmap")); 1359 1360 PMAP_LOCK_INIT(pmap); 1361 pmap->pm_tid = 0; 1362 pmap->pm_active = 0; 1363 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1364 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1365 1366 TAILQ_INIT(&pmap->ptbl_list); 1367 1368 //debugf("mmu_booke_pinit: e\n"); 1369 } 1370 1371 /* 1372 * Release any resources held by the given physical map. 1373 * Called when a pmap initialized by mmu_booke_pinit is being released. 1374 * Should only be called if the map contains no valid mappings. 1375 */ 1376 static void 1377 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1378 { 1379 1380 //debugf("mmu_booke_release: s\n"); 1381 1382 PMAP_LOCK_DESTROY(pmap); 1383 1384 //debugf("mmu_booke_release: e\n"); 1385 } 1386 1387 #if 0 1388 /* Not needed, kernel page tables are statically allocated. */ 1389 void 1390 mmu_booke_growkernel(vm_offset_t maxkvaddr) 1391 { 1392 } 1393 #endif 1394 1395 /* 1396 * Insert the given physical page at the specified virtual address in the 1397 * target physical map with the protection requested. If specified the page 1398 * will be wired down. 1399 */ 1400 static void 1401 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1402 vm_prot_t prot, boolean_t wired) 1403 { 1404 vm_page_lock_queues(); 1405 PMAP_LOCK(pmap); 1406 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1407 vm_page_unlock_queues(); 1408 PMAP_UNLOCK(pmap); 1409 } 1410 1411 static void 1412 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1413 vm_prot_t prot, boolean_t wired) 1414 { 1415 pte_t *pte; 1416 vm_paddr_t pa; 1417 u_int32_t flags; 1418 int su, sync; 1419 1420 pa = VM_PAGE_TO_PHYS(m); 1421 su = (pmap == kernel_pmap); 1422 sync = 0; 1423 1424 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1425 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1426 // (u_int32_t)pmap, su, pmap->pm_tid, 1427 // (u_int32_t)m, va, pa, prot, wired); 1428 1429 if (su) { 1430 KASSERT(((va >= virtual_avail) && (va <= VM_MAX_KERNEL_ADDRESS)), 1431 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1432 } else { 1433 KASSERT((va <= VM_MAXUSER_ADDRESS), 1434 ("mmu_booke_enter_locked: user pmap, non user va")); 1435 } 1436 1437 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1438 1439 /* 1440 * If there is an existing mapping, and the physical address has not 1441 * changed, must be protection or wiring change. 1442 */ 1443 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1444 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1445 1446 //debugf("mmu_booke_enter_locked: update\n"); 1447 1448 /* Wiring change, just update stats. */ 1449 if (wired) { 1450 if (!PTE_ISWIRED(pte)) { 1451 pte->flags |= PTE_WIRED; 1452 pmap->pm_stats.wired_count++; 1453 } 1454 } else { 1455 if (PTE_ISWIRED(pte)) { 1456 pte->flags &= ~PTE_WIRED; 1457 pmap->pm_stats.wired_count--; 1458 } 1459 } 1460 1461 /* Save the old bits and clear the ones we're interested in. */ 1462 flags = pte->flags; 1463 pte->flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1464 1465 if (prot & VM_PROT_WRITE) { 1466 /* Add write permissions. */ 1467 pte->flags |= PTE_SW; 1468 if (!su) 1469 pte->flags |= PTE_UW; 1470 } else { 1471 /* Handle modified pages, sense modify status. */ 1472 if (PTE_ISMODIFIED(pte)) 1473 vm_page_dirty(m); 1474 } 1475 1476 /* If we're turning on execute permissions, flush the icache. */ 1477 if (prot & VM_PROT_EXECUTE) { 1478 pte->flags |= PTE_SX; 1479 if (!su) 1480 pte->flags |= PTE_UX; 1481 1482 if ((flags & (PTE_UX | PTE_SX)) == 0) 1483 sync++; 1484 } 1485 1486 /* Flush the old mapping from TLB0. */ 1487 pte->flags &= ~PTE_REFERENCED; 1488 tlb0_flush_entry(pmap, va); 1489 } else { 1490 /* 1491 * If there is an existing mapping, but its for a different 1492 * physical address, pte_enter() will delete the old mapping. 1493 */ 1494 //if ((pte != NULL) && PTE_ISVALID(pte)) 1495 // debugf("mmu_booke_enter_locked: replace\n"); 1496 //else 1497 // debugf("mmu_booke_enter_locked: new\n"); 1498 1499 /* Now set up the flags and install the new mapping. */ 1500 flags = (PTE_SR | PTE_VALID); 1501 1502 if (!su) 1503 flags |= PTE_UR; 1504 1505 if (prot & VM_PROT_WRITE) { 1506 flags |= PTE_SW; 1507 if (!su) 1508 flags |= PTE_UW; 1509 } 1510 1511 if (prot & VM_PROT_EXECUTE) { 1512 flags |= PTE_SX; 1513 if (!su) 1514 flags |= PTE_UX; 1515 } 1516 1517 /* If its wired update stats. */ 1518 if (wired) { 1519 pmap->pm_stats.wired_count++; 1520 flags |= PTE_WIRED; 1521 } 1522 1523 pte_enter(mmu, pmap, m, va, flags); 1524 1525 /* Flush the real memory from the instruction cache. */ 1526 if (prot & VM_PROT_EXECUTE) 1527 sync++; 1528 } 1529 1530 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1531 __syncicache((void *)va, PAGE_SIZE); 1532 sync = 0; 1533 } 1534 1535 if (sync) { 1536 /* Create a temporary mapping. */ 1537 pmap = PCPU_GET(curpmap); 1538 1539 va = 0; 1540 pte = pte_find(mmu, pmap, va); 1541 KASSERT(pte == NULL, ("%s:%d", __func__, __LINE__)); 1542 1543 flags = PTE_SR | PTE_VALID | PTE_UR; 1544 pte_enter(mmu, pmap, m, va, flags); 1545 __syncicache((void *)va, PAGE_SIZE); 1546 pte_remove(mmu, pmap, va, PTBL_UNHOLD); 1547 } 1548 1549 //debugf("mmu_booke_enter_locked: e\n"); 1550 } 1551 1552 /* 1553 * Maps a sequence of resident pages belonging to the same object. 1554 * The sequence begins with the given page m_start. This page is 1555 * mapped at the given virtual address start. Each subsequent page is 1556 * mapped at a virtual address that is offset from start by the same 1557 * amount as the page is offset from m_start within the object. The 1558 * last page in the sequence is the page with the largest offset from 1559 * m_start that can be mapped at a virtual address less than the given 1560 * virtual address end. Not every virtual page between start and end 1561 * is mapped; only those for which a resident page exists with the 1562 * corresponding offset from m_start are mapped. 1563 */ 1564 static void 1565 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1566 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1567 { 1568 vm_page_t m; 1569 vm_pindex_t diff, psize; 1570 1571 psize = atop(end - start); 1572 m = m_start; 1573 PMAP_LOCK(pmap); 1574 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1575 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, prot & 1576 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1577 m = TAILQ_NEXT(m, listq); 1578 } 1579 PMAP_UNLOCK(pmap); 1580 } 1581 1582 static void 1583 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1584 vm_prot_t prot) 1585 { 1586 1587 //debugf("mmu_booke_enter_quick: s\n"); 1588 1589 PMAP_LOCK(pmap); 1590 mmu_booke_enter_locked(mmu, pmap, va, m, 1591 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1592 PMAP_UNLOCK(pmap); 1593 1594 //debugf("mmu_booke_enter_quick e\n"); 1595 } 1596 1597 /* 1598 * Remove the given range of addresses from the specified map. 1599 * 1600 * It is assumed that the start and end are properly rounded to the page size. 1601 */ 1602 static void 1603 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1604 { 1605 pte_t *pte; 1606 u_int8_t hold_flag; 1607 1608 int su = (pmap == kernel_pmap); 1609 1610 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1611 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1612 1613 if (su) { 1614 KASSERT(((va >= virtual_avail) && (va <= VM_MAX_KERNEL_ADDRESS)), 1615 ("mmu_booke_enter: kernel pmap, non kernel va")); 1616 } else { 1617 KASSERT((va <= VM_MAXUSER_ADDRESS), 1618 ("mmu_booke_enter: user pmap, non user va")); 1619 } 1620 1621 if (PMAP_REMOVE_DONE(pmap)) { 1622 //debugf("mmu_booke_remove: e (empty)\n"); 1623 return; 1624 } 1625 1626 hold_flag = PTBL_HOLD_FLAG(pmap); 1627 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1628 1629 vm_page_lock_queues(); 1630 PMAP_LOCK(pmap); 1631 for (; va < endva; va += PAGE_SIZE) { 1632 pte = pte_find(mmu, pmap, va); 1633 if ((pte != NULL) && PTE_ISVALID(pte)) { 1634 pte_remove(mmu, pmap, va, hold_flag); 1635 1636 /* Flush mapping from TLB0. */ 1637 tlb0_flush_entry(pmap, va); 1638 } 1639 } 1640 PMAP_UNLOCK(pmap); 1641 vm_page_unlock_queues(); 1642 1643 //debugf("mmu_booke_remove: e\n"); 1644 } 1645 1646 /* 1647 * Remove physical page from all pmaps in which it resides. 1648 */ 1649 static void 1650 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1651 { 1652 pv_entry_t pv, pvn; 1653 u_int8_t hold_flag; 1654 1655 //debugf("mmu_booke_remove_all: s\n"); 1656 1657 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1658 1659 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1660 pvn = TAILQ_NEXT(pv, pv_link); 1661 1662 PMAP_LOCK(pv->pv_pmap); 1663 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1664 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1665 1666 /* Flush mapping from TLB0. */ 1667 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 1668 PMAP_UNLOCK(pv->pv_pmap); 1669 } 1670 vm_page_flag_clear(m, PG_WRITEABLE); 1671 1672 //debugf("mmu_booke_remove_all: e\n"); 1673 } 1674 1675 /* 1676 * Map a range of physical addresses into kernel virtual address space. 1677 * 1678 * The value passed in *virt is a suggested virtual address for the mapping. 1679 * Architectures which can support a direct-mapped physical to virtual region 1680 * can return the appropriate address within that region, leaving '*virt' 1681 * unchanged. We cannot and therefore do not; *virt is updated with the 1682 * first usable address after the mapped region. 1683 */ 1684 static vm_offset_t 1685 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1686 vm_offset_t pa_end, int prot) 1687 { 1688 vm_offset_t sva = *virt; 1689 vm_offset_t va = sva; 1690 1691 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1692 // sva, pa_start, pa_end); 1693 1694 while (pa_start < pa_end) { 1695 mmu_booke_kenter(mmu, va, pa_start); 1696 va += PAGE_SIZE; 1697 pa_start += PAGE_SIZE; 1698 } 1699 *virt = va; 1700 1701 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1702 return (sva); 1703 } 1704 1705 /* 1706 * The pmap must be activated before it's address space can be accessed in any 1707 * way. 1708 */ 1709 static void 1710 mmu_booke_activate(mmu_t mmu, struct thread *td) 1711 { 1712 pmap_t pmap; 1713 1714 pmap = &td->td_proc->p_vmspace->vm_pmap; 1715 1716 //debugf("mmu_booke_activate: s (proc = '%s', id = %d, pmap = 0x%08x)\n", 1717 // td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1718 1719 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1720 1721 mtx_lock_spin(&sched_lock); 1722 1723 pmap->pm_active |= PCPU_GET(cpumask); 1724 PCPU_SET(curpmap, pmap); 1725 1726 if (!pmap->pm_tid) 1727 tid_alloc(pmap); 1728 1729 /* Load PID0 register with pmap tid value. */ 1730 load_pid0(pmap->pm_tid); 1731 1732 mtx_unlock_spin(&sched_lock); 1733 1734 //debugf("mmu_booke_activate: e (tid = %d for '%s')\n", pmap->pm_tid, 1735 // td->td_proc->p_comm); 1736 } 1737 1738 /* 1739 * Deactivate the specified process's address space. 1740 */ 1741 static void 1742 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1743 { 1744 pmap_t pmap; 1745 1746 pmap = &td->td_proc->p_vmspace->vm_pmap; 1747 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1748 PCPU_SET(curpmap, NULL); 1749 } 1750 1751 /* 1752 * Copy the range specified by src_addr/len 1753 * from the source map to the range dst_addr/len 1754 * in the destination map. 1755 * 1756 * This routine is only advisory and need not do anything. 1757 */ 1758 static void 1759 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1760 vm_size_t len, vm_offset_t src_addr) 1761 { 1762 1763 } 1764 1765 /* 1766 * Set the physical protection on the specified range of this map as requested. 1767 */ 1768 static void 1769 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1770 vm_prot_t prot) 1771 { 1772 vm_offset_t va; 1773 vm_page_t m; 1774 pte_t *pte; 1775 1776 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1777 mmu_booke_remove(mmu, pmap, sva, eva); 1778 return; 1779 } 1780 1781 if (prot & VM_PROT_WRITE) 1782 return; 1783 1784 vm_page_lock_queues(); 1785 PMAP_LOCK(pmap); 1786 for (va = sva; va < eva; va += PAGE_SIZE) { 1787 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1788 if (PTE_ISVALID(pte)) { 1789 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1790 1791 /* Handle modified pages. */ 1792 if (PTE_ISMODIFIED(pte)) 1793 vm_page_dirty(m); 1794 1795 /* Referenced pages. */ 1796 if (PTE_ISREFERENCED(pte)) 1797 vm_page_flag_set(m, PG_REFERENCED); 1798 1799 /* Flush mapping from TLB0. */ 1800 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1801 PTE_REFERENCED); 1802 tlb0_flush_entry(pmap, va); 1803 } 1804 } 1805 } 1806 PMAP_UNLOCK(pmap); 1807 vm_page_unlock_queues(); 1808 } 1809 1810 /* 1811 * Clear the write and modified bits in each of the given page's mappings. 1812 */ 1813 static void 1814 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1815 { 1816 pv_entry_t pv; 1817 pte_t *pte; 1818 1819 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1820 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1821 (m->flags & PG_WRITEABLE) == 0) 1822 return; 1823 1824 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1825 PMAP_LOCK(pv->pv_pmap); 1826 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1827 if (PTE_ISVALID(pte)) { 1828 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1829 1830 /* Handle modified pages. */ 1831 if (PTE_ISMODIFIED(pte)) 1832 vm_page_dirty(m); 1833 1834 /* Referenced pages. */ 1835 if (PTE_ISREFERENCED(pte)) 1836 vm_page_flag_set(m, PG_REFERENCED); 1837 1838 /* Flush mapping from TLB0. */ 1839 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1840 PTE_REFERENCED); 1841 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 1842 } 1843 } 1844 PMAP_UNLOCK(pv->pv_pmap); 1845 } 1846 vm_page_flag_clear(m, PG_WRITEABLE); 1847 } 1848 1849 static boolean_t 1850 mmu_booke_page_executable(mmu_t mmu, vm_page_t m) 1851 { 1852 pv_entry_t pv; 1853 pte_t *pte; 1854 boolean_t executable; 1855 1856 executable = FALSE; 1857 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1858 PMAP_LOCK(pv->pv_pmap); 1859 pte = pte_find(mmu, pv->pv_pmap, pv->pv_va); 1860 if (pte != NULL && PTE_ISVALID(pte) && (pte->flags & PTE_UX)) 1861 executable = TRUE; 1862 PMAP_UNLOCK(pv->pv_pmap); 1863 if (executable) 1864 break; 1865 } 1866 1867 return (executable); 1868 } 1869 1870 /* 1871 * Atomically extract and hold the physical page with the given 1872 * pmap and virtual address pair if that mapping permits the given 1873 * protection. 1874 */ 1875 static vm_page_t 1876 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 1877 vm_prot_t prot) 1878 { 1879 pte_t *pte; 1880 vm_page_t m; 1881 u_int32_t pte_wbit; 1882 1883 m = NULL; 1884 vm_page_lock_queues(); 1885 PMAP_LOCK(pmap); 1886 pte = pte_find(mmu, pmap, va); 1887 1888 if ((pte != NULL) && PTE_ISVALID(pte)) { 1889 if (pmap == kernel_pmap) 1890 pte_wbit = PTE_SW; 1891 else 1892 pte_wbit = PTE_UW; 1893 1894 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 1895 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1896 vm_page_hold(m); 1897 } 1898 } 1899 1900 vm_page_unlock_queues(); 1901 PMAP_UNLOCK(pmap); 1902 return (m); 1903 } 1904 1905 /* 1906 * Initialize a vm_page's machine-dependent fields. 1907 */ 1908 static void 1909 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 1910 { 1911 1912 TAILQ_INIT(&m->md.pv_list); 1913 } 1914 1915 /* 1916 * mmu_booke_zero_page_area zeros the specified hardware page by 1917 * mapping it into virtual memory and using bzero to clear 1918 * its contents. 1919 * 1920 * off and size must reside within a single page. 1921 */ 1922 static void 1923 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1924 { 1925 vm_offset_t va; 1926 1927 //debugf("mmu_booke_zero_page_area: s\n"); 1928 1929 mtx_lock(&zero_page_mutex); 1930 va = zero_page_va; 1931 1932 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 1933 bzero((caddr_t)va + off, size); 1934 mmu_booke_kremove(mmu, va); 1935 1936 mtx_unlock(&zero_page_mutex); 1937 1938 //debugf("mmu_booke_zero_page_area: e\n"); 1939 } 1940 1941 /* 1942 * mmu_booke_zero_page zeros the specified hardware page. 1943 */ 1944 static void 1945 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 1946 { 1947 1948 //debugf("mmu_booke_zero_page: s\n"); 1949 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 1950 //debugf("mmu_booke_zero_page: e\n"); 1951 } 1952 1953 /* 1954 * mmu_booke_copy_page copies the specified (machine independent) page by 1955 * mapping the page into virtual memory and using memcopy to copy the page, 1956 * one machine dependent page at a time. 1957 */ 1958 static void 1959 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 1960 { 1961 vm_offset_t sva, dva; 1962 1963 //debugf("mmu_booke_copy_page: s\n"); 1964 1965 mtx_lock(©_page_mutex); 1966 sva = copy_page_src_va; 1967 dva = copy_page_dst_va; 1968 1969 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 1970 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 1971 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 1972 mmu_booke_kremove(mmu, dva); 1973 mmu_booke_kremove(mmu, sva); 1974 1975 mtx_unlock(©_page_mutex); 1976 1977 //debugf("mmu_booke_copy_page: e\n"); 1978 } 1979 1980 #if 0 1981 /* 1982 * Remove all pages from specified address space, this aids process exit 1983 * speeds. This is much faster than mmu_booke_remove in the case of running 1984 * down an entire address space. Only works for the current pmap. 1985 */ 1986 void 1987 mmu_booke_remove_pages(pmap_t pmap) 1988 { 1989 } 1990 #endif 1991 1992 /* 1993 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 1994 * into virtual memory and using bzero to clear its contents. This is intended 1995 * to be called from the vm_pagezero process only and outside of Giant. No 1996 * lock is required. 1997 */ 1998 static void 1999 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2000 { 2001 vm_offset_t va; 2002 2003 //debugf("mmu_booke_zero_page_idle: s\n"); 2004 2005 va = zero_page_idle_va; 2006 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2007 bzero((caddr_t)va, PAGE_SIZE); 2008 mmu_booke_kremove(mmu, va); 2009 2010 //debugf("mmu_booke_zero_page_idle: e\n"); 2011 } 2012 2013 /* 2014 * Return whether or not the specified physical page was modified 2015 * in any of physical maps. 2016 */ 2017 static boolean_t 2018 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2019 { 2020 pte_t *pte; 2021 pv_entry_t pv; 2022 2023 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2024 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2025 return (FALSE); 2026 2027 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2028 PMAP_LOCK(pv->pv_pmap); 2029 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2030 if (!PTE_ISVALID(pte)) 2031 goto make_sure_to_unlock; 2032 2033 if (PTE_ISMODIFIED(pte)) { 2034 PMAP_UNLOCK(pv->pv_pmap); 2035 return (TRUE); 2036 } 2037 } 2038 make_sure_to_unlock: 2039 PMAP_UNLOCK(pv->pv_pmap); 2040 } 2041 return (FALSE); 2042 } 2043 2044 /* 2045 * Return whether or not the specified virtual address is elgible 2046 * for prefault. 2047 */ 2048 static boolean_t 2049 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2050 { 2051 2052 return (FALSE); 2053 } 2054 2055 /* 2056 * Clear the modify bits on the specified physical page. 2057 */ 2058 static void 2059 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2060 { 2061 pte_t *pte; 2062 pv_entry_t pv; 2063 2064 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2065 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2066 return; 2067 2068 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2069 PMAP_LOCK(pv->pv_pmap); 2070 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2071 if (!PTE_ISVALID(pte)) 2072 goto make_sure_to_unlock; 2073 2074 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2075 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2076 PTE_REFERENCED); 2077 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2078 } 2079 } 2080 make_sure_to_unlock: 2081 PMAP_UNLOCK(pv->pv_pmap); 2082 } 2083 } 2084 2085 /* 2086 * Return a count of reference bits for a page, clearing those bits. 2087 * It is not necessary for every reference bit to be cleared, but it 2088 * is necessary that 0 only be returned when there are truly no 2089 * reference bits set. 2090 * 2091 * XXX: The exact number of bits to check and clear is a matter that 2092 * should be tested and standardized at some point in the future for 2093 * optimal aging of shared pages. 2094 */ 2095 static int 2096 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2097 { 2098 pte_t *pte; 2099 pv_entry_t pv; 2100 int count; 2101 2102 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2103 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2104 return (0); 2105 2106 count = 0; 2107 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2108 PMAP_LOCK(pv->pv_pmap); 2109 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2110 if (!PTE_ISVALID(pte)) 2111 goto make_sure_to_unlock; 2112 2113 if (PTE_ISREFERENCED(pte)) { 2114 pte->flags &= ~PTE_REFERENCED; 2115 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2116 2117 if (++count > 4) { 2118 PMAP_UNLOCK(pv->pv_pmap); 2119 break; 2120 } 2121 } 2122 } 2123 make_sure_to_unlock: 2124 PMAP_UNLOCK(pv->pv_pmap); 2125 } 2126 return (count); 2127 } 2128 2129 /* 2130 * Clear the reference bit on the specified physical page. 2131 */ 2132 static void 2133 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2134 { 2135 pte_t *pte; 2136 pv_entry_t pv; 2137 2138 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2139 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2140 return; 2141 2142 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2143 PMAP_LOCK(pv->pv_pmap); 2144 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2145 if (!PTE_ISVALID(pte)) 2146 goto make_sure_to_unlock; 2147 2148 if (PTE_ISREFERENCED(pte)) { 2149 pte->flags &= ~PTE_REFERENCED; 2150 tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2151 } 2152 } 2153 make_sure_to_unlock: 2154 PMAP_UNLOCK(pv->pv_pmap); 2155 } 2156 } 2157 2158 /* 2159 * Change wiring attribute for a map/virtual-address pair. 2160 */ 2161 static void 2162 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2163 { 2164 pte_t *pte;; 2165 2166 PMAP_LOCK(pmap); 2167 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2168 if (wired) { 2169 if (!PTE_ISWIRED(pte)) { 2170 pte->flags |= PTE_WIRED; 2171 pmap->pm_stats.wired_count++; 2172 } 2173 } else { 2174 if (PTE_ISWIRED(pte)) { 2175 pte->flags &= ~PTE_WIRED; 2176 pmap->pm_stats.wired_count--; 2177 } 2178 } 2179 } 2180 PMAP_UNLOCK(pmap); 2181 } 2182 2183 /* 2184 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2185 * page. This count may be changed upwards or downwards in the future; it is 2186 * only necessary that true be returned for a small subset of pmaps for proper 2187 * page aging. 2188 */ 2189 static boolean_t 2190 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2191 { 2192 pv_entry_t pv; 2193 int loops; 2194 2195 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2196 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2197 return (FALSE); 2198 2199 loops = 0; 2200 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2201 2202 if (pv->pv_pmap == pmap) 2203 return (TRUE); 2204 2205 if (++loops >= 16) 2206 break; 2207 } 2208 return (FALSE); 2209 } 2210 2211 /* 2212 * Return the number of managed mappings to the given physical page that are 2213 * wired. 2214 */ 2215 static int 2216 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2217 { 2218 pv_entry_t pv; 2219 pte_t *pte; 2220 int count = 0; 2221 2222 if ((m->flags & PG_FICTITIOUS) != 0) 2223 return (count); 2224 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2225 2226 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2227 PMAP_LOCK(pv->pv_pmap); 2228 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2229 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2230 count++; 2231 PMAP_UNLOCK(pv->pv_pmap); 2232 } 2233 2234 return (count); 2235 } 2236 2237 static int 2238 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2239 { 2240 int i; 2241 vm_offset_t va; 2242 2243 /* 2244 * This currently does not work for entries that 2245 * overlap TLB1 entries. 2246 */ 2247 for (i = 0; i < tlb1_idx; i ++) { 2248 if (tlb1_iomapped(i, pa, size, &va) == 0) 2249 return (0); 2250 } 2251 2252 return (EFAULT); 2253 } 2254 2255 /* 2256 * Map a set of physical memory pages into the kernel virtual address space. 2257 * Return a pointer to where it is mapped. This routine is intended to be used 2258 * for mapping device memory, NOT real memory. 2259 */ 2260 static void * 2261 mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2262 { 2263 uintptr_t va; 2264 2265 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2266 if (bootverbose) 2267 printf("Wiring VA=%x to PA=%x (size=%x), using TLB1[%d]\n", 2268 va, pa, size, tlb1_idx); 2269 tlb1_set_entry(va, pa, size, _TLB_ENTRY_IO); 2270 return ((void *)va); 2271 } 2272 2273 /* 2274 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2275 */ 2276 static void 2277 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2278 { 2279 vm_offset_t base, offset; 2280 2281 //debugf("mmu_booke_unmapdev: s (va = 0x%08x)\n", va); 2282 2283 /* 2284 * Unmap only if this is inside kernel virtual space. 2285 */ 2286 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2287 base = trunc_page(va); 2288 offset = va & PAGE_MASK; 2289 size = roundup(offset + size, PAGE_SIZE); 2290 kmem_free(kernel_map, base, size); 2291 } 2292 2293 //debugf("mmu_booke_unmapdev: e\n"); 2294 } 2295 2296 /* 2297 * mmu_booke_object_init_pt preloads the ptes for a given object 2298 * into the specified pmap. This eliminates the blast of soft 2299 * faults on process startup and immediately after an mmap. 2300 */ 2301 static void 2302 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2303 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2304 { 2305 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2306 KASSERT(object->type == OBJT_DEVICE, 2307 ("mmu_booke_object_init_pt: non-device object")); 2308 } 2309 2310 /* 2311 * Perform the pmap work for mincore. 2312 */ 2313 static int 2314 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2315 { 2316 2317 TODO; 2318 return (0); 2319 } 2320 2321 /**************************************************************************/ 2322 /* TID handling */ 2323 /**************************************************************************/ 2324 /* 2325 * Flush all entries from TLB0 matching given tid. 2326 */ 2327 static void 2328 tid_flush(tlbtid_t tid) 2329 { 2330 int i, entryidx, way; 2331 2332 //debugf("tid_flush: s (tid = %d)\n", tid); 2333 2334 mtx_lock_spin(&tlb0_mutex); 2335 2336 for (i = 0; i < TLB0_SIZE; i++) { 2337 if (MAS1_GETTID(tlb0[i].mas1) == tid) { 2338 way = i / TLB0_ENTRIES_PER_WAY; 2339 entryidx = i - (way * TLB0_ENTRIES_PER_WAY); 2340 2341 //debugf("tid_flush: inval tlb0 entry %d\n", i); 2342 tlb0_inval_entry(entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT, way); 2343 } 2344 } 2345 2346 mtx_unlock_spin(&tlb0_mutex); 2347 2348 //debugf("tid_flush: e\n"); 2349 } 2350 2351 /* 2352 * Allocate a TID. If necessary, steal one from someone else. 2353 * The new TID is flushed from the TLB before returning. 2354 */ 2355 static tlbtid_t 2356 tid_alloc(pmap_t pmap) 2357 { 2358 tlbtid_t tid; 2359 static tlbtid_t next_tid = TID_MIN; 2360 2361 //struct thread *td; 2362 //struct proc *p; 2363 2364 //td = PCPU_GET(curthread); 2365 //p = td->td_proc; 2366 //debugf("tid_alloc: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 2367 //printf("tid_alloc: proc %d '%s'\n", p->p_pid, p->p_comm); 2368 2369 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2370 2371 /* 2372 * Find a likely TID, allocate unused if possible, 2373 * skip reserved entries. 2374 */ 2375 tid = next_tid; 2376 while (tidbusy[tid] != NULL) { 2377 if (tid == next_tid) 2378 break; 2379 2380 if (tid == TID_MAX) 2381 tid = TID_MIN; 2382 else 2383 tid++; 2384 2385 } 2386 2387 /* Now clean it out */ 2388 tid_flush(tid); 2389 2390 /* If we are stealing pmap then clear its tid */ 2391 if (tidbusy[tid]) { 2392 //debugf("warning: stealing tid %d\n", tid); 2393 tidbusy[tid]->pm_tid = 0; 2394 } 2395 2396 /* Calculate next tid */ 2397 if (tid == TID_MAX) 2398 next_tid = TID_MIN; 2399 else 2400 next_tid = tid + 1; 2401 2402 tidbusy[tid] = pmap; 2403 pmap->pm_tid = tid; 2404 2405 //debugf("tid_alloc: e (%02d next = %02d)\n", tid, next_tid); 2406 return (tid); 2407 } 2408 2409 #if 0 2410 /* 2411 * Free this pmap's TID. 2412 */ 2413 static void 2414 tid_free(pmap_t pmap) 2415 { 2416 tlbtid_t oldtid; 2417 2418 oldtid = pmap->pm_tid; 2419 2420 if (oldtid == 0) { 2421 panic("tid_free: freeing kernel tid"); 2422 } 2423 2424 #ifdef DEBUG 2425 if (tidbusy[oldtid] == 0) 2426 debugf("tid_free: freeing free tid %d\n", oldtid); 2427 if (tidbusy[oldtid] != pmap) { 2428 debugf("tid_free: freeing someone esle's tid\n " 2429 "tidbusy[%d] = 0x%08x pmap = 0x%08x\n", 2430 oldtid, (u_int32_t)tidbusy[oldtid], (u_int32_t)pmap); 2431 } 2432 #endif 2433 2434 tidbusy[oldtid] = NULL; 2435 tid_flush(oldtid); 2436 } 2437 #endif 2438 2439 #if 0 2440 #if DEBUG 2441 static void 2442 tid_print_busy(void) 2443 { 2444 int i; 2445 2446 for (i = 0; i < TID_MAX; i++) { 2447 debugf("tid %d = pmap 0x%08x", i, (u_int32_t)tidbusy[i]); 2448 if (tidbusy[i]) 2449 debugf(" pmap->tid = %d", tidbusy[i]->pm_tid); 2450 debugf("\n"); 2451 } 2452 2453 } 2454 #endif /* DEBUG */ 2455 #endif 2456 2457 /**************************************************************************/ 2458 /* TLB0 handling */ 2459 /**************************************************************************/ 2460 2461 static void 2462 tlb_print_entry(int i, u_int32_t mas1, u_int32_t mas2, u_int32_t mas3, u_int32_t mas7) 2463 { 2464 int as; 2465 char desc[3]; 2466 tlbtid_t tid; 2467 vm_size_t size; 2468 unsigned int tsize; 2469 2470 desc[2] = '\0'; 2471 if (mas1 & MAS1_VALID) 2472 desc[0] = 'V'; 2473 else 2474 desc[0] = ' '; 2475 2476 if (mas1 & MAS1_IPROT) 2477 desc[1] = 'P'; 2478 else 2479 desc[1] = ' '; 2480 2481 as = (mas1 & MAS1_TS) ? 1 : 0; 2482 tid = MAS1_GETTID(mas1); 2483 2484 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2485 size = 0; 2486 if (tsize) 2487 size = tsize2size(tsize); 2488 2489 debugf("%3d: (%s) [AS=%d] " 2490 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2491 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2492 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2493 } 2494 2495 /* Convert TLB0 va and way number to tlb0[] table index. */ 2496 static inline unsigned int 2497 tlb0_tableidx(vm_offset_t va, unsigned int way) 2498 { 2499 unsigned int idx; 2500 2501 idx = (way * TLB0_ENTRIES_PER_WAY); 2502 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2503 return (idx); 2504 } 2505 2506 /* 2507 * Write given entry to TLB0 hardware. 2508 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2509 */ 2510 static void 2511 tlb0_write_entry(unsigned int idx, unsigned int way) 2512 { 2513 u_int32_t mas0, mas7, nv; 2514 2515 /* Clear high order RPN bits. */ 2516 mas7 = 0; 2517 2518 /* Preserve NV. */ 2519 mas0 = mfspr(SPR_MAS0); 2520 nv = mas0 & (TLB0_NWAYS - 1); 2521 2522 /* Select entry. */ 2523 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way) | nv; 2524 2525 //debugf("tlb0_write_entry: s (idx=%d way=%d mas0=0x%08x " 2526 // "mas1=0x%08x mas2=0x%08x mas3=0x%08x)\n", 2527 // idx, way, mas0, tlb0[idx].mas1, 2528 // tlb0[idx].mas2, tlb0[idx].mas3); 2529 2530 mtspr(SPR_MAS0, mas0); 2531 __asm volatile("isync"); 2532 mtspr(SPR_MAS1, tlb0[idx].mas1); 2533 __asm volatile("isync"); 2534 mtspr(SPR_MAS2, tlb0[idx].mas2); 2535 __asm volatile("isync"); 2536 mtspr(SPR_MAS3, tlb0[idx].mas3); 2537 __asm volatile("isync"); 2538 mtspr(SPR_MAS7, mas7); 2539 __asm volatile("isync; tlbwe; isync; msync"); 2540 2541 //debugf("tlb0_write_entry: e\n"); 2542 } 2543 2544 /* 2545 * Invalidate TLB0 entry, clear correspondig tlb0 table element. 2546 */ 2547 static void 2548 tlb0_inval_entry(vm_offset_t va, unsigned int way) 2549 { 2550 int idx = tlb0_tableidx(va, way); 2551 2552 //debugf("tlb0_inval_entry: s (va=0x%08x way=%d idx=%d)\n", 2553 // va, way, idx); 2554 2555 tlb0[idx].mas1 = 1 << MAS1_TSIZE_SHIFT; /* !MAS1_VALID */ 2556 tlb0[idx].mas2 = va & MAS2_EPN; 2557 tlb0[idx].mas3 = 0; 2558 2559 tlb0_write_entry(idx, way); 2560 2561 //debugf("tlb0_inval_entry: e\n"); 2562 } 2563 2564 /* 2565 * Invalidate TLB0 entry that corresponds to pmap/va. 2566 */ 2567 static void 2568 tlb0_flush_entry(pmap_t pmap, vm_offset_t va) 2569 { 2570 int idx, way; 2571 2572 //debugf("tlb0_flush_entry: s (pmap=0x%08x va=0x%08x)\n", 2573 // (u_int32_t)pmap, va); 2574 2575 mtx_lock_spin(&tlb0_mutex); 2576 2577 /* Check all TLB0 ways. */ 2578 for (way = 0; way < TLB0_NWAYS; way ++) { 2579 idx = tlb0_tableidx(va, way); 2580 2581 /* Invalidate only if entry matches va and pmap tid. */ 2582 if (((MAS1_GETTID(tlb0[idx].mas1) == pmap->pm_tid) && 2583 ((tlb0[idx].mas2 & MAS2_EPN) == va))) { 2584 tlb0_inval_entry(va, way); 2585 } 2586 } 2587 2588 mtx_unlock_spin(&tlb0_mutex); 2589 2590 //debugf("tlb0_flush_entry: e\n"); 2591 } 2592 2593 /* Clean TLB0 hardware and tlb0[] table. */ 2594 static void 2595 tlb0_init(void) 2596 { 2597 int entryidx, way; 2598 2599 debugf("tlb0_init: TLB0_SIZE = %d TLB0_NWAYS = %d\n", 2600 TLB0_SIZE, TLB0_NWAYS); 2601 2602 mtx_lock_spin(&tlb0_mutex); 2603 2604 for (way = 0; way < TLB0_NWAYS; way ++) { 2605 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2606 tlb0_inval_entry(entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT, way); 2607 } 2608 } 2609 2610 mtx_unlock_spin(&tlb0_mutex); 2611 } 2612 2613 #if 0 2614 #if DEBUG 2615 /* Print out tlb0 entries for given va. */ 2616 static void 2617 tlb0_print_tlbentries_va(vm_offset_t va) 2618 { 2619 u_int32_t mas0, mas1, mas2, mas3, mas7; 2620 int way, idx; 2621 2622 debugf("TLB0 entries for va = 0x%08x:\n", va); 2623 for (way = 0; way < TLB0_NWAYS; way ++) { 2624 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2625 mtspr(SPR_MAS0, mas0); 2626 __asm volatile("isync"); 2627 2628 mas2 = va & MAS2_EPN; 2629 mtspr(SPR_MAS2, mas2); 2630 __asm volatile("isync; tlbre"); 2631 2632 mas1 = mfspr(SPR_MAS1); 2633 mas2 = mfspr(SPR_MAS2); 2634 mas3 = mfspr(SPR_MAS3); 2635 mas7 = mfspr(SPR_MAS7); 2636 2637 idx = tlb0_tableidx(va, way); 2638 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2639 } 2640 } 2641 2642 /* Print out contents of the MAS registers for each TLB0 entry */ 2643 static void 2644 tlb0_print_tlbentries(void) 2645 { 2646 u_int32_t mas0, mas1, mas2, mas3, mas7; 2647 int entryidx, way, idx; 2648 2649 debugf("TLB0 entries:\n"); 2650 for (way = 0; way < TLB0_NWAYS; way ++) { 2651 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2652 2653 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2654 mtspr(SPR_MAS0, mas0); 2655 __asm volatile("isync"); 2656 2657 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2658 mtspr(SPR_MAS2, mas2); 2659 2660 __asm volatile("isync; tlbre"); 2661 2662 mas1 = mfspr(SPR_MAS1); 2663 mas2 = mfspr(SPR_MAS2); 2664 mas3 = mfspr(SPR_MAS3); 2665 mas7 = mfspr(SPR_MAS7); 2666 2667 idx = tlb0_tableidx(mas2, way); 2668 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2669 } 2670 } 2671 } 2672 2673 /* Print out kernel tlb0[] table. */ 2674 static void 2675 tlb0_print_entries(void) 2676 { 2677 int i; 2678 2679 debugf("tlb0[] table entries:\n"); 2680 for (i = 0; i < TLB0_SIZE; i++) { 2681 tlb_print_entry(i, tlb0[i].mas1, 2682 tlb0[i].mas2, tlb0[i].mas3, 0); 2683 } 2684 } 2685 #endif /* DEBUG */ 2686 #endif 2687 2688 /**************************************************************************/ 2689 /* TLB1 handling */ 2690 /**************************************************************************/ 2691 /* 2692 * Write given entry to TLB1 hardware. 2693 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2694 */ 2695 static void 2696 tlb1_write_entry(unsigned int idx) 2697 { 2698 u_int32_t mas0, mas7; 2699 2700 //debugf("tlb1_write_entry: s\n"); 2701 2702 /* Clear high order RPN bits */ 2703 mas7 = 0; 2704 2705 /* Select entry */ 2706 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2707 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2708 2709 mtspr(SPR_MAS0, mas0); 2710 __asm volatile("isync"); 2711 mtspr(SPR_MAS1, tlb1[idx].mas1); 2712 __asm volatile("isync"); 2713 mtspr(SPR_MAS2, tlb1[idx].mas2); 2714 __asm volatile("isync"); 2715 mtspr(SPR_MAS3, tlb1[idx].mas3); 2716 __asm volatile("isync"); 2717 mtspr(SPR_MAS7, mas7); 2718 __asm volatile("isync; tlbwe; isync; msync"); 2719 2720 //debugf("tlb1_write_entry: e\n");; 2721 } 2722 2723 /* 2724 * Return the largest uint value log such that 2^log <= num. 2725 */ 2726 static unsigned int 2727 ilog2(unsigned int num) 2728 { 2729 int lz; 2730 2731 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2732 return (31 - lz); 2733 } 2734 2735 /* 2736 * Convert TLB TSIZE value to mapped region size. 2737 */ 2738 static vm_size_t 2739 tsize2size(unsigned int tsize) 2740 { 2741 2742 /* 2743 * size = 4^tsize KB 2744 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2745 */ 2746 2747 return ((1 << (2 * tsize)) * 1024); 2748 } 2749 2750 /* 2751 * Convert region size (must be power of 4) to TLB TSIZE value. 2752 */ 2753 static unsigned int 2754 size2tsize(vm_size_t size) 2755 { 2756 2757 /* 2758 * tsize = log2(size) / 2 - 5 2759 */ 2760 2761 return (ilog2(size) / 2 - 5); 2762 } 2763 2764 /* 2765 * Setup entry in a sw tlb1 table, write entry to TLB1 hardware. 2766 * This routine is used for low level operations on the TLB1, 2767 * for creating temporaray as well as permanent mappings (tlb_set_entry). 2768 * 2769 * We assume kernel mappings only, thus all entries created have supervisor 2770 * permission bits set nad user permission bits cleared. 2771 * 2772 * Provided mapping size must be a power of 4. 2773 * Mapping flags must be a combination of MAS2_[WIMG]. 2774 * Entry TID is set to _tid which must not exceed 8 bit value. 2775 * Entry TS is set to either 0 or MAS1_TS based on provided _ts. 2776 */ 2777 static void 2778 __tlb1_set_entry(unsigned int idx, vm_offset_t va, vm_offset_t pa, 2779 vm_size_t size, u_int32_t flags, unsigned int _tid, unsigned int _ts) 2780 { 2781 int tsize; 2782 u_int32_t ts, tid; 2783 2784 //debugf("__tlb1_set_entry: s (idx = %d va = 0x%08x pa = 0x%08x " 2785 // "size = 0x%08x flags = 0x%08x _tid = %d _ts = %d\n", 2786 // idx, va, pa, size, flags, _tid, _ts); 2787 2788 /* Convert size to TSIZE */ 2789 tsize = size2tsize(size); 2790 //debugf("__tlb1_set_entry: tsize = %d\n", tsize); 2791 2792 tid = (_tid << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2793 ts = (_ts) ? MAS1_TS : 0; 2794 tlb1[idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2795 tlb1[idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2796 2797 tlb1[idx].mas2 = (va & MAS2_EPN) | flags; 2798 2799 /* Set supervisor rwx permission bits */ 2800 tlb1[idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2801 2802 //debugf("__tlb1_set_entry: mas1 = %08x mas2 = %08x mas3 = 0x%08x\n", 2803 // tlb1[idx].mas1, tlb1[idx].mas2, tlb1[idx].mas3); 2804 2805 tlb1_write_entry(idx); 2806 //debugf("__tlb1_set_entry: e\n"); 2807 } 2808 2809 /* 2810 * Register permanent kernel mapping in TLB1. 2811 * 2812 * Entries are created starting from index 0 (current free entry is 2813 * kept in tlb1_idx) and are not supposed to be invalidated. 2814 */ 2815 static int 2816 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, u_int32_t flags) 2817 { 2818 //debugf("tlb1_set_entry: s (tlb1_idx = %d va = 0x%08x pa = 0x%08x " 2819 // "size = 0x%08x flags = 0x%08x\n", 2820 // tlb1_idx, va, pa, size, flags); 2821 2822 if (tlb1_idx >= TLB1_SIZE) { 2823 //debugf("tlb1_set_entry: e (tlb1 full!)\n"); 2824 return (-1); 2825 } 2826 2827 /* TS = 0, TID = 0 */ 2828 __tlb1_set_entry(tlb1_idx++, va, pa, size, flags, KERNEL_TID, 0); 2829 //debugf("tlb1_set_entry: e\n"); 2830 return (0); 2831 } 2832 2833 /* 2834 * Invalidate TLB1 entry, clear correspondig tlb1 table element. 2835 * This routine is used to clear temporary entries created 2836 * early in a locore.S or through the use of __tlb1_set_entry(). 2837 */ 2838 void 2839 tlb1_inval_entry(unsigned int idx) 2840 { 2841 vm_offset_t va; 2842 2843 va = tlb1[idx].mas2 & MAS2_EPN; 2844 2845 tlb1[idx].mas1 = 0; /* !MAS1_VALID */ 2846 tlb1[idx].mas2 = 0; 2847 tlb1[idx].mas3 = 0; 2848 2849 tlb1_write_entry(idx); 2850 } 2851 2852 static int 2853 tlb1_entry_size_cmp(const void *a, const void *b) 2854 { 2855 const vm_size_t *sza; 2856 const vm_size_t *szb; 2857 2858 sza = a; 2859 szb = b; 2860 if (*sza > *szb) 2861 return (-1); 2862 else if (*sza < *szb) 2863 return (1); 2864 else 2865 return (0); 2866 } 2867 2868 /* 2869 * Mapin contiguous RAM region into the TLB1 using maximum of 2870 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2871 * 2872 * If necessarry round up last entry size and return total size 2873 * used by all allocated entries. 2874 */ 2875 vm_size_t 2876 tlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2877 { 2878 vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2879 vm_size_t mapped_size, sz, esz; 2880 unsigned int log; 2881 int i; 2882 2883 debugf("tlb1_mapin_region:\n"); 2884 debugf(" region size = 0x%08x va = 0x%08x pa = 0x%08x\n", size, va, pa); 2885 2886 mapped_size = 0; 2887 sz = size; 2888 memset(entry_size, 0, sizeof(entry_size)); 2889 2890 /* Calculate entry sizes. */ 2891 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2892 2893 /* Largest region that is power of 4 and fits within size */ 2894 log = ilog2(sz)/2; 2895 esz = 1 << (2 * log); 2896 2897 /* Minimum region size is 4KB */ 2898 if (esz < (1 << 12)) 2899 esz = 1 << 12; 2900 2901 /* If this is last entry cover remaining size. */ 2902 if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2903 while (esz < sz) 2904 esz = esz << 2; 2905 } 2906 2907 entry_size[i] = esz; 2908 mapped_size += esz; 2909 if (esz < sz) 2910 sz -= esz; 2911 else 2912 sz = 0; 2913 } 2914 2915 /* Sort entry sizes, required to get proper entry address alignment. */ 2916 qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2917 sizeof(vm_size_t), tlb1_entry_size_cmp); 2918 2919 /* Load TLB1 entries. */ 2920 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2921 esz = entry_size[i]; 2922 if (!esz) 2923 break; 2924 debugf(" entry %d: sz = 0x%08x (va = 0x%08x pa = 0x%08x)\n", 2925 tlb1_idx, esz, va, pa); 2926 tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2927 2928 va += esz; 2929 pa += esz; 2930 } 2931 2932 debugf(" mapped size 0x%08x (wasted space 0x%08x)\n", 2933 mapped_size, mapped_size - size); 2934 2935 return (mapped_size); 2936 } 2937 2938 /* 2939 * TLB1 initialization routine, to be called after the very first 2940 * assembler level setup done in locore.S. 2941 */ 2942 void 2943 tlb1_init(vm_offset_t ccsrbar) 2944 { 2945 uint32_t mas0; 2946 2947 /* TBL1[1] is used to map the kernel. Save that entry. */ 2948 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 2949 mtspr(SPR_MAS0, mas0); 2950 __asm __volatile("isync; tlbre"); 2951 2952 tlb1[1].mas1 = mfspr(SPR_MAS1); 2953 tlb1[1].mas2 = mfspr(SPR_MAS2); 2954 tlb1[1].mas3 = mfspr(SPR_MAS3); 2955 2956 /* Mapin CCSRBAR in TLB1[0] */ 2957 __tlb1_set_entry(0, CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, 2958 _TLB_ENTRY_IO, KERNEL_TID, 0); 2959 2960 /* Setup TLB miss defaults */ 2961 set_mas4_defaults(); 2962 2963 /* Reset next available TLB1 entry index. */ 2964 tlb1_idx = 2; 2965 } 2966 2967 /* 2968 * Setup MAS4 defaults. 2969 * These values are loaded to MAS0-2 on a TLB miss. 2970 */ 2971 static void 2972 set_mas4_defaults(void) 2973 { 2974 u_int32_t mas4; 2975 2976 /* Defaults: TLB0, PID0, TSIZED=4K */ 2977 mas4 = MAS4_TLBSELD0; 2978 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 2979 2980 mtspr(SPR_MAS4, mas4); 2981 __asm volatile("isync"); 2982 } 2983 2984 /* 2985 * Print out contents of the MAS registers for each TLB1 entry 2986 */ 2987 void 2988 tlb1_print_tlbentries(void) 2989 { 2990 u_int32_t mas0, mas1, mas2, mas3, mas7; 2991 int i; 2992 2993 debugf("TLB1 entries:\n"); 2994 for (i = 0; i < TLB1_SIZE; i++) { 2995 2996 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 2997 mtspr(SPR_MAS0, mas0); 2998 2999 __asm volatile("isync; tlbre"); 3000 3001 mas1 = mfspr(SPR_MAS1); 3002 mas2 = mfspr(SPR_MAS2); 3003 mas3 = mfspr(SPR_MAS3); 3004 mas7 = mfspr(SPR_MAS7); 3005 3006 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3007 } 3008 } 3009 3010 /* 3011 * Print out contents of the in-ram tlb1 table. 3012 */ 3013 void 3014 tlb1_print_entries(void) 3015 { 3016 int i; 3017 3018 debugf("tlb1[] table entries:\n"); 3019 for (i = 0; i < TLB1_SIZE; i++) 3020 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3021 } 3022 3023 /* 3024 * Return 0 if the physical IO range is encompassed by one of the 3025 * the TLB1 entries, otherwise return related error code. 3026 */ 3027 static int 3028 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3029 { 3030 u_int32_t prot; 3031 vm_paddr_t pa_start; 3032 vm_paddr_t pa_end; 3033 unsigned int entry_tsize; 3034 vm_size_t entry_size; 3035 3036 *va = (vm_offset_t)NULL; 3037 3038 /* Skip invalid entries */ 3039 if (!(tlb1[i].mas1 & MAS1_VALID)) 3040 return (EINVAL); 3041 3042 /* 3043 * The entry must be cache-inhibited, guarded, and r/w 3044 * so it can function as an i/o page 3045 */ 3046 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3047 if (prot != (MAS2_I | MAS2_G)) 3048 return (EPERM); 3049 3050 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3051 if (prot != (MAS3_SR | MAS3_SW)) 3052 return (EPERM); 3053 3054 /* The address should be within the entry range. */ 3055 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3056 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3057 3058 entry_size = tsize2size(entry_tsize); 3059 pa_start = tlb1[i].mas3 & MAS3_RPN; 3060 pa_end = pa_start + entry_size - 1; 3061 3062 if ((pa < pa_start) || ((pa + size) > pa_end)) 3063 return (ERANGE); 3064 3065 /* Return virtual address of this mapping. */ 3066 *va = (tlb1[i].mas2 & MAS2_EPN) + (pa - pa_start); 3067 return (0); 3068 } 3069